Lines Matching defs:LdSt

2849     const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps,
2852   if (!LdSt.mayLoadOrStore())
2857   if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, OffsetIsScalable,
3863     const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset,
3866   assert(LdSt.mayLoadOrStore() && "Expected a memory operation.");
3868   if (LdSt.getNumExplicitOperands() == 3) {
3870     if ((!LdSt.getOperand(1).isReg() && !LdSt.getOperand(1).isFI()) ||
3871         !LdSt.getOperand(2).isImm())
3873   } else if (LdSt.getNumExplicitOperands() == 4) {
3875     if (!LdSt.getOperand(1).isReg() ||
3876         (!LdSt.getOperand(2).isReg() && !LdSt.getOperand(2).isFI()) ||
3877         !LdSt.getOperand(3).isImm())
3888   if (!getMemOpInfo(LdSt.getOpcode(), Scale, Width, Dummy1, Dummy2))
3894   if (isPostIndexLdStOpcode(LdSt.getOpcode())) {
3895     BaseOp = &LdSt.getOperand(2);
3897   } else if (LdSt.getNumExplicitOperands() == 3) {
3898     BaseOp = &LdSt.getOperand(1);
3899     Offset = LdSt.getOperand(2).getImm() * Scale.getKnownMinValue();
3901     assert(LdSt.getNumExplicitOperands() == 4 && "invalid number of operands");
3902     BaseOp = &LdSt.getOperand(2);
3903     Offset = LdSt.getOperand(3).getImm() * Scale.getKnownMinValue();
3911 AArch64InstrInfo::getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const {
3912   assert(LdSt.mayLoadOrStore() && "Expected a memory operation.");
3913   MachineOperand &OfsOp = LdSt.getOperand(LdSt.getNumExplicitOperands() - 1);
4756 /// Only called for LdSt for which getMemOperandWithOffset returns true.