| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 1209 Register LHSReg = getRegForValue(LHS); emitAddSub() local
1299 emitAddSub_rr(bool UseAdd,MVT RetVT,unsigned LHSReg,unsigned RHSReg,bool SetFlags,bool WantResult) emitAddSub_rr() argument
1336 emitAddSub_ri(bool UseAdd,MVT RetVT,unsigned LHSReg,uint64_t Imm,bool SetFlags,bool WantResult) emitAddSub_ri() argument
1381 emitAddSub_rs(bool UseAdd,MVT RetVT,unsigned LHSReg,unsigned RHSReg,AArch64_AM::ShiftExtendType ShiftType,uint64_t ShiftImm,bool SetFlags,bool WantResult) emitAddSub_rs() argument
1423 emitAddSub_rx(bool UseAdd,MVT RetVT,unsigned LHSReg,unsigned RHSReg,AArch64_AM::ShiftExtendType ExtType,uint64_t ShiftImm,bool SetFlags,bool WantResult) emitAddSub_rx() argument
1495 emitICmp_ri(MVT RetVT,unsigned LHSReg,uint64_t Imm) emitICmp_ri() argument
1511 Register LHSReg = getRegForValue(LHS); emitFCmp() local
1568 emitSubs_rr(MVT RetVT,unsigned LHSReg,unsigned RHSReg,bool WantResult) emitSubs_rr() argument
1574 emitSubs_rs(MVT RetVT,unsigned LHSReg,unsigned RHSReg,AArch64_AM::ShiftExtendType ShiftType,uint64_t ShiftImm,bool WantResult) emitSubs_rs() argument
1599 Register LHSReg = getRegForValue(LHS); emitLogicalOp() local
1661 emitLogicalOp_ri(unsigned ISDOpc,MVT RetVT,unsigned LHSReg,uint64_t Imm) emitLogicalOp_ri() argument
1706 emitLogicalOp_rs(unsigned ISDOpc,MVT RetVT,unsigned LHSReg,unsigned RHSReg,uint64_t ShiftImm) emitLogicalOp_rs() argument
1747 emitAnd_ri(MVT RetVT,unsigned LHSReg,uint64_t Imm) emitAnd_ri() argument
3710 Register LHSReg = getRegForValue(LHS); fastLowerIntrinsicCall() local
3740 Register LHSReg = getRegForValue(LHS); fastLowerIntrinsicCall() local
3827 Register LHSReg = getRegForValue(II->getArgOperand(0)); fastLowerIntrinsicCall() local
[all...] |
| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 504 unsigned LHSReg, unsigned RHSReg, in validOpRegPair() argument
545 auto LHSReg = MIB.getReg(2); in selectCmp() local
578 insertComparison(CmpConstants Helper,InsertInfo I,unsigned ResReg,ARMCC::CondCodes Cond,unsigned LHSReg,unsigned RHSReg,unsigned PrevRes) const insertComparison() argument
[all...] |
| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 2131 Register LHSReg = getRegForValue(LHS); X86FastEmitCMoveSelect() local
2186 Register LHSReg = getRegForValue(LHS); X86FastEmitSSESelect() local
2331 Register LHSReg = getRegForValue(LHS); X86FastEmitPseudoSelect() local
2888 Register LHSReg = getRegForValue(LHS); fastLowerIntrinsicCall() local
3072 Register LHSReg = getRegForValue(LHS); fastLowerIntrinsicCall() local
[all...] |
| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 3118 Register LHSReg = MI.getOperand(1).getReg(); matchHoistLogicOpWithSameOpcodeHands() local
4898 Register LHSReg = MI.getOperand(1).getReg(); matchReassocCommBinOp() local
6026 Register LHSReg = MI.getOperand(1).getReg(); matchCombineFSubFNegFMulToFMadOrFMA() local
6073 Register LHSReg = MI.getOperand(1).getReg(); matchCombineFSubFpExtFMulToFMadOrFMA() local
6126 Register LHSReg = MI.getOperand(1).getReg(); matchCombineFSubFpExtFNegFMulToFMadOrFMA() local
6518 Register LHSReg = MI.getOperand(LHSOpndIdx).getReg(); applyCommuteBinOpOperands() local
[all...] |
| /llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 312 Register LHSReg = getRegForValue(LHS); emitLogicalOp() local
|