Lines Matching defs:LHSReg

206   unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
209   unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
212   unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
216   unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
225   bool emitICmp_ri(MVT RetVT, unsigned LHSReg, uint64_t Imm);
242   unsigned emitSubs_rr(MVT RetVT, unsigned LHSReg, unsigned RHSReg,
244   unsigned emitSubs_rs(MVT RetVT, unsigned LHSReg, unsigned RHSReg,
249   unsigned emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
251   unsigned emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
253   unsigned emitAnd_ri(MVT RetVT, unsigned LHSReg, uint64_t Imm);
1211   Register LHSReg = getRegForValue(LHS);
1212   if (!LHSReg)
1216     LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt);
1222       ResultReg = emitAddSub_ri(!UseAdd, RetVT, LHSReg, -Imm, SetFlags,
1225       ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, Imm, SetFlags,
1229       ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, 0, SetFlags, WantResult);
1240     return emitAddSub_rx(UseAdd, RetVT, LHSReg, RHSReg, ExtendType, 0,
1259       ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, RHSReg, AArch64_AM::LSL,
1282           ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, RHSReg, ShiftType,
1298   return emitAddSub_rr(UseAdd, RetVT, LHSReg, RHSReg, SetFlags, WantResult);
1301 unsigned AArch64FastISel::emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
1304   assert(LHSReg && RHSReg && "Invalid register number.");
1306   if (LHSReg == AArch64::SP || LHSReg == AArch64::WSP ||
1330   LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
1333       .addReg(LHSReg)
1338 unsigned AArch64FastISel::emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
1341   assert(LHSReg && "Invalid register number.");
1375   LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
1377       .addReg(LHSReg)
1383 unsigned AArch64FastISel::emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
1388   assert(LHSReg && RHSReg && "Invalid register number.");
1389   assert(LHSReg != AArch64::SP && LHSReg != AArch64::WSP &&
1416   LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
1419       .addReg(LHSReg)
1425 unsigned AArch64FastISel::emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
1430   assert(LHSReg && RHSReg && "Invalid register number.");
1431   assert(LHSReg != AArch64::XZR && LHSReg != AArch64::WZR &&
1460   LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
1463       .addReg(LHSReg)
1497 bool AArch64FastISel::emitICmp_ri(MVT RetVT, unsigned LHSReg, uint64_t Imm) {
1498   return emitAddSub_ri(/*UseAdd=*/false, RetVT, LHSReg, Imm,
1513   Register LHSReg = getRegForValue(LHS);
1514   if (!LHSReg)
1520         .addReg(LHSReg);
1530       .addReg(LHSReg)
1570 unsigned AArch64FastISel::emitSubs_rr(MVT RetVT, unsigned LHSReg,
1572   return emitAddSub_rr(/*UseAdd=*/false, RetVT, LHSReg, RHSReg,
1576 unsigned AArch64FastISel::emitSubs_rs(MVT RetVT, unsigned LHSReg,
1580   return emitAddSub_rs(/*UseAdd=*/false, RetVT, LHSReg, RHSReg, ShiftType,
1601   Register LHSReg = getRegForValue(LHS);
1602   if (!LHSReg)
1608     ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, Imm);
1629       ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal);
1643         ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal);
1654   ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, RHSReg);
1663                                            unsigned LHSReg, uint64_t Imm) {
1698       fastEmitInst_ri(Opc, RC, LHSReg,
1708                                            unsigned LHSReg, unsigned RHSReg,
1740       fastEmitInst_rri(Opc, RC, LHSReg, RHSReg,
1749 unsigned AArch64FastISel::emitAnd_ri(MVT RetVT, unsigned LHSReg,
1751   return emitLogicalOp_ri(ISD::AND, RetVT, LHSReg, Imm);
3716       Register LHSReg = getRegForValue(LHS);
3717       if (!LHSReg)
3725         MulReg = emitSMULL_rr(MVT::i64, LHSReg, RHSReg);
3735         // LHSReg and RHSReg cannot be killed by this Mul, since they are
3737         MulReg = emitMul_rr(VT, LHSReg, RHSReg);
3738         unsigned SMULHReg = fastEmit_rr(VT, VT, ISD::MULHS, LHSReg, RHSReg);
3746       Register LHSReg = getRegForValue(LHS);
3747       if (!LHSReg)
3755         MulReg = emitUMULL_rr(MVT::i64, LHSReg, RHSReg);
3764         // LHSReg and RHSReg cannot be killed by this Mul, since they are
3766         MulReg = emitMul_rr(VT, LHSReg, RHSReg);
3767         unsigned UMULHReg = fastEmit_rr(VT, VT, ISD::MULHU, LHSReg, RHSReg);
3833     Register LHSReg = getRegForValue(II->getArgOperand(0));
3835     if (!LHSReg || !RHSReg)
3839         fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, LHSReg, RHSReg);