| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCHazardRecognizers.h | 34 PPCDispatchGroupSBHazardRecognizer(const InstrItineraryData *ItinData, in PPCDispatchGroupSBHazardRecognizer()
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| H A D | PPCInstrInfo.h | 342 getOperandLatency(const InstrItineraryData * ItinData,SDNode * DefNode,unsigned DefIdx,SDNode * UseNode,unsigned UseIdx) getOperandLatency() argument
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| H A D | PPCInstrInfo.cpp | 138 getInstrLatency(const InstrItineraryData * ItinData,const MachineInstr & MI,unsigned * PredCost) const getInstrLatency() argument
169 getOperandLatency(const InstrItineraryData * ItinData,const MachineInstr & DefMI,unsigned DefIdx,const MachineInstr & UseMI,unsigned UseIdx) const getOperandLatency() argument
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| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ScoreboardHazardRecognizer.h | 95 const InstrItineraryData *ItinData; variable
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| /llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 1442 getOperandLatency(const InstrItineraryData * ItinData,SDNode * DefNode,unsigned DefIdx,SDNode * UseNode,unsigned UseIdx) const getOperandLatency() argument
1458 getInstrLatency(const InstrItineraryData * ItinData,SDNode * N) const getInstrLatency() argument
1473 getNumMicroOps(const InstrItineraryData * ItinData,const MachineInstr & MI) const getNumMicroOps() argument
1504 getInstrLatency(const InstrItineraryData * ItinData,const MachineInstr & MI,unsigned * PredCost) const getInstrLatency() argument
1518 const InstrItineraryData *ItinData = SchedModel.getInstrItineraries(); hasLowDefLatency() local
1644 getOperandLatency(const InstrItineraryData * ItinData,const MachineInstr & DefMI,unsigned DefIdx,const MachineInstr & UseMI,unsigned UseIdx) const getOperandLatency() argument
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| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 3461 getNumMicroOpsSwiftLdSt(const InstrItineraryData * ItinData,const MachineInstr & MI) getNumMicroOpsSwiftLdSt() argument
3763 getNumMicroOps(const InstrItineraryData * ItinData,const MachineInstr & MI) const getNumMicroOps() argument
3877 getVLDMDefCycle(const InstrItineraryData * ItinData,const MCInstrDesc & DefMCID,unsigned DefClass,unsigned DefIdx,unsigned DefAlign) const getVLDMDefCycle() argument
3917 getLDMDefCycle(const InstrItineraryData * ItinData,const MCInstrDesc & DefMCID,unsigned DefClass,unsigned DefIdx,unsigned DefAlign) const getLDMDefCycle() argument
3951 getVSTMUseCycle(const InstrItineraryData * ItinData,const MCInstrDesc & UseMCID,unsigned UseClass,unsigned UseIdx,unsigned UseAlign) const getVSTMUseCycle() argument
3990 getSTMUseCycle(const InstrItineraryData * ItinData,const MCInstrDesc & UseMCID,unsigned UseClass,unsigned UseIdx,unsigned UseAlign) const getSTMUseCycle() argument
4018 getOperandLatency(const InstrItineraryData * ItinData,const MCInstrDesc & DefMCID,unsigned DefIdx,unsigned DefAlign,const MCInstrDesc & UseMCID,unsigned UseIdx,unsigned UseAlign) const getOperandLatency() argument
4364 getOperandLatency(const InstrItineraryData * ItinData,const MachineInstr & DefMI,unsigned DefIdx,const MachineInstr & UseMI,unsigned UseIdx) const getOperandLatency() argument
4398 getOperandLatencyImpl(const InstrItineraryData * ItinData,const MachineInstr & DefMI,unsigned DefIdx,const MCInstrDesc & DefMCID,unsigned DefAdj,const MachineOperand & DefMO,unsigned Reg,const MachineInstr & UseMI,unsigned UseIdx,const MCInstrDesc & UseMCID,unsigned UseAdj) const getOperandLatencyImpl() argument
4458 getOperandLatency(const InstrItineraryData * ItinData,SDNode * DefNode,unsigned DefIdx,SDNode * UseNode,unsigned UseIdx) const getOperandLatency() argument
4735 getInstrLatency(const InstrItineraryData * ItinData,const MachineInstr & MI,unsigned * PredCost) const getInstrLatency() argument
4786 getInstrLatency(const InstrItineraryData * ItinData,SDNode * Node) const getInstrLatency() argument
4828 const InstrItineraryData *ItinData = SchedModel.getInstrItineraries(); hasLowDefLatency() local
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| /llvm-project/llvm/utils/TableGen/ |
| H A D | SubtargetEmitter.cpp | 354 FormItineraryStageString(const std::string & Name,Record * ItinData,std::string & ItinString,unsigned & NStages) FormItineraryStageString() argument
400 FormItineraryOperandCycleString(Record * ItinData,std::string & ItinString,unsigned & NOperandCycles) FormItineraryOperandCycleString() argument
416 FormItineraryBypassString(const std::string & Name,Record * ItinData,std::string & ItinString,unsigned NOperandCycles) FormItineraryBypassString() argument
516 Record *ItinData = ProcModel.ItinDefList[SchedClassIdx]; EmitStageAndOperandCycleData() local
[all...] |
| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 1970 getInstrLatency(const InstrItineraryData * ItinData,const MachineInstr & MI,unsigned * PredCost) const getInstrLatency() argument
4308 getInstrTimingClassLatency(const InstrItineraryData * ItinData,const MachineInstr & MI) const getInstrTimingClassLatency() argument
4328 getOperandLatency(const InstrItineraryData * ItinData,const MachineInstr & DefMI,unsigned DefIdx,const MachineInstr & UseMI,unsigned UseIdx) const getOperandLatency() argument
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.cpp | 983 getInstrLatency(const InstrItineraryData * ItinData,const MachineInstr &,unsigned * PredCost) const getInstrLatency() argument
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| H A D | SIInstrInfo.cpp | 9526 getInstrLatency(const InstrItineraryData * ItinData,const MachineInstr & MI,unsigned * PredCost) const getInstrLatency() argument
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