Lines Matching defs:ItinData

3477 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData,
3482     int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());
3779 unsigned ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
3781   if (!ItinData || ItinData->isEmpty())
3786   int ItinUOps = ItinData->getNumMicroOps(Class);
3789       return getNumMicroOpsSwiftLdSt(ItinData, MI);
3893 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
3899     return ItinData->getOperandCycle(DefClass, DefIdx);
3933 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
3939     return ItinData->getOperandCycle(DefClass, DefIdx);
3967 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
3972     return ItinData->getOperandCycle(UseClass, UseIdx);
4006 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
4011     return ItinData->getOperandCycle(UseClass, UseIdx);
4034     const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID,
4041     return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
4050     DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
4059     DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
4080     DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
4091     UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
4100     UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
4118     UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
4134       if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
4137     } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
4380     const InstrItineraryData *ItinData, const MachineInstr &DefMI,
4383   if (!ItinData || ItinData->isEmpty())
4409       ItinData, *ResolvedDefMI, DefIdx, ResolvedDefMI->getDesc(), DefAdj, DefMO,
4414     const InstrItineraryData *ItinData, const MachineInstr &DefMI,
4429     unsigned Latency = getInstrLatency(ItinData, DefMI);
4456       ItinData, DefMCID, DefIdx, DefAlign, UseMCID, UseIdx, UseAlign);
4474 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
4485   if (!ItinData || ItinData->isEmpty())
4490         ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
4506       ItinData, DefMCID, DefIdx, DefAlign, UseMCID, UseIdx, UseAlign);
4751 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
4766         Latency += getInstrLatency(ItinData, *I, PredCost);
4780   if (!ItinData)
4786   if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)
4787     return getNumMicroOps(ItinData, MI);
4790   unsigned Latency = ItinData->getStageLatency(Class);
4802 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
4807   if (!ItinData || ItinData->isEmpty())
4813     return ItinData->getStageLatency(get(Opcode).getSchedClass());
4844   const InstrItineraryData *ItinData = SchedModel.getInstrItineraries();
4845   if (!ItinData || ItinData->isEmpty())
4852         ItinData->getOperandCycle(DefClass, DefIdx);