| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 304 bool IsZExt = isa<ZExtInst>(I); isIntExtFree() local
1166 emitAddSub(bool UseAdd,MVT RetVT,const Value * LHS,const Value * RHS,bool SetFlags,bool WantResult,bool IsZExt) emitAddSub() argument
1466 emitCmp(const Value * LHS,const Value * RHS,bool IsZExt) emitCmp() argument
1489 emitICmp(MVT RetVT,const Value * LHS,const Value * RHS,bool IsZExt) emitICmp() argument
1533 emitAdd(MVT RetVT,const Value * LHS,const Value * RHS,bool SetFlags,bool WantResult,bool IsZExt) emitAdd() argument
1562 emitSub(MVT RetVT,const Value * LHS,const Value * RHS,bool SetFlags,bool WantResult,bool IsZExt) emitSub() argument
3909 bool IsZExt = Outs[0].Flags.isZExt(); selectRet() local
4000 emiti1Ext(unsigned SrcReg,MVT DestVT,bool IsZExt) emiti1Ext() argument
4092 emitLSL_ri(MVT RetVT,MVT SrcVT,unsigned Op0,uint64_t Shift,bool IsZExt) emitLSL_ri() argument
4195 emitLSR_ri(MVT RetVT,MVT SrcVT,unsigned Op0,uint64_t Shift,bool IsZExt) emitLSR_ri() argument
4311 emitASR_ri(MVT RetVT,MVT SrcVT,unsigned Op0,uint64_t Shift,bool IsZExt) emitASR_ri() argument
4391 emitIntExt(MVT SrcVT,unsigned SrcReg,MVT DestVT,bool IsZExt) emitIntExt() argument
4516 bool IsZExt = isa<ZExtInst>(I); optimizeIntExtLoad() local
4573 bool IsZExt = isa<ZExtInst>(I); selectIntExt() local
4659 bool IsZExt = true; selectMul() local
4722 bool IsZExt = I->getOpcode() != Instruction::AShr; selectShift() local
[all...] |
| H A D | AArch64ISelLowering.cpp | 16542 bool IsZExt = false; performVecReduceAddCombineWithUADDLP() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 450 bool IsZExt, unsigned FP64LoadOpc) { in PPCEmitLoad() argument
818 bool IsZExt, unsigned DestReg, in PPCEmitCmp() argument
1808 PPCEmitIntExt(MVT SrcVT,unsigned SrcReg,MVT DestVT,unsigned DestReg,bool IsZExt) PPCEmitIntExt() argument
1905 bool IsZExt = isa<ZExtInst>(I); SelectIntExt() local
2308 bool IsZExt = false; tryToFoldLoadIntoMI() local
[all...] |
| H A D | PPCInstrInfo.cpp | 5197 bool IsZExt = definedByZeroExtendingOp(Reg, MRI); isSignOrZeroExtended() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 1751 bool IsZExt = Outs[0].Flags.isZExt(); in selectRet() local
1889 unsigned DestReg, bool IsZExt) { in emitIntExt() argument
1976 bool IsZExt = Opcode == Instruction::LShr; in selectShift() local
|
| /freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineFrameInfo.h | 540 setObjectZExt(int ObjectIdx,bool IsZExt) setObjectZExt() argument
|
| H A D | TargetLowering.h | 301 bool IsZExt : 1; global() variable
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstructionCombining.cpp | 1026 bool IsZExt = isa<ZExtInst>(CastOp); foldBinOpOfSelectAndCastOfSelectCondition() local
3340 bool IsZExt = isa<ZExtInst>(Cond); visitSwitchInst() local
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 783 bool IsZExt = (Ld->getExtensionType() == ISD::ZEXTLOAD); tryIndexedLoad() local
|