Lines Matching defs:IsZExt
206 bool WantResult = true, bool IsZExt = false);
224 bool emitCmp(const Value *LHS, const Value *RHS, bool IsZExt);
225 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
238 bool IsZExt = false);
242 bool IsZExt = false);
260 bool IsZExt = true);
263 bool IsZExt = true);
266 bool IsZExt = false);
305 bool IsZExt = isa<ZExtInst>(I);
312 if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr()))
1090 Addr.getShift(), /*IsZExt=*/true);
1093 Addr.getShift(), /*IsZExt=*/false);
1167 bool WantResult, bool IsZExt) {
1178 ExtendType = IsZExt ? AArch64_AM::UXTB : AArch64_AM::SXTB;
1182 ExtendType = IsZExt ? AArch64_AM::UXTH : AArch64_AM::SXTH;
1214 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt);
1218 uint64_t Imm = IsZExt ? C->getZExtValue() : C->getSExtValue();
1294 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt);
1467 bool AArch64FastISel::emitCmp(const Value *LHS, const Value *RHS, bool IsZExt) {
1482 return emitICmp(VT, LHS, RHS, IsZExt);
1490 bool IsZExt) {
1492 IsZExt) != 0;
1534 bool SetFlags, bool WantResult, bool IsZExt) {
1536 IsZExt);
1563 bool SetFlags, bool WantResult, bool IsZExt) {
1565 IsZExt);
3923 bool IsZExt = Outs[0].Flags.isZExt();
3924 SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
4014 unsigned AArch64FastISel::emiti1Ext(unsigned SrcReg, MVT DestVT, bool IsZExt) {
4022 if (IsZExt) {
4106 uint64_t Shift, bool IsZExt) {
4131 return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4170 unsigned Opc = OpcTable[IsZExt][Is64Bit];
4209 uint64_t Shift, bool IsZExt) {
4234 return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4266 if (Shift >= SrcBits && IsZExt)
4271 if (!IsZExt) {
4272 Op0 = emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4277 IsZExt = true;
4286 unsigned Opc = OpcTable[IsZExt][Is64Bit];
4325 uint64_t Shift, bool IsZExt) {
4350 return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4382 if (Shift >= SrcBits && IsZExt)
4391 unsigned Opc = OpcTable[IsZExt][Is64Bit];
4405 bool IsZExt) {
4425 return emiti1Ext(SrcReg, DestVT, IsZExt);
4428 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
4430 Opc = IsZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
4435 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
4437 Opc = IsZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
4442 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
4530 bool IsZExt = isa<ZExtInst>(I);
4538 if (!(IsZExt && isZExtLoad(LoadMI)) && !(!IsZExt && isSExtLoad(LoadMI)))
4547 if (IsZExt) {
4587 bool IsZExt = isa<ZExtInst>(I);
4589 if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr())) {
4605 unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt);
4673 bool IsZExt = true;
4679 IsZExt = true;
4688 IsZExt = false;
4699 emitLSL_ri(VT, SrcVT, Src0Reg, ShiftVal, IsZExt);
4736 bool IsZExt = I->getOpcode() != Instruction::AShr;
4743 IsZExt = true;
4752 IsZExt = false;
4765 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);
4768 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);
4771 ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);