Lines Matching defs:IsZExt
161 const TargetRegisterClass *RC, bool IsZExt = true,
168 unsigned DestReg, bool IsZExt);
450 bool IsZExt, unsigned FP64LoadOpc) {
479 Opc = (IsZExt ? (Is32BitInt ? PPC::LHZ : PPC::LHZ8)
483 Opc = (IsZExt ? (Is32BitInt ? PPC::LWZ : PPC::LWZ8)
818 bool IsZExt, unsigned DestReg,
843 Imm = (IsZExt) ? (int64_t)CIVal.getZExtValue() :
845 if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm)))
918 CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW;
920 CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI;
924 CmpOpc = IsZExt ? PPC::CMPLD : PPC::CMPD;
926 CmpOpc = IsZExt ? PPC::CMPLDI : PPC::CMPDI;
932 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt))
938 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt))
1443 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/false))
1455 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/true))
1806 unsigned DestReg, bool IsZExt) {
1813 if (!IsZExt) {
1903 bool IsZExt = isa<ZExtInst>(I);
1929 if (!PPCEmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, IsZExt))
2310 bool IsZExt = false;
2317 IsZExt = true;
2328 IsZExt = true;
2366 if (!PPCEmitLoad(VT, ResultReg, Addr, nullptr, IsZExt,