/llvm-project/llvm/lib/Target/X86/ |
H A D | X86SelectionDAGInfo.cpp | 73 SDValue InGlue; EmitTargetCodeForMemset() local 164 SDValue InGlue; emitRepmovs() local [all...] |
H A D | X86ISelLoweringCall.cpp | 1009 /// \param [in,out] InGlue Represents SDvalue in the parent DAG node for in getv64i1Argument() argument 1094 LowerCallResult(SDValue Chain,SDValue InGlue,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals,uint32_t * RegMask) const LowerCallResult() argument 2390 SDValue InGlue; LowerCall() local [all...] |
H A D | X86ISelDAGToDAG.cpp | 4251 emitPCMPESTR(unsigned ROpc,unsigned MOpc,bool MayFoldLoad,const SDLoc & dl,MVT VT,SDNode * Node,SDValue & InGlue) emitPCMPESTR() argument 5186 SDValue InGlue = Chain.getValue(1); Select() local 5576 SDValue InGlue = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg, Select() local 5662 SDValue InGlue = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg, Select() local 5791 SDValue InGlue; Select() local 6227 SDValue InGlue = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, X86::EAX, Select() local [all...] |
/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRISelDAGToDAG.cpp | 451 SDValue InGlue; select() local 519 SDValue InGlue = SDValue(Mul, 0); selectMultiplication() local
|
H A D | AVRISelLowering.cpp | 1609 SDValue InGlue; LowerCall() local 1662 LowerCallResult(SDValue Chain,SDValue InGlue,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const LowerCallResult() argument [all...] |
/llvm-project/llvm/lib/Target/Mips/ |
H A D | Mips16ISelDAGToDAG.cpp | 50 Hi = CurDAG->getMachineNode(Opcode, DL, Ty, InGlue); in selectMULT() local
|
H A D | MipsISelLowering.cpp | 602 InGlue = CopyFromLo.getValue(2); in performDivRemCombine() local 3098 SDValue InGlue; getOpndList() local 3510 SDValue InGlue = Chain.getValue(1); LowerCall() local 3530 LowerCallResult(SDValue Chain,SDValue InGlue,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & DL,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals,TargetLowering::CallLoweringInfo & CLI) const LowerCallResult() argument [all...] |
H A D | MipsSEISelDAGToDAG.cpp | 207 SDValue InGlue = Node->getOperand(2); selectAddE() local
|
/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFISelLowering.cpp | 482 SDValue InGlue; LowerCall() local 584 LowerCallResult(SDValue Chain,SDValue InGlue,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & DL,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const LowerCallResult() argument [all...] |
/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 888 SDValue InGlue; in LowerCCCCallTo() local 935 LowerCallResult(SDValue Chain,SDValue InGlue,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const LowerCallResult() argument [all...] |
/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiISelLowering.cpp | 716 SDValue InGlue; LowerCCCCallTo() local 778 LowerCallResult(SDValue Chain,SDValue InGlue,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & DL,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const LowerCallResult() argument [all...] |
/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGSDNodes.cpp | 293 SDValue InGlue; in ClusterNeighboringLoads() local
|
H A D | SelectionDAGISel.cpp | 2522 SDValue InGlue = *It++; Select_STACKMAP() local
|
/llvm-project/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 970 static SDValue LowerCallResult(SDValue Chain, SDValue InGlue, in LowerCallResult() argument 1094 SDValue InGlue; LowerCCCCallTo() local [all...] |
/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1044 SDValue InGlue; in LowerCall_32() local 1381 SDValue InGlue; LowerCall_64() local 2254 SDValue InGlue; LowerGlobalTLSAddress() local [all...] |
/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 1557 LowerUnalignedStoreParam(SelectionDAG & DAG,SDValue Chain,uint64_t Offset,EVT ElementType,SDValue StVal,SDValue & InGlue,unsigned ArgID,const SDLoc & dl) LowerUnalignedStoreParam() argument 1587 LowerUnalignedLoadRetParam(SelectionDAG & DAG,SDValue & Chain,uint64_t Offset,EVT ElementType,SDValue & InGlue,SmallVectorImpl<SDValue> & TempProxyRegOps,const SDLoc & dl) LowerUnalignedLoadRetParam() argument 1680 SDValue InGlue = Chain.getValue(1); LowerCall() local [all...] |
/llvm-project/llvm/lib/Target/M68k/ |
H A D | M68kISelLowering.cpp | 770 SDValue InGlue; in LowerCall() local 884 LowerCallResult(SDValue Chain,SDValue InGlue,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & DL,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const LowerCallResult() argument [all...] |
/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 4130 SDValue InGlue = N->getOperand(4); Select() local 4238 SDValue InGlue = N->getOperand(4); Select() local
|
H A D | ARMISelLowering.cpp | 2218 LowerCallResult(SDValue Chain,SDValue InGlue,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals,bool isThisReturn,SDValue ThisVal,bool isCmseNSCall) const LowerCallResult() argument 2675 SDValue InGlue; LowerCall() local [all...] |
/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 4612 SDValue InGlue; // Null incoming flag value. in trySETCC() local 5504 SDValue InGlue = N->getOperand(1); Select() local
|
H A D | PPCISelLowering.cpp | 5319 PrepareTailCall(SelectionDAG & DAG,SDValue & InGlue,SDValue & Chain,const SDLoc & dl,int SPDiff,unsigned NumBytes,SDValue LROp,SDValue FPOp,SmallVectorImpl<TailCallArgumentInfo> & TailCallArguments) PrepareTailCall() argument 5355 LowerCallResult(SDValue Chain,SDValue InGlue,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const LowerCallResult() argument 6189 SDValue InGlue; LowerCall_32SVR4() local 6803 SDValue InGlue; LowerCall_64SVR4() local 7805 SDValue InGlue; LowerCall_AIX() local [all...] |
/llvm-project/llvm/lib/Target/VE/ |
H A D | VEISelLowering.cpp | 749 SDValue InGlue; LowerCall() local [all...] |
/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 1413 SDValue InGlue; LowerToTLSGeneralDynamicModel() local
|
/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIISelLowering.cpp | 3240 LowerCallResult(SDValue Chain,SDValue InGlue,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & DL,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals,bool IsThisReturn,SDValue ThisVal) const LowerCallResult() argument 3842 SDValue InGlue; LowerCall() local [all...] |
/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 7709 LowerCallResult(SDValue Chain,SDValue InGlue,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<CCValAssign> & RVLocs,const SDLoc & DL,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals,bool isThisReturn,SDValue ThisVal,bool RequiresSMChange) const LowerCallResult() argument 8091 changeStreamingMode(SelectionDAG & DAG,SDLoc DL,bool Enable,SDValue Chain,SDValue InGlue,unsigned Condition,SDValue PStateSM) const changeStreamingMode() argument 8620 SDValue InGlue; LowerCall() local [all...] |