| /llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PreLegalizerCombiner.cpp | 422 auto ExtOpc = ExtMI->getOpcode(); matchExtUaddvToUaddlv() local
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| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstExtenders.cpp | 1607 unsigned ExtOpc = MI.getOpcode(); replaceInstrExact() local
1725 unsigned ExtOpc = MI.getOpcode(); replaceInstrExpr() local
[all...] |
| H A D | HexagonBitSimplify.cpp | 2543 unsigned ExtOpc = 0; in simplifyExtractLow() local
[all...] |
| H A D | HexagonISelLoweringHVX.cpp | 1585 unsigned ExtOpc = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; resizeToWidth() local
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| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.cpp | 547 MachineInstrBuilder MachineIRBuilder::buildExtOrTrunc(unsigned ExtOpc, in buildExtOrTrunc() argument
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| H A D | LegalizerHelper.cpp | 2445 unsigned ExtOpc = MI.getOpcode() == TargetOpcode::G_CTTZ || widenScalar() local
2739 unsigned ExtOpc = LI.getExtOpcodeForWideningConstant( widenScalar() local
[all...] |
| H A D | CombinerHelper.cpp | 686 getExtLoadOpcForExtend(unsigned ExtOpc) getExtLoadOpcForExtend() argument
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| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 4291 unsigned ExtOpc = lowerScalarSplat() local
4358 unsigned ExtOpc = lowerScalarInsert() local
8794 unsigned ExtOpc = lowerVectorIntrinsicScalars() local
9031 unsigned ExtOpc = promoteVCIXScalar() local
12132 customLegalizeToWOp(SDNode * N,SelectionDAG & DAG,unsigned ExtOpc=ISD::ANY_EXTEND) customLegalizeToWOp() argument
12423 unsigned ExtOpc = ISD::ANY_EXTEND; ReplaceNodeResults() local
14299 unsigned ExtOpc = getExtOpc(*SupportsExt); getOrCreateExtendedOp() local
[all...] |
| /llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCalls.cpp | 3491 Instruction::CastOps ExtOpc = Instruction::CastOps::CastOpsEnd; visitCallInst() local
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| H A D | InstCombineCompares.cpp | 7548 unsigned ExtOpc = ExtI->getOpcode(); visitICmpInst() local
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 3128 unsigned ExtOpc = getCastInstrCost() local
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| H A D | X86ISelLowering.cpp | 20236 SplitAndExtendv16i1(unsigned ExtOpc,MVT VT,SDValue In,const SDLoc & dl,SelectionDAG & DAG) SplitAndExtendv16i1() argument
24493 unsigned ExtOpc = LowerEXTEND_VECTOR_INREG() local
28467 unsigned ExtOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; LowerABD() local
29703 unsigned ExtOpc = Opc == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; LowerShift() local
32628 unsigned ExtOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; ReplaceNodeResults() local
47987 unsigned ExtOpc = LHS.getOpcode(); combineShiftToPMULH() local
48434 unsigned ExtOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; combineVectorPack() local
58519 ISD::NodeType ExtOpc = IsBool ? getExtendForContent(BCont) LowerAsmOperandForConstraint() local
[all...] |
| /llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 1737 customLegalizeToWOp(SDNode * N,SelectionDAG & DAG,int NumOp,unsigned ExtOpc=ISD::ANY_EXTEND) customLegalizeToWOp() argument
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 1900 extendLow32IntoHigh32(MachineIRBuilder & B,Register Hi32Reg,Register Lo32Reg,unsigned ExtOpc,const RegisterBank & RegBank,bool IsBooleanSrc=false) extendLow32IntoHigh32() argument
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| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 1449 unsigned ExtOpc = PromoteOperand() local
7075 unsigned ExtOpc = N0.getOpcode(); visitAND() local
12919 ExtendUsesToFormExtLoad(EVT VT,SDNode * N,SDValue N0,unsigned ExtOpc,SmallVectorImpl<SDNode * > & ExtendNodes,const TargetLowering & TLI) ExtendUsesToFormExtLoad() argument
13256 tryToFoldExtOfLoad(SelectionDAG & DAG,DAGCombiner & Combiner,const TargetLowering & TLI,EVT VT,bool LegalOperations,SDNode * N,SDValue N0,ISD::LoadExtType ExtLoadType,ISD::NodeType ExtOpc,bool NonNegZExt=false) tryToFoldExtOfLoad() argument
13316 tryToFoldExtOfMaskedLoad(SelectionDAG & DAG,const TargetLowering & TLI,EVT VT,bool LegalOperations,SDNode * N,SDValue N0,ISD::LoadExtType ExtLoadType,ISD::NodeType ExtOpc) tryToFoldExtOfMaskedLoad() argument
[all...] |
| H A D | TargetLowering.cpp | 5561 ISD::NodeType ExtOpc = LowerAsmOperandForConstraint() local
9243 unsigned ExtOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; expandAVG() local
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| H A D | LegalizeIntegerTypes.cpp | 5835 unsigned ExtOpc = ISD::ANY_EXTEND; PromoteIntRes_BUILD_VECTOR() local
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