| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | A15SDOptimizer.cpp | 145 MCRegister DReg = in getDPRLaneFromSPR() local
431 createExtractSubreg(MachineBasicBlock & MBB,MachineBasicBlock::iterator InsertBefore,const DebugLoc & DL,unsigned DReg,unsigned Lane,const TargetRegisterClass * TRC) createExtractSubreg() argument
476 createInsertSubreg(MachineBasicBlock & MBB,MachineBasicBlock::iterator InsertBefore,const DebugLoc & DL,unsigned DReg,unsigned Lane,unsigned ToInsert) createInsertSubreg() argument
|
| H A D | ARMBaseInstrInfo.cpp | 5134 ImplicitSReg = TRI->getSubReg(DReg, in setExecutionDomain() local
5077 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass); getCorrespondingDRegAndLane() local
5106 getImplicitSPRUseForDPRUse(const TargetRegisterInfo * TRI,MachineInstr & MI,unsigned DReg,unsigned Lane,unsigned & ImplicitSReg) getImplicitSPRUseForDPRUse() argument
5388 unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0, getPartialRegUpdateClearance() local
5409 unsigned DReg = Reg; breakPartialRegDependency() local
[all...] |
| /llvm-project/llvm/lib/Target/Mips/ |
| H A D | Mips16FrameLowering.cpp | 77 unsigned DReg = MRI->getDwarfRegNum(Reg, true); emitPrologue() local
|
| /llvm-project/llvm/lib/Target/M68k/MCTargetDesc/ |
| H A D | M68kBaseInfo.h | 106 DReg = 0x8, enumerator
|
| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FloatingPoint.cpp | 934 unsigned DReg = llvm::countr_zero(Defs); adjustLiveRegs() local
966 unsigned DReg = llvm::countr_zero(Defs); adjustLiveRegs() local
|
| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 466 Register DReg = DstInst->getOperand(0).getReg(); adjustSchedDependency() local
|
| /llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 4930 unsigned DReg = Inst.getOperand(0).getReg(); expandRotation() local
4993 unsigned DReg = Inst.getOperand(0).getReg(); expandRotationImm() local
5055 unsigned DReg = Inst.getOperand(0).getReg(); expandDRotation() local
5118 unsigned DReg = Inst.getOperand(0).getReg(); expandDRotationImm() local
[all...] |
| /llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 945 unsigned DReg = CSKY::F0_64 + RegNo; getRegForInlineAsmConstraint() local
|
| /llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 4849 unsigned DReg = RegNo - LoongArch::F0 + LoongArch::F0_64; getRegForInlineAsmConstraint() local
|
| /llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 2505 setVecListOneD(unsigned int DReg) setVecListOneD() argument
|
| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 20726 unsigned DReg = RISCV::F0_D + RegNo; getRegForInlineAsmConstraint() local
|