Lines Matching defs:DReg

5093   MCRegister DReg =
5097   if (DReg)
5098     return DReg;
5101   DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass);
5103   assert(DReg && "S-register with no D super-register?");
5104   return DReg;
5123                                        MachineInstr &MI, MCRegister DReg,
5128   if (MI.definesRegister(DReg, TRI) || MI.readsRegister(DReg, TRI)) {
5134   ImplicitSReg = TRI->getSubReg(DReg,
5153   MCRegister DReg;
5197     DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane);
5204         .addReg(DReg, RegState::Undef)
5221     DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane);
5224     if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg))
5233     MIB.addReg(DReg, RegState::Define)
5234         .addReg(DReg, getUndefRegState(!MI.readsRegister(DReg, TRI)))
5408     MCRegister DReg =
5410     if (!DReg || !MI.definesRegister(DReg, TRI))
5429   unsigned DReg = Reg;
5433     DReg = ARM::D0 + (Reg - ARM::S0) / 2;
5434     assert(TRI->isSuperRegister(Reg, DReg) && "Register enums broken");
5437   assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps");
5438   assert(MI.definesRegister(DReg, TRI) && "MI doesn't clobber full D-reg");
5448   BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::FCONSTD), DReg)
5451   MI.addRegisterKilled(DReg, TRI, true);