Home
last modified time | relevance | path

Searched defs:DAG (Results 1 – 25 of 113) sorted by relevance

12345

/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGTargetInfo.h81 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, in EmitTargetCodeForMemset() argument
120 EmitTargetCodeForMemchr(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, in EmitTargetCodeForStrcpy() argument
51 EmitTargetCodeForMemcpy(SelectionDAG & DAG,const SDLoc & dl,SDValue Chain,SDValue Op1,SDValue Op2,SDValue Op3,Align Alignment,bool isVolatile,bool AlwaysInline,MachinePointerInfo DstPtrInfo,MachinePointerInfo SrcPtrInfo) EmitTargetCodeForMemcpy() argument
68 EmitTargetCodeForMemmove(SelectionDAG & DAG,const SDLoc & dl,SDValue Chain,SDValue Op1,SDValue Op2,SDValue Op3,Align Alignment,bool isVolatile,MachinePointerInfo DstPtrInfo,MachinePointerInfo SrcPtrInfo) EmitTargetCodeForMemmove() argument
95 EmitTargetCodeForMemcmp(SelectionDAG & DAG,const SDLoc & dl,SDValue Chain,SDValue Op1,SDValue Op2,SDValue Op3,MachinePointerInfo Op1PtrInfo,MachinePointerInfo Op2PtrInfo) EmitTargetCodeForMemcmp() argument
107 EmitTargetCodeForMemchr(SelectionDAG & DAG,const SDLoc & dl,SDValue Chain,SDValue Src,SDValue Char,SDValue Length,MachinePointerInfo SrcPtrInfo) EmitTargetCodeForMemchr() argument
132 EmitTargetCodeForStrcmp(SelectionDAG & DAG,const SDLoc & dl,SDValue Chain,SDValue Op1,SDValue Op2,MachinePointerInfo Op1PtrInfo,MachinePointerInfo Op2PtrInfo) EmitTargetCodeForStrcmp() argument
140 EmitTargetCodeForStrlen(SelectionDAG & DAG,const SDLoc & DL,SDValue Chain,SDValue Src,MachinePointerInfo SrcPtrInfo) EmitTargetCodeForStrlen() argument
146 EmitTargetCodeForStrnlen(SelectionDAG & DAG,const SDLoc & DL,SDValue Chain,SDValue Src,SDValue MaxLength,MachinePointerInfo SrcPtrInfo) EmitTargetCodeForStrnlen() argument
152 EmitTargetCodeForSetTag(SelectionDAG & DAG,const SDLoc & dl,SDValue Chain,SDValue Addr,SDValue Size,MachinePointerInfo DstPtrInfo,bool ZeroData) EmitTargetCodeForSetTag() argument
[all...]
H A DSelectionDAGAddressAnalysis.h66 const SelectionDAG &DAG) const { in equalBaseIndex()
77 bool contains(const SelectionDAG &DAG, int64_t BitSize, in contains()
/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.cpp24 createMemMemNode(SelectionDAG & DAG,const SDLoc & DL,unsigned Op,SDValue Chain,SDValue Dst,SDValue Src,SDValue LenAdj,SDValue Byte) createMemMemNode() argument
41 emitMemMemImm(SelectionDAG & DAG,const SDLoc & DL,unsigned Op,SDValue Chain,SDValue Dst,SDValue Src,uint64_t Size,SDValue Byte=SDValue ()) emitMemMemImm() argument
50 emitMemMemReg(SelectionDAG & DAG,const SDLoc & DL,unsigned Op,SDValue Chain,SDValue Dst,SDValue Src,SDValue Size,SDValue Byte=SDValue ()) emitMemMemReg() argument
61 EmitTargetCodeForMemcpy(SelectionDAG & DAG,const SDLoc & DL,SDValue Chain,SDValue Dst,SDValue Src,SDValue Size,Align Alignment,bool IsVolatile,bool AlwaysInline,MachinePointerInfo DstPtrInfo,MachinePointerInfo SrcPtrInfo) const EmitTargetCodeForMemcpy() argument
77 memsetStore(SelectionDAG & DAG,const SDLoc & DL,SDValue Chain,SDValue Dst,uint64_t ByteVal,uint64_t Size,Align Alignment,MachinePointerInfo DstPtrInfo) memsetStore() argument
89 EmitTargetCodeForMemset(SelectionDAG & DAG,const SDLoc & DL,SDValue Chain,SDValue Dst,SDValue Byte,SDValue Size,Align Alignment,bool IsVolatile,bool AlwaysInline,MachinePointerInfo DstPtrInfo) const EmitTargetCodeForMemset() argument
163 addIPMSequence(const SDLoc & DL,SDValue CCReg,SelectionDAG & DAG) addIPMSequence() argument
173 EmitTargetCodeForMemcmp(SelectionDAG & DAG,const SDLoc & DL,SDValue Chain,SDValue Src1,SDValue Src2,SDValue Size,MachinePointerInfo Op1PtrInfo,MachinePointerInfo Op2PtrInfo) const EmitTargetCodeForMemcmp() argument
189 EmitTargetCodeForMemchr(SelectionDAG & DAG,const SDLoc & DL,SDValue Chain,SDValue Src,SDValue Char,SDValue Length,MachinePointerInfo SrcPtrInfo) const EmitTargetCodeForMemchr() argument
215 EmitTargetCodeForStrcpy(SelectionDAG & DAG,const SDLoc & DL,SDValue Chain,SDValue Dest,SDValue Src,MachinePointerInfo DestPtrInfo,MachinePointerInfo SrcPtrInfo,bool isStpcpy) const EmitTargetCodeForStrcpy() argument
225 EmitTargetCodeForStrcmp(SelectionDAG & DAG,const SDLoc & DL,SDValue Chain,SDValue Src1,SDValue Src2,MachinePointerInfo Op1PtrInfo,MachinePointerInfo Op2PtrInfo) const EmitTargetCodeForStrcmp() argument
242 getBoundedStrlen(SelectionDAG & DAG,const SDLoc & DL,SDValue Chain,SDValue Src,SDValue Limit) getBoundedStrlen() argument
256 EmitTargetCodeForStrlen(SelectionDAG & DAG,const SDLoc & DL,SDValue Chain,SDValue Src,MachinePointerInfo SrcPtrInfo) const EmitTargetCodeForStrlen() argument
263 EmitTargetCodeForStrnlen(SelectionDAG & DAG,const SDLoc & DL,SDValue Chain,SDValue Src,SDValue MaxLength,MachinePointerInfo SrcPtrInfo) const EmitTargetCodeForStrnlen() argument
[all...]
H A DSystemZISelLowering.cpp1479 convertLocVTToValVT(SelectionDAG & DAG,const SDLoc & DL,CCValAssign & VA,SDValue Chain,SDValue Value) convertLocVTToValVT() argument
1508 convertValVTToLocVT(SelectionDAG & DAG,const SDLoc & DL,CCValAssign & VA,SDValue Value) convertValVTToLocVT() argument
1543 lowerI128ToGR128(SelectionDAG & DAG,SDValue In) lowerI128ToGR128() argument
1562 lowerGR128ToI128(SelectionDAG & DAG,SDValue In) lowerGR128ToI128() argument
1581 splitValueIntoRegisterParts(SelectionDAG & DAG,const SDLoc & DL,SDValue Val,SDValue * Parts,unsigned NumParts,MVT PartVT,std::optional<CallingConv::ID> CC) const splitValueIntoRegisterParts() argument
1594 joinRegisterPartsIntoValue(SelectionDAG & DAG,const SDLoc & DL,const SDValue * Parts,unsigned NumParts,MVT PartVT,EVT ValueVT,std::optional<CallingConv::ID> CC) const joinRegisterPartsIntoValue() argument
1608 LowerFormalArguments(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & DL,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const LowerFormalArguments() argument
1807 getADAEntry(SelectionDAG & DAG,SDValue Val,SDLoc DL,unsigned Offset,bool LoadAdr=false) getADAEntry() argument
1828 getADAEntry(SelectionDAG & DAG,const GlobalValue * GV,SDLoc DL,EVT PtrVT) getADAEntry() argument
1851 getzOSCalleeAndADA(SelectionDAG & DAG,SDValue & Callee,SDValue & ADA,SDLoc & DL,SDValue & Chain) getzOSCalleeAndADA() argument
1898 SelectionDAG &DAG = CLI.DAG; LowerCall() local
2124 makeExternalCall(SDValue Chain,SelectionDAG & DAG,const char * CalleeName,EVT RetVT,ArrayRef<SDValue> Ops,CallingConv::ID CallConv,bool IsSigned,SDLoc DL,bool DoesNotReturn,bool IsReturnValueUsed) const makeExternalCall() argument
2408 emitIntrinsicWithCCAndChain(SelectionDAG & DAG,SDValue Op,unsigned Opcode) emitIntrinsicWithCCAndChain() argument
2428 emitIntrinsicWithCC(SelectionDAG & DAG,SDValue Op,unsigned Opcode) emitIntrinsicWithCC() argument
2471 adjustZeroCmp(SelectionDAG & DAG,const SDLoc & DL,Comparison & C) adjustZeroCmp() argument
2491 adjustSubwordCmp(SelectionDAG & DAG,const SDLoc & DL,Comparison & C) adjustSubwordCmp() argument
2650 adjustForSubtraction(SelectionDAG & DAG,const SDLoc & DL,Comparison & C) adjustForSubtraction() argument
2721 adjustICmpTruncate(SelectionDAG & DAG,const SDLoc & DL,Comparison & C) adjustICmpTruncate() argument
2853 adjustForTestUnderMask(SelectionDAG & DAG,const SDLoc & DL,Comparison & C) adjustForTestUnderMask() argument
2963 adjustICmp128(SelectionDAG & DAG,const SDLoc & DL,Comparison & C) adjustICmp128() argument
3010 adjustForRedundantAnd(SelectionDAG & DAG,const SDLoc & DL,Comparison & C) adjustForRedundantAnd() argument
3028 getIntrinsicCmp(SelectionDAG & DAG,unsigned Opcode,SDValue Call,unsigned CCValid,uint64_t CC,ISD::CondCode Cond) getIntrinsicCmp() argument
3061 getCmp(SelectionDAG & DAG,SDValue CmpOp0,SDValue CmpOp1,ISD::CondCode Cond,const SDLoc & DL,SDValue Chain=SDValue (),bool IsSignaling=false) getCmp() argument
3127 emitCmp(SelectionDAG & DAG,const SDLoc & DL,Comparison & C) emitCmp() argument
3165 lowerMUL_LOHI32(SelectionDAG & DAG,const SDLoc & DL,unsigned Extend,SDValue Op0,SDValue Op1,SDValue & Hi,SDValue & Lo) lowerMUL_LOHI32() argument
3181 lowerGR128Binary(SelectionDAG & DAG,const SDLoc & DL,EVT VT,unsigned Opcode,SDValue Op0,SDValue Op1,SDValue & Even,SDValue & Odd) lowerGR128Binary() argument
3193 emitSETCC(SelectionDAG & DAG,const SDLoc & DL,SDValue CCReg,unsigned CCValid,unsigned CCMask) emitSETCC() argument
3275 expandV4F32ToV2F64(SelectionDAG & DAG,int Start,const SDLoc & DL,SDValue Op,SDValue Chain) expandV4F32ToV2F64() argument
3288 getVectorCmp(SelectionDAG & DAG,unsigned Opcode,const SDLoc & DL,EVT VT,SDValue CmpOp0,SDValue CmpOp1,SDValue Chain) const getVectorCmp() argument
3329 lowerVectorSETCC(SelectionDAG & DAG,const SDLoc & DL,EVT VT,ISD::CondCode CC,SDValue CmpOp0,SDValue CmpOp1,SDValue Chain,bool IsSignaling) const lowerVectorSETCC() argument
3423 lowerSTRICT_FSETCC(SDValue Op,SelectionDAG & DAG,bool IsSignaling) const lowerSTRICT_FSETCC() argument
3471 getAbsolute(SelectionDAG & DAG,const SDLoc & DL,SDValue Op,bool IsNegative) getAbsolute() argument
3564 lowerTLSGetOffset(GlobalAddressSDNode * Node,SelectionDAG & DAG,unsigned Opcode,SDValue GOTOffset) const lowerTLSGetOffset() argument
4563 getCSAddressAndShifts(SDValue Addr,SelectionDAG & DAG,SDLoc DL,SDValue & AlignedAddr,SDValue & BitShift,SDValue & NegBitShift) getCSAddressAndShifts() argument
4589 lowerATOMIC_LOAD_OP(SDValue Op,SelectionDAG & DAG,unsigned Opcode) const lowerATOMIC_LOAD_OP() argument
4812 getCCResult(SelectionDAG & DAG,SDValue CCReg) getCCResult() argument
5167 getPermuteNode(SelectionDAG & DAG,const SDLoc & DL,const Permute & P,SDValue Op0,SDValue Op1) getPermuteNode() argument
5213 getGeneralPermuteNode(SelectionDAG & DAG,const SDLoc & DL,SDValue * Ops,const SmallVectorImpl<int> & Bytes) getGeneralPermuteNode() argument
5384 getNode(SelectionDAG & DAG,const SDLoc & DL) getNode() argument
5554 insertUnpackIfPrepared(SelectionDAG & DAG,const SDLoc & DL,SDValue Op) insertUnpackIfPrepared() argument
5579 buildScalarToVector(SelectionDAG & DAG,const SDLoc & DL,EVT VT,SDValue Value) buildScalarToVector() argument
5595 buildMergeScalars(SelectionDAG & DAG,const SDLoc & DL,EVT VT,SDValue Op0,SDValue Op1) buildMergeScalars() argument
5611 joinDwords(SelectionDAG & DAG,const SDLoc & DL,SDValue Op0,SDValue Op1) joinDwords() argument
5632 tryBuildVectorShuffle(SelectionDAG & DAG,BuildVectorSDNode * BVN) tryBuildVectorShuffle() argument
5694 buildVector(SelectionDAG & DAG,const SDLoc & DL,EVT VT,SmallVectorImpl<SDValue> & Elems) const buildVector() argument
6010 lowerShift(SDValue Op,SelectionDAG & DAG,unsigned ByScalar) const lowerShift() argument
6253 expandBitCastI128ToF128(SelectionDAG & DAG,SDValue Src,const SDLoc & SL) expandBitCastI128ToF128() argument
6277 expandBitCastF128ToI128(SelectionDAG & DAG,SDValue Src,const SDLoc & SL) expandBitCastF128ToI128() argument
6536 SelectionDAG &DAG = DCI.DAG; combineExtract() local
6675 SelectionDAG &DAG = DCI.DAG; combineZERO_EXTEND() local
6726 SelectionDAG &DAG = DCI.DAG; combineSIGN_EXTEND_INREG() local
6747 SelectionDAG &DAG = DCI.DAG; combineSIGN_EXTEND() local
6775 SelectionDAG &DAG = DCI.DAG; combineMERGE() local
6880 SelectionDAG &DAG = DCI.DAG; combineLOAD() local
6981 isOnlyUsedByStores(SDValue StoredVal,SelectionDAG & DAG) isOnlyUsedByStores() argument
7045 SelectionDAG &DAG = DCI.DAG; combineSTORE() local
7215 SelectionDAG &DAG = DCI.DAG; combineVECTOR_SHUFFLE() local
7254 SelectionDAG &DAG = DCI.DAG; combineEXTRACT_VECTOR_ELT() local
7295 SelectionDAG &DAG = DCI.DAG; combineJOIN_DWORDS() local
7329 SelectionDAG &DAG = DCI.DAG; combineFP_ROUND() local
7393 SelectionDAG &DAG = DCI.DAG; combineFP_EXTEND() local
7448 SelectionDAG &DAG = DCI.DAG; combineINT_TO_FP() local
7476 SelectionDAG &DAG = DCI.DAG; combineBSWAP() local
7673 SelectionDAG &DAG = DCI.DAG; combineBR_CCMASK() local
7697 SelectionDAG &DAG = DCI.DAG; combineSELECT_CCMASK() local
7764 SelectionDAG &DAG = DCI.DAG; combineIntDIVREM() local
7781 SelectionDAG &DAG = DCI.DAG; combineINTRINSIC() local
7949 computeKnownBitsBinOp(const SDValue Op,KnownBits & Known,const APInt & DemandedElts,const SelectionDAG & DAG,unsigned Depth,unsigned OpNo) computeKnownBitsBinOp() argument
7964 computeKnownBitsForTargetNode(const SDValue Op,KnownBits & Known,const APInt & DemandedElts,const SelectionDAG & DAG,unsigned Depth) const computeKnownBitsForTargetNode() argument
8056 computeNumSignBitsBinOp(SDValue Op,const APInt & DemandedElts,const SelectionDAG & DAG,unsigned Depth,unsigned OpNo) computeNumSignBitsBinOp() argument
8080 ComputeNumSignBitsForTargetNode(SDValue Op,const APInt & DemandedElts,const SelectionDAG & DAG,unsigned Depth) const ComputeNumSignBitsForTargetNode() argument
8135 isGuaranteedNotToBeUndefOrPoisonForTargetNode(SDValue Op,const APInt & DemandedElts,const SelectionDAG & DAG,bool PoisonOnly,unsigned Depth) const isGuaranteedNotToBeUndefOrPoisonForTargetNode() argument
[all...]
/llvm-project/llvm/lib/Target/VE/
H A DVECustomDAG.h143 SelectionDAG &DAG; variable
149 VECustomDAG(SelectionDAG &DAG, SDLoc DL) : DAG(DAG), DL(DL) {} in VECustomDAG()
151 VECustomDAG(SelectionDAG &DAG, SDValue WhereOp) : DAG(DAG), DL(WhereOp) {} in VECustomDAG()
153 VECustomDAG(SelectionDAG &DAG, const SDNode *WhereN) : DAG(DAG), DL(WhereN) {} in VECustomDAG()
/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGAddressAnalysis.cpp25 const SelectionDAG &DAG, in equalBaseIndex()
97 const SelectionDAG &DAG, bool &IsAlias) { in computeAliasing()
177 bool BaseIndexOffset::contains(const SelectionDAG &DAG, int64_t BitSize, in contains()
199 const SelectionDAG &DAG) { in matchLSNode()
302 const SelectionDAG &DAG) { in match()
H A DMatchContext.h28 : DAG(DAG), TLI(TLI), Root(Root) {} in EmptyMatchContext() argument
23 SelectionDAG &DAG; global() variable
52 SelectionDAG &DAG; global() variable
59 VPMatchContext(SelectionDAG & DAG,const TargetLowering & TLI,SDNode * _Root) VPMatchContext() argument
[all...]
/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.h26 const ScheduleDAG *DAG; variable
56 const ScheduleDAG &DAG; variable
/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblySelectionDAGInfo.cpp37 auto &ST = DAG.getMachineFunction().getSubtarget<WebAssemblySubtarget>(); in EmitTargetCodeForMemmove() argument
22 EmitTargetCodeForMemcpy(SelectionDAG & DAG,const SDLoc & DL,SDValue Chain,SDValue Dst,SDValue Src,SDValue Size,Align Alignment,bool IsVolatile,bool AlwaysInline,MachinePointerInfo DstPtrInfo,MachinePointerInfo SrcPtrInfo) const EmitTargetCodeForMemcpy() argument
46 EmitTargetCodeForMemset(SelectionDAG & DAG,const SDLoc & DL,SDValue Chain,SDValue Dst,SDValue Val,SDValue Size,Align Alignment,bool IsVolatile,bool AlwaysInline,MachinePointerInfo DstPtrInfo) const EmitTargetCodeForMemset() argument
[all...]
/llvm-project/llvm/lib/Target/X86/
H A DX86SelectionDAGInfo.cpp32 isBaseRegConflictPossible(SelectionDAG & DAG,ArrayRef<MCPhysReg> ClobberSet) const isBaseRegConflictPossible() argument
48 EmitTargetCodeForMemset(SelectionDAG & DAG,const SDLoc & dl,SDValue Chain,SDValue Dst,SDValue Val,SDValue Size,Align Alignment,bool isVolatile,bool AlwaysInline,MachinePointerInfo DstPtrInfo) const EmitTargetCodeForMemset() argument
156 emitRepmovs(const X86Subtarget & Subtarget,SelectionDAG & DAG,const SDLoc & dl,SDValue Chain,SDValue Dst,SDValue Src,SDValue Size,MVT AVT) emitRepmovs() argument
178 emitRepmovsB(const X86Subtarget & Subtarget,SelectionDAG & DAG,const SDLoc & dl,SDValue Chain,SDValue Dst,SDValue Src,uint64_t Size) emitRepmovsB() argument
208 emitConstantSizeRepmov(SelectionDAG & DAG,const X86Subtarget & Subtarget,const SDLoc & dl,SDValue Chain,SDValue Dst,SDValue Src,uint64_t Size,EVT SizeVT,Align Alignment,bool isVolatile,bool AlwaysInline,MachinePointerInfo DstPtrInfo,MachinePointerInfo SrcPtrInfo) emitConstantSizeRepmov() argument
264 EmitTargetCodeForMemcpy(SelectionDAG & DAG,const SDLoc & dl,SDValue Chain,SDValue Dst,SDValue Src,SDValue Size,Align Alignment,bool isVolatile,bool AlwaysInline,MachinePointerInfo DstPtrInfo,MachinePointerInfo SrcPtrInfo) const EmitTargetCodeForMemcpy() argument
[all...]
H A DX86ISelLowering.cpp2610 emitStackGuardXorFP(SelectionDAG & DAG,SDValue Val,const SDLoc & DL) const emitStackGuardXorFP() argument
2845 TranslateX86CC(ISD::CondCode SetCCOpcode,const SDLoc & DL,bool isFP,SDValue & LHS,SDValue & RHS,SelectionDAG & DAG) TranslateX86CC() argument
3265 isLoadBitCastBeneficial(EVT LoadVT,EVT BitcastVT,const SelectionDAG & DAG,const MachineMemOperand & MMO) const isLoadBitCastBeneficial() argument
3496 preferredShiftLegalizationStrategy(SelectionDAG & DAG,SDNode * N,unsigned ExpansionFactor) const preferredShiftLegalizationStrategy() argument
3791 getConstVector(ArrayRef<int> Values,MVT VT,SelectionDAG & DAG,const SDLoc & dl,bool IsMask=false) getConstVector() argument
3822 getConstVector(ArrayRef<APInt> Bits,const APInt & Undefs,MVT VT,SelectionDAG & DAG,const SDLoc & dl) getConstVector() argument
3863 getConstVector(ArrayRef<APInt> Bits,MVT VT,SelectionDAG & DAG,const SDLoc & dl) getConstVector() argument
3870 getZeroVector(MVT VT,const X86Subtarget & Subtarget,SelectionDAG & DAG,const SDLoc & dl) getZeroVector() argument
3919 extractSubVector(SDValue Vec,unsigned IdxVal,SelectionDAG & DAG,const SDLoc & dl,unsigned vectorWidth) extractSubVector() argument
3957 extract128BitVector(SDValue Vec,unsigned IdxVal,SelectionDAG & DAG,const SDLoc & dl) extract128BitVector() argument
3965 extract256BitVector(SDValue Vec,unsigned IdxVal,SelectionDAG & DAG,const SDLoc & dl) extract256BitVector() argument
3971 insertSubVector(SDValue Result,SDValue Vec,unsigned IdxVal,SelectionDAG & DAG,const SDLoc & dl,unsigned vectorWidth) insertSubVector() argument
4001 insert128BitVector(SDValue Result,SDValue Vec,unsigned IdxVal,SelectionDAG & DAG,const SDLoc & dl) insert128BitVector() argument
4009 widenSubVector(MVT VT,SDValue Vec,bool ZeroNewElements,const X86Subtarget & Subtarget,SelectionDAG & DAG,const SDLoc & dl) widenSubVector() argument
4023 widenSubVector(SDValue Vec,bool ZeroNewElements,const X86Subtarget & Subtarget,SelectionDAG & DAG,const SDLoc & dl,unsigned WideSizeInBits) widenSubVector() argument
4047 widenMaskVector(SDValue Vec,bool ZeroNewElements,const X86Subtarget & Subtarget,SelectionDAG & DAG,const SDLoc & dl) widenMaskVector() argument
4057 collectConcatOps(SDNode * N,SmallVectorImpl<SDValue> & Ops,SelectionDAG & DAG) collectConcatOps() argument
4121 isUpperSubvectorUndef(SDValue V,const SDLoc & DL,SelectionDAG & DAG) isUpperSubvectorUndef() argument
4141 isFreeToSplitVector(SDNode * N,SelectionDAG & DAG) isFreeToSplitVector() argument
4146 splitVector(SDValue Op,SelectionDAG & DAG,const SDLoc & dl) splitVector() argument
4165 splitVectorOp(SDValue Op,SelectionDAG & DAG,const SDLoc & dl) splitVectorOp() argument
4190 splitVectorIntUnary(SDValue Op,SelectionDAG & DAG,const SDLoc & dl) splitVectorIntUnary() argument
4206 splitVectorIntBinary(SDValue Op,SelectionDAG & DAG,const SDLoc & dl) splitVectorIntBinary() argument
4224 SplitOpsAndApply(SelectionDAG & DAG,const X86Subtarget & Subtarget,const SDLoc & DL,EVT VT,ArrayRef<SDValue> Ops,F Builder,bool CheckBWI=true) SplitOpsAndApply() argument
4267 getAVX512Node(unsigned Opcode,const SDLoc & DL,MVT VT,ArrayRef<SDValue> Ops,SelectionDAG & DAG,const X86Subtarget & Subtarget) getAVX512Node() argument
4330 insert1BitVector(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) insert1BitVector() argument
4495 concatSubVectors(SDValue V1,SDValue V2,SelectionDAG & DAG,const SDLoc & dl) concatSubVectors() argument
4510 getOnesVector(EVT VT,SelectionDAG & DAG,const SDLoc & dl) getOnesVector() argument
4519 getEXTEND_VECTOR_INREG(unsigned Opcode,const SDLoc & DL,EVT VT,SDValue In,SelectionDAG & DAG) getEXTEND_VECTOR_INREG() argument
4545 getBitSelect(const SDLoc & DL,MVT VT,SDValue LHS,SDValue RHS,SDValue Mask,SelectionDAG & DAG) getBitSelect() argument
4583 getVectorShuffle(SelectionDAG & DAG,EVT VT,const SDLoc & dl,SDValue V1,SDValue V2,ArrayRef<int> Mask) getVectorShuffle() argument
4604 getUnpackl(SelectionDAG & DAG,const SDLoc & dl,EVT VT,SDValue V1,SDValue V2) getUnpackl() argument
4612 getUnpackh(SelectionDAG & DAG,const SDLoc & dl,EVT VT,SDValue V1,SDValue V2) getUnpackh() argument
4622 getPack(SelectionDAG & DAG,const X86Subtarget & Subtarget,const SDLoc & dl,MVT VT,SDValue LHS,SDValue RHS,bool PackHiHalf=false) getPack() argument
4692 getShuffleVectorZeroOrUndef(SDValue V2,int Idx,bool IsZero,const X86Subtarget & Subtarget,SelectionDAG & DAG) getShuffleVectorZeroOrUndef() argument
5117 IsNOT(SDValue V,SelectionDAG & DAG) IsNOT() argument
5832 getFauxShuffleMask(SDValue N,const APInt & DemandedElts,SmallVectorImpl<int> & Mask,SmallVectorImpl<SDValue> & Ops,const SelectionDAG & DAG,unsigned Depth,bool ResolveKnownElts) getFauxShuffleMask() argument
6349 getTargetShuffleInputs(SDValue Op,const APInt & DemandedElts,SmallVectorImpl<SDValue> & Inputs,SmallVectorImpl<int> & Mask,APInt & KnownUndef,APInt & KnownZero,const SelectionDAG & DAG,unsigned Depth,bool ResolveKnownElts) getTargetShuffleInputs() argument
6374 getTargetShuffleInputs(SDValue Op,const APInt & DemandedElts,SmallVectorImpl<SDValue> & Inputs,SmallVectorImpl<int> & Mask,const SelectionDAG & DAG,unsigned Depth,bool ResolveKnownElts) getTargetShuffleInputs() argument
6383 getTargetShuffleInputs(SDValue Op,SmallVectorImpl<SDValue> & Inputs,SmallVectorImpl<int> & Mask,const SelectionDAG & DAG,unsigned Depth=0,bool ResolveKnownElts=true) getTargetShuffleInputs() argument
6398 getBROADCAST_LOAD(unsigned Opcode,const SDLoc & DL,EVT VT,EVT MemVT,MemSDNode * Mem,unsigned Offset,SelectionDAG & DAG) getBROADCAST_LOAD() argument
6422 getShuffleScalarElt(SDValue Op,unsigned Index,SelectionDAG & DAG,unsigned Depth) getShuffleScalarElt() argument
6525 LowerBuildVectorAsInsert(SDValue Op,const SDLoc & DL,const APInt & NonZeroMask,unsigned NumNonZero,unsigned NumZero,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerBuildVectorAsInsert() argument
6567 LowerBuildVectorv16i8(SDValue Op,const SDLoc & DL,const APInt & NonZeroMask,unsigned NumNonZero,unsigned NumZero,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerBuildVectorv16i8() argument
6649 LowerBuildVectorv8i16(SDValue Op,const SDLoc & DL,const APInt & NonZeroMask,unsigned NumNonZero,unsigned NumZero,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerBuildVectorv8i16() argument
6661 LowerBuildVectorv4x32(SDValue Op,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerBuildVectorv4x32() argument
6787 getVShift(bool isLeft,EVT VT,SDValue SrcOp,unsigned NumBits,SelectionDAG & DAG,const TargetLowering & TLI,const SDLoc & dl) getVShift() argument
6799 LowerAsSplatVectorLoad(SDValue SrcOp,MVT VT,const SDLoc & dl,SelectionDAG & DAG) LowerAsSplatVectorLoad() argument
6921 EltsFromConsecutiveLoads(EVT VT,ArrayRef<SDValue> Elts,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget,bool IsAfterLegalize) EltsFromConsecutiveLoads() argument
7203 combineToConsecutiveLoads(EVT VT,SDValue Op,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget,bool IsAfterLegalize) combineToConsecutiveLoads() argument
7305 lowerBuildVectorAsBroadcast(BuildVectorSDNode * BVOp,const SDLoc & dl,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerBuildVectorAsBroadcast() argument
7571 buildFromShuffleMostly(SDValue Op,const SDLoc & DL,SelectionDAG & DAG) buildFromShuffleMostly() argument
7642 LowerBUILD_VECTORvXbf16(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerBUILD_VECTORvXbf16() argument
7657 LowerBUILD_VECTORvXi1(SDValue Op,const SDLoc & dl,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerBUILD_VECTORvXi1() argument
7781 isHorizontalBinOpPart(const BuildVectorSDNode * N,unsigned Opcode,const SDLoc & DL,SelectionDAG & DAG,unsigned BaseIdx,unsigned LastIdx,SDValue & V0,SDValue & V1) isHorizontalBinOpPart() argument
7895 ExpandHorizontalBinOp(const SDValue & V0,const SDValue & V1,const SDLoc & DL,SelectionDAG & DAG,unsigned X86Opcode,bool Mode,bool isUndefLO,bool isUndefHI) ExpandHorizontalBinOp() argument
7936 isAddSubOrSubAdd(const BuildVectorSDNode * BV,const X86Subtarget & Subtarget,SelectionDAG & DAG,SDValue & Opnd0,SDValue & Opnd1,unsigned & NumExtracts,bool & IsSubAdd) isAddSubOrSubAdd() argument
8063 isFMAddSubOrFMSubAdd(const X86Subtarget & Subtarget,SelectionDAG & DAG,SDValue & Opnd0,SDValue & Opnd1,SDValue & Opnd2,unsigned ExpectedUses) isFMAddSubOrFMSubAdd() argument
8093 lowerToAddSubOrFMAddSub(const BuildVectorSDNode * BV,const SDLoc & DL,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerToAddSubOrFMAddSub() argument
8130 isHopBuildVector(const BuildVectorSDNode * BV,SelectionDAG & DAG,unsigned & HOpcode,SDValue & V0,SDValue & V1) isHopBuildVector() argument
8220 getHopForBuildVector(const BuildVectorSDNode * BV,const SDLoc & DL,SelectionDAG & DAG,unsigned HOpcode,SDValue V0,SDValue V1) getHopForBuildVector() argument
8259 LowerToHorizontalOp(const BuildVectorSDNode * BV,const SDLoc & DL,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerToHorizontalOp() argument
8383 lowerBuildVectorToBitOp(BuildVectorSDNode * Op,const SDLoc & DL,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerBuildVectorToBitOp() argument
8459 materializeVectorConstant(SDValue Op,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) materializeVectorConstant() argument
8484 createVariablePermute(MVT VT,SDValue SrcVec,SDValue IndicesVec,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) createVariablePermute() argument
8615 __anon0268aba81b02(SelectionDAG &DAG, const SDLoc &DL, ArrayRef<SDValue> Ops) createVariablePermute() argument
8753 LowerBUILD_VECTORAsVariablePermute(SDValue V,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerBUILD_VECTORAsVariablePermute() argument
9238 LowerAVXCONCAT_VECTORS(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerAVXCONCAT_VECTORS() argument
9307 LowerCONCAT_VECTORSvXi1(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerCONCAT_VECTORSvXi1() argument
9382 LowerCONCAT_VECTORS(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerCONCAT_VECTORS() argument
9680 isTargetShuffleEquivalent(MVT VT,ArrayRef<int> Mask,ArrayRef<int> ExpectedMask,const SelectionDAG & DAG,SDValue V1=SDValue (),SDValue V2=SDValue ()) isTargetShuffleEquivalent() argument
9740 isUnpackWdShuffleMask(ArrayRef<int> Mask,MVT VT,const SelectionDAG & DAG) isUnpackWdShuffleMask() argument
9756 is128BitUnpackShuffleMask(ArrayRef<int> Mask,const SelectionDAG & DAG) is128BitUnpackShuffleMask() argument
9823 getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,const SDLoc & DL,SelectionDAG & DAG) getV4X86ShuffleImm8ForMask() argument
9864 lowerShuffleWithPSHUFB(const SDLoc & DL,MVT VT,ArrayRef<int> Mask,SDValue V1,SDValue V2,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleWithPSHUFB() argument
9921 lowerShuffleToEXPAND(const SDLoc & DL,MVT VT,const APInt & Zeroable,ArrayRef<int> Mask,SDValue & V1,SDValue & V2,SelectionDAG & DAG,const X86Subtarget & Subtarget) lowerShuffleToEXPAND() argument
9944 matchShuffleWithUNPCK(MVT VT,SDValue & V1,SDValue & V2,unsigned & UnpackOpcode,bool IsUnary,ArrayRef<int> TargetMask,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) matchShuffleWithUNPCK() argument
10032 lowerShuffleWithUNPCK(const SDLoc & DL,MVT VT,ArrayRef<int> Mask,SDValue V1,SDValue V2,SelectionDAG & DAG) lowerShuffleWithUNPCK() argument
10059 lowerShuffleWithUNPCK256(const SDLoc & DL,MVT VT,ArrayRef<int> Mask,SDValue V1,SDValue V2,SelectionDAG & DAG) lowerShuffleWithUNPCK256() argument
10123 getAVX512TruncNode(const SDLoc & DL,MVT DstVT,SDValue Src,const X86Subtarget & Subtarget,SelectionDAG & DAG,bool ZeroUppers) getAVX512TruncNode() argument
10186 lowerShuffleWithVPMOV(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleWithVPMOV() argument
10236 lowerShuffleAsVTRUNC(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsVTRUNC() argument
10388 matchShuffleWithPACK(MVT VT,MVT & SrcVT,SDValue & V1,SDValue & V2,unsigned & PackOpcode,ArrayRef<int> TargetMask,const SelectionDAG & DAG,const X86Subtarget & Subtarget,unsigned MaxStages=1) matchShuffleWithPACK() argument
10458 lowerShuffleWithPACK(const SDLoc & DL,MVT VT,ArrayRef<int> Mask,SDValue V1,SDValue V2,SelectionDAG & DAG,const X86Subtarget & Subtarget) lowerShuffleWithPACK() argument
10510 lowerShuffleAsBitMask(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsBitMask() argument
10564 lowerShuffleAsBitBlend(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,SelectionDAG & DAG) lowerShuffleAsBitBlend() argument
10673 lowerShuffleAsBlend(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Original,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsBlend() argument
10833 lowerShuffleAsBlendAndPermute(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,SelectionDAG & DAG,bool ImmBlends=false) lowerShuffleAsBlendAndPermute() argument
10872 lowerShuffleAsUNPCKAndPermute(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,SelectionDAG & DAG) lowerShuffleAsUNPCKAndPermute() argument
10956 lowerShuffleAsPermuteAndUnpack(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsPermuteAndUnpack() argument
11065 lowerShuffleAsByteRotateAndPermute(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsByteRotateAndPermute() argument
11182 lowerShuffleAsDecomposedShuffleMerge(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsDecomposedShuffleMerge() argument
11321 lowerShuffleAsBitRotate(const SDLoc & DL,MVT VT,SDValue V1,ArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsBitRotate() argument
11472 lowerShuffleAsByteRotate(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsByteRotate() argument
11530 lowerShuffleAsVALIGN(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsVALIGN() argument
11581 lowerShuffleAsByteShiftMask(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsByteShiftMask() argument
11730 lowerShuffleAsShift(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG,bool BitwiseOnly) lowerShuffleAsShift() argument
11889 lowerShuffleWithSSE4A(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,SelectionDAG & DAG) lowerShuffleWithSSE4A() argument
11916 lowerShuffleAsSpecificZeroOrAnyExtend(const SDLoc & DL,MVT VT,int Scale,int Offset,bool AnyExt,SDValue InputV,ArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsSpecificZeroOrAnyExtend() argument
12081 lowerShuffleAsZeroOrAnyExtend(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsZeroOrAnyExtend() argument
12198 getScalarValueForVectorElement(SDValue V,int Idx,SelectionDAG & DAG) getScalarValueForVectorElement() argument
12243 lowerShuffleAsElementInsertion(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsElementInsertion() argument
12369 lowerShuffleAsTruncBroadcast(const SDLoc & DL,MVT VT,SDValue V0,int BroadcastIdx,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsTruncBroadcast() argument
12457 lowerShuffleOfExtractsAsVperm(const SDLoc & DL,SDValue N0,SDValue N1,ArrayRef<int> Mask,SelectionDAG & DAG) lowerShuffleOfExtractsAsVperm() argument
12512 lowerShuffleAsBroadcast(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsBroadcast() argument
12706 matchShuffleAsInsertPS(SDValue & V1,SDValue & V2,unsigned & InsertPSMask,const APInt & Zeroable,ArrayRef<int> Mask,SelectionDAG & DAG) matchShuffleAsInsertPS() argument
12793 lowerShuffleAsInsertPS(const SDLoc & DL,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,SelectionDAG & DAG) lowerShuffleAsInsertPS() argument
12817 lowerV2F64Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV2F64Shuffle() argument
12901 lowerV2I64Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV2I64Shuffle() argument
13000 lowerShuffleWithSHUFPS(const SDLoc & DL,MVT VT,ArrayRef<int> Mask,SDValue V1,SDValue V2,SelectionDAG & DAG) lowerShuffleWithSHUFPS() argument
13093 lowerV4F32Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV4F32Shuffle() argument
13197 lowerV4I32Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV4I32Shuffle() argument
13337 lowerV8I16GeneralSingleInputShuffle(const SDLoc & DL,MVT VT,SDValue V,MutableArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV8I16GeneralSingleInputShuffle() argument
13831 lowerShuffleAsBlendOfPSHUFBs(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,SelectionDAG & DAG,bool & V1InUse,bool & V2InUse) lowerShuffleAsBlendOfPSHUFBs() argument
13895 lowerV8I16Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV8I16Shuffle() argument
14099 lowerV8F16Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV8F16Shuffle() argument
14130 lowerShuffleWithPERMV(const SDLoc & DL,MVT VT,ArrayRef<int> Mask,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleWithPERMV() argument
14174 lowerV16I8Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV16I8Shuffle() argument
14529 lower128BitShuffle(const SDLoc & DL,ArrayRef<int> Mask,MVT VT,SDValue V1,SDValue V2,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lower128BitShuffle() argument
14565 splitAndLowerShuffle(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,SelectionDAG & DAG,bool SimpleOnly) splitAndLowerShuffle() argument
14695 lowerShuffleAsSplitOrBlend(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsSplitOrBlend() argument
14749 lowerShuffleAsLanePermuteAndSHUFP(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,SelectionDAG & DAG) lowerShuffleAsLanePermuteAndSHUFP() argument
14784 lowerShuffleAsLanePermuteAndPermute(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,SelectionDAG & DAG,const X86Subtarget & Subtarget) lowerShuffleAsLanePermuteAndPermute() argument
14907 lowerShuffleAsLanePermuteAndShuffle(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,SelectionDAG & DAG,const X86Subtarget & Subtarget) lowerShuffleAsLanePermuteAndShuffle() argument
14968 lowerV2X128Shuffle(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV2X128Shuffle() argument
15086 lowerShuffleAsLanePermuteAndRepeatedMask(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsLanePermuteAndRepeatedMask() argument
15311 getShuffleHalfVectors(const SDLoc & DL,SDValue V1,SDValue V2,ArrayRef<int> HalfMask,int HalfIdx1,int HalfIdx2,bool UndefLower,SelectionDAG & DAG,bool UseConcat=false) getShuffleHalfVectors() argument
15351 lowerShuffleWithUndefHalf(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleWithUndefHalf() argument
15461 lowerShuffleAsRepeatedMaskAndLanePermute(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsRepeatedMaskAndLanePermute() argument
15707 lowerShuffleWithSHUFPD(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleWithSHUFPD() argument
15734 lowerShuffleAsVTRUNCAndUnpack(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,SelectionDAG & DAG) lowerShuffleAsVTRUNCAndUnpack() argument
15781 lowerShufflePairAsUNPCKAndPermute(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,SelectionDAG & DAG) lowerShufflePairAsUNPCKAndPermute() argument
15854 lowerV4F64Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV4F64Shuffle() argument
15974 lowerV4I64Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV4I64Shuffle() argument
16087 lowerV8F32Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV8F32Shuffle() argument
16209 lowerV8I32Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV8I32Shuffle() argument
16351 lowerV16I16Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV16I16Shuffle() argument
16474 lowerV32I8Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV32I8Shuffle() argument
16596 lower256BitShuffle(const SDLoc & DL,ArrayRef<int> Mask,MVT VT,SDValue V1,SDValue V2,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lower256BitShuffle() argument
16668 lowerV4X128Shuffle(const SDLoc & DL,MVT VT,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV4X128Shuffle() argument
16774 lowerV8F64Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV8F64Shuffle() argument
16828 lowerV16F32Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV16F32Shuffle() argument
16895 lowerV8I64Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV8I64Shuffle() argument
16968 lowerV16I32Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV16I32Shuffle() argument
17065 lowerV32I16Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV32I16Shuffle() argument
17129 lowerV64I8Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV64I8Shuffle() argument
17228 lower512BitShuffle(const SDLoc & DL,ArrayRef<int> Mask,MVT VT,SDValue V1,SDValue V2,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lower512BitShuffle() argument
17301 lower1BitShuffleAsKSHIFTR(const SDLoc & DL,ArrayRef<int> Mask,MVT VT,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lower1BitShuffleAsKSHIFTR() argument
17377 lower1BitShuffle(const SDLoc & DL,ArrayRef<int> Mask,MVT VT,SDValue V1,SDValue V2,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lower1BitShuffle() argument
17641 lowerVECTOR_SHUFFLE(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerVECTOR_SHUFFLE() argument
17784 lowerVSELECTtoVectorShuffle(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerVSELECTtoVectorShuffle() argument
17914 LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,SelectionDAG & DAG) LowerEXTRACT_VECTOR_ELT_SSE4() argument
17965 ExtractBitFromMaskVector(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) ExtractBitFromMaskVector() argument
18201 InsertBitToMaskVector(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) InsertBitToMaskVector() argument
18438 LowerSCALAR_TO_VECTOR(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerSCALAR_TO_VECTOR() argument
18477 LowerINSERT_SUBVECTOR(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerINSERT_SUBVECTOR() argument
18484 LowerEXTRACT_SUBVECTOR(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerEXTRACT_SUBVECTOR() argument
18607 LowerGlobalOrExternal(SDValue Op,SelectionDAG & DAG,bool ForCall) const LowerGlobalOrExternal() argument
18687 GetTLSADDR(SelectionDAG & DAG,SDValue Chain,GlobalAddressSDNode * GA,SDValue * InGlue,const EVT PtrVT,unsigned ReturnReg,unsigned char OperandFlags,bool LocalDynamic=false) GetTLSADDR() argument
18740 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode * GA,SelectionDAG & DAG,const EVT PtrVT) LowerToTLSGeneralDynamicModel32() argument
18754 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode * GA,SelectionDAG & DAG,const EVT PtrVT) LowerToTLSGeneralDynamicModel64() argument
18762 LowerToTLSGeneralDynamicModelX32(GlobalAddressSDNode * GA,SelectionDAG & DAG,const EVT PtrVT) LowerToTLSGeneralDynamicModelX32() argument
18769 LowerToTLSLocalDynamicModel(GlobalAddressSDNode * GA,SelectionDAG & DAG,const EVT PtrVT,bool Is64Bit,bool Is64BitLP64) LowerToTLSLocalDynamicModel() argument
18808 LowerToTLSExecModel(GlobalAddressSDNode * GA,SelectionDAG & DAG,const EVT PtrVT,TLSModel::Model model,bool is64Bit,bool isPIC) LowerToTLSExecModel() argument
19035 LowerShiftParts(SDValue Op,SelectionDAG & DAG) LowerShiftParts() argument
19044 LowerI64IntToFP_AVX512DQ(SDValue Op,const SDLoc & dl,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerI64IntToFP_AVX512DQ() argument
19085 LowerI64IntToFP16(SDValue Op,const SDLoc & dl,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerI64IntToFP16() argument
19146 vectorizeExtractedCast(SDValue Cast,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) vectorizeExtractedCast() argument
19188 lowerFPToIntToFP(SDValue CastToFP,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) lowerFPToIntToFP() argument
19235 lowerINT_TO_FP_vXi64(SDValue Op,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) lowerINT_TO_FP_vXi64() argument
19324 promoteXINT_TO_FP(SDValue Op,const SDLoc & dl,SelectionDAG & DAG) promoteXINT_TO_FP() argument
19504 shouldUseHorizontalOp(bool IsSingleSource,SelectionDAG & DAG,const X86Subtarget & Subtarget) shouldUseHorizontalOp() argument
19513 LowerUINT_TO_FP_i64(SDValue Op,const SDLoc & dl,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerUINT_TO_FP_i64() argument
19581 LowerUINT_TO_FP_i32(SDValue Op,const SDLoc & dl,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerUINT_TO_FP_i32() argument
19631 lowerUINT_TO_FP_v2i32(SDValue Op,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) lowerUINT_TO_FP_v2i32() argument
19684 lowerUINT_TO_FP_vXi32(SDValue Op,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) lowerUINT_TO_FP_vXi32() argument
19841 lowerUINT_TO_FP_vec(SDValue Op,const SDLoc & dl,SelectionDAG & DAG,const X86Subtarget & Subtarget) lowerUINT_TO_FP_vec() argument
20020 FP_TO_INTHelper(SDValue Op,SelectionDAG & DAG,bool IsSigned,SDValue & Chain) const FP_TO_INTHelper() argument
20174 LowerAVXExtend(SDValue Op,const SDLoc & dl,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerAVXExtend() argument
20237 SplitAndExtendv16i1(unsigned ExtOpc,MVT VT,SDValue In,const SDLoc & dl,SelectionDAG & DAG) SplitAndExtendv16i1() argument
20251 LowerZERO_EXTEND_Mask(SDValue Op,const SDLoc & DL,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerZERO_EXTEND_Mask() argument
20307 LowerZERO_EXTEND(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerZERO_EXTEND() argument
20325 truncateVectorWithPACK(unsigned Opcode,EVT DstVT,SDValue In,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) truncateVectorWithPACK() argument
20448 truncateVectorWithPACKUS(EVT DstVT,SDValue In,const SDLoc & DL,const X86Subtarget & Subtarget,SelectionDAG & DAG) truncateVectorWithPACKUS() argument
20456 truncateVectorWithPACKSS(EVT DstVT,SDValue In,const SDLoc & DL,const X86Subtarget & Subtarget,SelectionDAG & DAG) truncateVectorWithPACKSS() argument
20468 matchTruncateWithPACK(unsigned & PackOpcode,EVT DstVT,SDValue In,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) matchTruncateWithPACK() argument
20559 LowerTruncateVecPackWithSignBits(MVT DstVT,SDValue In,const SDLoc & DL,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerTruncateVecPackWithSignBits() argument
20592 LowerTruncateVecPack(MVT DstVT,SDValue In,const SDLoc & DL,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerTruncateVecPack() argument
20642 LowerTruncateVecI1(SDValue Op,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerTruncateVecI1() argument
20845 expandFP_TO_UINT_SSE(MVT VT,SDValue Src,const SDLoc & dl,SelectionDAG & DAG,const X86Subtarget & Subtarget) expandFP_TO_UINT_SSE() argument
21664 LowerFP16_TO_FP(SDValue Op,SelectionDAG & DAG) LowerFP16_TO_FP() argument
21693 LowerFP_TO_FP16(SDValue Op,SelectionDAG & DAG) LowerFP_TO_FP16() argument
21750 lowerAddSubToHorizontalOp(SDValue Op,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) lowerAddSubToHorizontalOp() argument
21833 LowerFROUND(SDValue Op,SelectionDAG & DAG) LowerFROUND() argument
21855 LowerFABSorFNEG(SDValue Op,SelectionDAG & DAG) LowerFABSorFNEG() argument
21916 LowerFCOPYSIGN(SDValue Op,SelectionDAG & DAG) LowerFCOPYSIGN() argument
21985 LowerFGETSIGN(SDValue Op,SelectionDAG & DAG) LowerFGETSIGN() argument
22004 getBT(SDValue Src,SDValue BitNo,const SDLoc & DL,SelectionDAG & DAG) getBT() argument
22046 getSETCC(X86::CondCode Cond,SDValue EFLAGS,const SDLoc & dl,SelectionDAG & DAG) getSETCC() argument
22065 emitOrXorXorTree(SDValue X,const SDLoc & DL,SelectionDAG & DAG,EVT VecVT,EVT CmpVT,bool HasPT,F SToV) emitOrXorXorTree() argument
22095 combineVectorSizedSetCCEquality(EVT VT,SDValue X,SDValue Y,ISD::CondCode CC,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineVectorSizedSetCCEquality() argument
22315 LowerVectorAllEqual(const SDLoc & DL,SDValue LHS,SDValue RHS,ISD::CondCode CC,const APInt & OriginalMask,const X86Subtarget & Subtarget,SelectionDAG & DAG,X86::CondCode & X86CC) LowerVectorAllEqual() argument
22463 MatchVectorAllEqualTest(SDValue LHS,SDValue RHS,ISD::CondCode CC,const SDLoc & DL,const X86Subtarget & Subtarget,SelectionDAG & DAG,X86::CondCode & X86CC) MatchVectorAllEqualTest() argument
22621 EmitTest(SDValue Op,unsigned X86CC,const SDLoc & dl,SelectionDAG & DAG,const X86Subtarget & Subtarget) EmitTest() argument
22731 EmitCmp(SDValue Op0,SDValue Op1,unsigned X86CC,const SDLoc & dl,SelectionDAG & DAG,const X86Subtarget & Subtarget) EmitCmp() argument
22851 getSqrtEstimate(SDValue Op,SelectionDAG & DAG,int Enabled,int & RefinementSteps,bool & UseOneConstNR,bool Reciprocal) const getSqrtEstimate() argument
22904 getRecipEstimate(SDValue Op,SelectionDAG & DAG,int Enabled,int & RefinementSteps) const getRecipEstimate() argument
22965 BuildSDIVPow2(SDNode * N,const APInt & Divisor,SelectionDAG & DAG,SmallVectorImpl<SDNode * > & Created) const BuildSDIVPow2() argument
22997 LowerAndToBT(SDValue And,ISD::CondCode CC,const SDLoc & dl,SelectionDAG & DAG,X86::CondCode & X86CC) LowerAndToBT() argument
23134 splitIntVSETCC(EVT VT,SDValue LHS,SDValue RHS,ISD::CondCode Cond,SelectionDAG & DAG,const SDLoc & dl) splitIntVSETCC() argument
23158 LowerIntVSETCC_AVX512(SDValue Op,const SDLoc & dl,SelectionDAG & DAG) LowerIntVSETCC_AVX512() argument
23181 incDecVectorConstant(SDValue V,SelectionDAG & DAG,bool IsInc,bool NSW) incDecVectorConstant() argument
23218 LowerVSETCCWithSUBUS(SDValue Op0,SDValue Op1,MVT VT,ISD::CondCode Cond,const SDLoc & dl,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerVSETCCWithSUBUS() argument
23271 LowerVSETCC(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerVSETCC() argument
23722 EmitAVX512Test(SDValue Op0,SDValue Op1,ISD::CondCode CC,const SDLoc & dl,SelectionDAG & DAG,const X86Subtarget & Subtarget,SDValue & X86CC) EmitAVX512Test() argument
23778 emitFlagsForSetcc(SDValue Op0,SDValue Op1,ISD::CondCode CC,const SDLoc & dl,SelectionDAG & DAG,SDValue & X86CC) const emitFlagsForSetcc() argument
23980 getX86XALUOOp(X86::CondCode & Cond,SDValue Op,SelectionDAG & DAG) getX86XALUOOp() argument
24025 LowerXALUO(SDValue Op,SelectionDAG & DAG) LowerXALUO() argument
24055 isTruncWithZeroHighBitsInput(SDValue V,SelectionDAG & DAG) isTruncWithZeroHighBitsInput() argument
24378 LowerSIGN_EXTEND_Mask(SDValue Op,const SDLoc & dl,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerSIGN_EXTEND_Mask() argument
24432 LowerANY_EXTEND(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerANY_EXTEND() argument
24450 LowerEXTEND_VECTOR_INREG(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerEXTEND_VECTOR_INREG() argument
24572 LowerSIGN_EXTEND(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerSIGN_EXTEND() argument
24624 splitVectorStore(StoreSDNode * Store,SelectionDAG & DAG) splitVectorStore() argument
24659 scalarizeVectorStore(StoreSDNode * Store,MVT StoreVT,SelectionDAG & DAG) scalarizeVectorStore() argument
24693 LowerStore(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerStore() argument
24780 LowerLoad(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerLoad() argument
25160 LowerVACOPY(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerVACOPY() argument
25206 getTargetVShiftByConstNode(unsigned Opc,const SDLoc & dl,MVT VT,SDValue SrcOp,uint64_t ShiftAmt,SelectionDAG & DAG) getTargetVShiftByConstNode() argument
25259 getTargetVShiftNode(unsigned Opc,const SDLoc & dl,MVT VT,SDValue SrcOp,SDValue ShAmt,int ShAmtIdx,const X86Subtarget & Subtarget,SelectionDAG & DAG) getTargetVShiftNode() argument
25354 getMaskNode(SDValue Mask,MVT MaskVT,const X86Subtarget & Subtarget,SelectionDAG & DAG,const SDLoc & dl) getMaskNode() argument
25390 getVectorMaskingNode(SDValue Op,SDValue Mask,SDValue PreservedSrc,const X86Subtarget & Subtarget,SelectionDAG & DAG) getVectorMaskingNode() argument
25416 getScalarMaskingNode(SDValue Op,SDValue Mask,SDValue PreservedSrc,const X86Subtarget & Subtarget,SelectionDAG & DAG) getScalarMaskingNode() argument
25462 recoverFramePointer(SelectionDAG & DAG,const Function * Fn,SDValue EntryEBP) recoverFramePointer() argument
26519 getAVX2GatherNode(unsigned Opc,SDValue Op,SelectionDAG & DAG,SDValue Src,SDValue Mask,SDValue Base,SDValue Index,SDValue ScaleOp,SDValue Chain,const X86Subtarget & Subtarget) getAVX2GatherNode() argument
26551 getGatherNode(SDValue Op,SelectionDAG & DAG,SDValue Src,SDValue Mask,SDValue Base,SDValue Index,SDValue ScaleOp,SDValue Chain,const X86Subtarget & Subtarget) getGatherNode() argument
26589 getScatterNode(unsigned Opc,SDValue Op,SelectionDAG & DAG,SDValue Src,SDValue Mask,SDValue Base,SDValue Index,SDValue ScaleOp,SDValue Chain,const X86Subtarget & Subtarget) getScatterNode() argument
26620 getPrefetchNode(unsigned Opc,SDValue Op,SelectionDAG & DAG,SDValue Mask,SDValue Base,SDValue Index,SDValue ScaleOp,SDValue Chain,const X86Subtarget & Subtarget) getPrefetchNode() argument
26651 expandIntrinsicWChainHelper(SDNode * N,const SDLoc & DL,SelectionDAG & DAG,unsigned TargetOpcode,unsigned SrcReg,const X86Subtarget & Subtarget,SmallVectorImpl<SDValue> & Results) expandIntrinsicWChainHelper() argument
26706 getReadTimeStampCounter(SDNode * N,const SDLoc & DL,unsigned Opcode,SelectionDAG & DAG,const X86Subtarget & Subtarget,SmallVectorImpl<SDValue> & Results) getReadTimeStampCounter() argument
26727 LowerREADCYCLECOUNTER(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerREADCYCLECOUNTER() argument
26735 MarkEHRegistrationNode(SDValue Op,SelectionDAG & DAG) MarkEHRegistrationNode() argument
26753 MarkEHGuard(SDValue Op,SelectionDAG & DAG) MarkEHGuard() argument
26775 EmitTruncSStore(bool SignedSat,SDValue Chain,const SDLoc & DL,SDValue Val,SDValue Ptr,EVT MemVT,MachineMemOperand * MMO,SelectionDAG & DAG) EmitTruncSStore() argument
26787 EmitMaskedTruncSStore(bool SignedSat,SDValue Chain,const SDLoc & DL,SDValue Val,SDValue Ptr,SDValue Mask,EVT MemVT,MachineMemOperand * MMO,SelectionDAG & DAG) EmitMaskedTruncSStore() argument
26804 LowerINTRINSIC_W_CHAIN(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerINTRINSIC_W_CHAIN() argument
27495 LowerADJUST_TRAMPOLINE(SDValue Op,SelectionDAG & DAG) LowerADJUST_TRAMPOLINE() argument
27871 createSetFPEnvNodes(SDValue Ptr,SDValue Chain,SDLoc DL,EVT MemVT,MachineMemOperand * MMO,SelectionDAG & DAG,const X86Subtarget & Subtarget) createSetFPEnvNodes() argument
27944 LowerVectorCTLZ_AVX512CDI(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerVectorCTLZ_AVX512CDI() argument
27976 LowerVectorCTLZInRegLUT(SDValue Op,const SDLoc & DL,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerVectorCTLZInRegLUT() argument
28058 LowerVectorCTLZ(SDValue Op,const SDLoc & DL,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerVectorCTLZ() argument
28079 LowerCTLZ(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerCTLZ() argument
28118 LowerCTTZ(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerCTTZ() argument
28142 lowerAddSub(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) lowerAddSub() argument
28159 LowerADDSAT_SUBSAT(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerADDSAT_SUBSAT() argument
28230 LowerABS(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerABS() argument
28266 LowerAVG(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerAVG() argument
28282 LowerMINMAX(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerMINMAX() argument
28298 LowerFMINIMUM_FMAXIMUM(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerFMINIMUM_FMAXIMUM() argument
28446 LowerABD(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerABD() argument
28481 LowerMUL(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerMUL() argument
28655 LowervXi8MulWithUNPCK(SDValue A,SDValue B,const SDLoc & dl,MVT VT,bool IsSigned,const X86Subtarget & Subtarget,SelectionDAG & DAG,SDValue * Low=nullptr) LowervXi8MulWithUNPCK() argument
28732 LowerMULH(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerMULH() argument
28839 LowerMULO(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerMULO() argument
29035 LowerWin64_FP_TO_INT128(SDValue Op,SelectionDAG & DAG,SDValue & Chain) const LowerWin64_FP_TO_INT128() argument
29193 LowerShiftByScalarImmediate(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerShiftByScalarImmediate() argument
29356 LowerShiftByScalarVariable(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerShiftByScalarVariable() argument
29422 convertShiftLeftToScale(SDValue Amt,const SDLoc & dl,const X86Subtarget & Subtarget,SelectionDAG & DAG) convertShiftLeftToScale() argument
29476 LowerShift(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerShift() argument
29961 LowerFunnelShift(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerFunnelShift() argument
30163 LowerRotate(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerRotate() argument
31003 emitLockedStackOp(SelectionDAG & DAG,const X86Subtarget & Subtarget,SDValue Chain,const SDLoc & DL) emitLockedStackOp() argument
31065 LowerATOMIC_FENCE(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerATOMIC_FENCE() argument
31088 LowerCMP_SWAP(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerCMP_SWAP() argument
31126 getPMOVMSKB(const SDLoc & DL,SDValue V,SelectionDAG & DAG,const X86Subtarget & Subtarget) getPMOVMSKB() argument
31155 LowerBITCAST(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerBITCAST() argument
31224 LowerHorizontalByteSum(SDValue V,MVT VT,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerHorizontalByteSum() argument
31288 LowerVectorCTPOPInRegLUT(SDValue Op,const SDLoc & DL,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerVectorCTPOPInRegLUT() argument
31335 LowerVectorCTPOP(SDValue Op,const SDLoc & DL,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerVectorCTPOP() argument
31378 LowerCTPOP(SDValue N,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerCTPOP() argument
31464 LowerBITREVERSE_XOP(SDValue Op,SelectionDAG & DAG) LowerBITREVERSE_XOP() argument
31510 LowerBITREVERSE(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerBITREVERSE() argument
31600 LowerPARITY(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerPARITY() argument
31655 lowerAtomicArithWithLOCK(SDValue N,SelectionDAG & DAG,const X86Subtarget & Subtarget) lowerAtomicArithWithLOCK() argument
31687 lowerAtomicArith(SDValue N,SelectionDAG & DAG,const X86Subtarget & Subtarget) lowerAtomicArith() argument
31755 LowerATOMIC_STORE(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerATOMIC_STORE() argument
31837 LowerADDSUBO_CARRY(SDValue Op,SelectionDAG & DAG) LowerADDSUBO_CARRY() argument
31870 LowerFSINCOS(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerFSINCOS() argument
31925 ExtendToType(SDValue InOp,MVT NVT,SelectionDAG & DAG,bool FillWithZeroes=false) ExtendToType() argument
31975 LowerMSCATTER(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerMSCATTER() argument
32038 LowerMLOAD(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerMLOAD() argument
32104 LowerMSTORE(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerMSTORE() argument
32146 LowerMGATHER(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerMGATHER() argument
32198 LowerADDRSPACECAST(SDValue Op,SelectionDAG & DAG) LowerADDRSPACECAST() argument
32239 LowerCVTPS2PH(SDValue Op,SelectionDAG & DAG) LowerCVTPS2PH() argument
32253 LowerPREFETCH(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerPREFETCH() argument
32318 getFlagsOfCmpZeroFori1(SelectionDAG & DAG,const SDLoc & DL,SDValue Mask) getFlagsOfCmpZeroFori1() argument
32330 visitMaskedLoad(SelectionDAG & DAG,const SDLoc & DL,SDValue Chain,MachineMemOperand * MMO,SDValue & NewLoad,SDValue Ptr,SDValue PassThru,SDValue Mask) const visitMaskedLoad() argument
32349 visitMaskedStore(SelectionDAG & DAG,const SDLoc & DL,SDValue Chain,MachineMemOperand * MMO,SDValue Ptr,SDValue Val,SDValue Mask) const visitMaskedStore() argument
37125 computeKnownBitsForPSADBW(SDValue LHS,SDValue RHS,KnownBits & Known,const APInt & DemandedElts,const SelectionDAG & DAG,unsigned Depth) computeKnownBitsForPSADBW() argument
37145 computeKnownBitsForPMADDWD(SDValue LHS,SDValue RHS,KnownBits & Known,const APInt & DemandedElts,const SelectionDAG & DAG,unsigned Depth) computeKnownBitsForPMADDWD() argument
37168 computeKnownBitsForPMADDUBSW(SDValue LHS,SDValue RHS,KnownBits & Known,const APInt & DemandedElts,const SelectionDAG & DAG,unsigned Depth) computeKnownBitsForPMADDUBSW() argument
37191 computeKnownBitsForTargetNode(const SDValue Op,KnownBits & Known,const APInt & DemandedElts,const SelectionDAG & DAG,unsigned Depth) const computeKnownBitsForTargetNode() argument
37611 ComputeNumSignBitsForTargetNode(SDValue Op,const APInt & DemandedElts,const SelectionDAG & DAG,unsigned Depth) const ComputeNumSignBitsForTargetNode() argument
37788 narrowLoadToVZLoad(LoadSDNode * LN,MVT MemVT,MVT VT,SelectionDAG & DAG) narrowLoadToVZLoad() argument
37805 matchUnaryShuffle(MVT MaskVT,ArrayRef<int> Mask,bool AllowFloatDomain,bool AllowIntDomain,SDValue V1,const SelectionDAG & DAG,const X86Subtarget & Subtarget,unsigned & Shuffle,MVT & SrcVT,MVT & DstVT) matchUnaryShuffle() argument
37960 matchUnaryPermuteShuffle(MVT MaskVT,ArrayRef<int> Mask,const APInt & Zeroable,bool AllowFloatDomain,bool AllowIntDomain,const SelectionDAG & DAG,const X86Subtarget & Subtarget,unsigned & Shuffle,MVT & ShuffleVT,unsigned & PermuteImm) matchUnaryPermuteShuffle() argument
38109 matchBinaryShuffle(MVT MaskVT,ArrayRef<int> Mask,bool AllowFloatDomain,bool AllowIntDomain,SDValue & V1,SDValue & V2,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget,unsigned & Shuffle,MVT & SrcVT,MVT & DstVT,bool IsUnary) matchBinaryShuffle() argument
38305 matchBinaryPermuteShuffle(MVT MaskVT,ArrayRef<int> Mask,const APInt & Zeroable,bool AllowFloatDomain,bool AllowIntDomain,SDValue & V1,SDValue & V2,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget,unsigned & Shuffle,MVT & ShuffleVT,unsigned & PermuteImm) matchBinaryPermuteShuffle() argument
38484 combineX86ShuffleChain(ArrayRef<SDValue> Inputs,SDValue Root,ArrayRef<int> BaseMask,int Depth,bool HasVariableMask,bool AllowVariableCrossLaneMask,bool AllowVariablePerLaneMask,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineX86ShuffleChain() argument
38594 __anon0268aba87802(MVT ShuffleVT, const SDLoc &DL, ArrayRef<int> ScaledMask, SDValue V1, SDValue V2, SelectionDAG &DAG) combineX86ShuffleChain() argument
39229 combineX86ShuffleChainWithExtract(ArrayRef<SDValue> Inputs,SDValue Root,ArrayRef<int> BaseMask,int Depth,bool HasVariableMask,bool AllowVariableCrossLaneMask,bool AllowVariablePerLaneMask,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineX86ShuffleChainWithExtract() argument
39350 canonicalizeShuffleMaskWithHorizOp(MutableArrayRef<SDValue> Ops,MutableArrayRef<int> Mask,unsigned RootSizeInBits,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) canonicalizeShuffleMaskWithHorizOp() argument
39560 combineX86ShufflesConstants(ArrayRef<SDValue> Ops,ArrayRef<int> Mask,SDValue Root,bool HasVariableMask,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineX86ShufflesConstants() argument
39686 combineX86ShufflesRecursively(ArrayRef<SDValue> SrcOps,int SrcOpIndex,SDValue Root,ArrayRef<int> RootMask,ArrayRef<const SDNode * > SrcNodes,unsigned Depth,unsigned MaxDepth,bool HasVariableMask,bool AllowVariableCrossLaneMask,bool AllowVariablePerLaneMask,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineX86ShufflesRecursively() argument
40119 combineX86ShufflesRecursively(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineX86ShufflesRecursively() argument
40177 combineRedundantDWordShuffle(SDValue N,MutableArrayRef<int> Mask,const SDLoc & DL,SelectionDAG & DAG) combineRedundantDWordShuffle() argument
40305 combineCommutableSHUFP(SDValue N,MVT VT,const SDLoc & DL,SelectionDAG & DAG) combineCommutableSHUFP() argument
40360 combineBlendOfPermutes(MVT VT,SDValue N0,SDValue N1,ArrayRef<int> BlendMask,const APInt & DemandedElts,SelectionDAG & DAG,const X86Subtarget & Subtarget,const SDLoc & DL) combineBlendOfPermutes() argument
40464 canonicalizeShuffleWithOp(SDValue N,SelectionDAG & DAG,const SDLoc & DL) canonicalizeShuffleWithOp() argument
40623 canonicalizeLaneShuffleWithRepeatedOps(SDValue V,SelectionDAG & DAG,const SDLoc & DL) canonicalizeLaneShuffleWithRepeatedOps() argument
40675 combineTargetShuffle(SDValue N,const SDLoc & DL,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineTargetShuffle() argument
41481 isAddSubOrSubAdd(SDNode * N,const X86Subtarget & Subtarget,SelectionDAG & DAG,SDValue & Opnd0,SDValue & Opnd1,bool & IsSubAdd) isAddSubOrSubAdd() argument
41542 combineShuffleToFMAddSub(SDNode * N,const SDLoc & DL,const X86Subtarget & Subtarget,SelectionDAG & DAG) combineShuffleToFMAddSub() argument
41584 combineShuffleToAddSubOrFMAddSub(SDNode * N,const SDLoc & DL,const X86Subtarget & Subtarget,SelectionDAG & DAG) combineShuffleToAddSubOrFMAddSub() argument
41624 combineShuffleOfConcatUndef(SDNode * N,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineShuffleOfConcatUndef() argument
41668 narrowShuffle(ShuffleVectorSDNode * Shuf,SelectionDAG & DAG) narrowShuffle() argument
41698 combineShuffle(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineShuffle() argument
43111 SimplifyMultipleUseDemandedBitsForTargetNode(SDValue Op,const APInt & DemandedBits,const APInt & DemandedElts,SelectionDAG & DAG,unsigned Depth) const SimplifyMultipleUseDemandedBitsForTargetNode() argument
43230 isGuaranteedNotToBeUndefOrPoisonForTargetNode(SDValue Op,const APInt & DemandedElts,const SelectionDAG & DAG,bool PoisonOnly,unsigned Depth) const isGuaranteedNotToBeUndefOrPoisonForTargetNode() argument
43266 canCreateUndefOrPoisonForTargetNode(SDValue Op,const APInt & DemandedElts,const SelectionDAG & DAG,bool PoisonOnly,bool ConsiderFlags,unsigned Depth) const canCreateUndefOrPoisonForTargetNode() argument
43288 isSplatValueForTargetNode(SDValue Op,const APInt & DemandedElts,APInt & UndefElts,const SelectionDAG & DAG,unsigned Depth) const isSplatValueForTargetNode() argument
43348 adjustBitcastSrcVectorSSE1(SelectionDAG & DAG,SDValue Src,const SDLoc & DL) adjustBitcastSrcVectorSSE1() argument
43382 signExtendBitcastSrcVector(SelectionDAG & DAG,EVT SExtVT,SDValue Src,const SDLoc & DL) signExtendBitcastSrcVector() argument
43413 combineBitcastvxi1(SelectionDAG & DAG,EVT VT,SDValue Src,const SDLoc & DL,const X86Subtarget & Subtarget) combineBitcastvxi1() argument
43562 combinevXi1ConstantToInteger(SDValue Op,SelectionDAG & DAG) combinevXi1ConstantToInteger() argument
43579 combineCastedMaskArithmetic(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineCastedMaskArithmetic() argument
43635 createMMXBuildVector(BuildVectorSDNode * BV,SelectionDAG & DAG,const X86Subtarget & Subtarget) createMMXBuildVector() argument
43716 combineBitcastToBoolVector(EVT VT,SDValue V,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget,unsigned Depth=0) combineBitcastToBoolVector() argument
43804 combineBitcast(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineBitcast() argument
44095 detectExtMul(SelectionDAG & DAG,const SDValue & Mul,SDValue & Op0,SDValue & Op1) detectExtMul() argument
44146 createVPDPBUSD(SelectionDAG & DAG,SDValue LHS,SDValue RHS,unsigned & LogBias,const SDLoc & DL,const X86Subtarget & Subtarget) createVPDPBUSD() argument
44192 createPSADBW(SelectionDAG & DAG,const SDValue & Zext0,const SDValue & Zext1,const SDLoc & DL,const X86Subtarget & Subtarget) createPSADBW() argument
44222 combineMinMaxReduction(SDNode * Extract,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineMinMaxReduction() argument
44296 combinePredicateReduction(SDNode * Extract,SelectionDAG & DAG,const X86Subtarget & Subtarget) combinePredicateReduction() argument
44435 combineVPDPBUSDPattern(SDNode * Extract,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineVPDPBUSDPattern() argument
44506 combineBasicSADPattern(SDNode * Extract,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineBasicSADPattern() argument
44590 combineExtractFromVectorLoad(SDNode * N,EVT VecVT,SDValue SrcVec,uint64_t Idx,const SDLoc & dl,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI) combineExtractFromVectorLoad() argument
44626 combineExtractWithShuffle(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineExtractWithShuffle() argument
44830 scalarizeExtEltFP(SDNode * ExtElt,SelectionDAG & DAG,const X86Subtarget & Subtarget) scalarizeExtEltFP() argument
44931 combineArithReduction(SDNode * ExtElt,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineArithReduction() argument
45063 __anon0268aba89802(SelectionDAG &DAG, const SDLoc &DL, ArrayRef<SDValue> Ops) combineArithReduction() argument
45124 combineExtractVectorElt(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineExtractVectorElt() argument
45302 combineToExtendBoolVectorInReg(unsigned Opcode,const SDLoc & DL,EVT VT,SDValue N0,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineToExtendBoolVectorInReg() argument
45401 combineVSelectWithAllOnesOrZeros(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineVSelectWithAllOnesOrZeros() argument
45507 narrowVectorSelect(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) narrowVectorSelect() argument
45535 combineSelectOfTwoConstants(SDNode * N,SelectionDAG & DAG) combineSelectOfTwoConstants() argument
45612 combineVSelectToBLENDV(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineVSelectToBLENDV() argument
45721 combineLogicBlendIntoConditionalNegate(EVT VT,SDValue Mask,SDValue X,SDValue Y,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineLogicBlendIntoConditionalNegate() argument
45765 commuteSelect(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) commuteSelect() argument
45797 combineSelect(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineSelect() argument
46320 combineSetCCAtomicArith(SDValue Cmp,X86::CondCode & CC,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineSetCCAtomicArith() argument
46439 checkSignTestSetCCCombine(SDValue Cmp,X86::CondCode & CC,SelectionDAG & DAG) checkSignTestSetCCCombine() argument
46666 combineCarryThroughADD(SDValue EFLAGS,SelectionDAG & DAG) combineCarryThroughADD() argument
46726 combinePTESTCC(SDValue EFLAGS,X86::CondCode & CC,SelectionDAG & DAG,const X86Subtarget & Subtarget) combinePTESTCC() argument
46890 combineSetCCMOVMSK(SDValue EFLAGS,X86::CondCode & CC,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineSetCCMOVMSK() argument
47125 combineSetCCEFLAGS(SDValue EFLAGS,X86::CondCode & CC,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineSetCCEFLAGS() argument
47147 combineCMov(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineCMov() argument
47399 canReduceVMulWidth(SDNode * N,SelectionDAG & DAG,ShrinkMode & Mode) canReduceVMulWidth() argument
47461 reduceVMULWidth(SDNode * N,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) reduceVMULWidth() argument
47530 combineMulSpecial(uint64_t MulAmt,SDNode * N,SelectionDAG & DAG,EVT VT,const SDLoc & DL) combineMulSpecial() argument
47620 combineMulToPMADDWD(SDNode * N,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineMulToPMADDWD() argument
47730 combineMulToPMULDQ(SDNode * N,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineMulToPMULDQ() argument
47761 __anon0268aba8a302(SelectionDAG &DAG, const SDLoc &DL, ArrayRef<SDValue> Ops) combineMulToPMULDQ() argument
47772 combineMul(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineMul() argument
47959 combineShiftToPMULH(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineShiftToPMULH() argument
48008 combineShiftLeft(SDNode * N,SelectionDAG & DAG) combineShiftLeft() argument
48053 combineShiftRightArithmetic(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineShiftRightArithmetic() argument
48122 combineShiftRightLogical(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineShiftRightLogical() argument
48175 combineHorizOpWithShuffle(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineHorizOpWithShuffle() argument
48319 combineVectorPack(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineVectorPack() argument
48470 combineVectorHADDSUB(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineVectorHADDSUB() argument
48518 combineVectorShiftVar(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineVectorShiftVar() argument
48551 combineVectorShiftImm(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineVectorShiftImm() argument
48704 combineVectorInsert(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineVectorInsert() argument
48743 combineCompareEqual(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineCompareEqual() argument
48850 combineAndNotIntoANDNP(SDNode * N,SelectionDAG & DAG) combineAndNotIntoANDNP() argument
48881 combineAndShuffleNot(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineAndShuffleNot() argument
48968 PromoteMaskArithmetic(SDValue N,const SDLoc & DL,EVT VT,SelectionDAG & DAG,unsigned Depth) PromoteMaskArithmetic() argument
49022 PromoteMaskArithmetic(SDValue N,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) PromoteMaskArithmetic() argument
49065 convertIntLogicToFPLogic(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) convertIntLogicToFPLogic() argument
49129 combineBitOpWithMOVMSK(SDNode * N,SelectionDAG & DAG) combineBitOpWithMOVMSK() argument
49164 combineBitOpWithShift(SDNode * N,SelectionDAG & DAG) combineBitOpWithShift() argument
49207 combineBitOpWithPACK(SDNode * N,SelectionDAG & DAG) combineBitOpWithPACK() argument
49250 combineAndMaskToShift(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineAndMaskToShift() argument
49345 combineAndLoadToBZHI(SDNode * Node,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineAndLoadToBZHI() argument
49427 combineScalarAndWithMaskSetcc(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineScalarAndWithMaskSetcc() argument
49507 getBMIMatchingOp(unsigned Opc,SelectionDAG & DAG,SDValue OpMustEq,SDValue Op,unsigned Depth) getBMIMatchingOp() argument
49552 combineBMILogicOp(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineBMILogicOp() argument
49572 combineX86SubCmpForFlags(SDNode * N,SDValue Flag,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & ST) combineX86SubCmpForFlags() argument
49633 combineAndOrForCcmpCtest(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & ST) combineAndOrForCcmpCtest() argument
49713 combineAnd(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineAnd() argument
49979 canonicalizeBitSelect(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) canonicalizeBitSelect() argument
50083 combineLogicBlendIntoPBLENDV(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineLogicBlendIntoPBLENDV() argument
50138 lowerX86CmpEqZeroToCtlzSrl(SDValue Op,SelectionDAG & DAG) lowerX86CmpEqZeroToCtlzSrl() argument
50159 combineOrCmpEqZeroToCtlzSrl(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineOrCmpEqZeroToCtlzSrl() argument
50236 foldMaskedMergeImpl(SDValue And0_L,SDValue And0_R,SDValue And1_L,SDValue And1_R,const SDLoc & DL,SelectionDAG & DAG) foldMaskedMergeImpl() argument
50260 foldMaskedMerge(SDNode * Node,SelectionDAG & DAG) foldMaskedMerge() argument
50293 combineAddOrSubToADCOrSBB(bool IsSub,const SDLoc & DL,EVT VT,SDValue X,SDValue Y,SelectionDAG & DAG,bool ZeroSecondOpOnly=false) combineAddOrSubToADCOrSBB() argument
50476 combineAddOrSubToADCOrSBB(SDNode * N,const SDLoc & DL,SelectionDAG & DAG) combineAddOrSubToADCOrSBB() argument
50496 combineOrXorWithSETCC(SDNode * N,SDValue N0,SDValue N1,SelectionDAG & DAG) combineOrXorWithSETCC() argument
50544 combineOr(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineOr() argument
50707 foldXorTruncShiftIntoCmp(SDNode * N,SelectionDAG & DAG) foldXorTruncShiftIntoCmp() argument
50762 foldVectorXorShiftIntoCmp(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) foldVectorXorShiftIntoCmp() argument
50818 detectUSatPattern(SDValue In,EVT VT,SelectionDAG & DAG,const SDLoc & DL) detectUSatPattern() argument
50900 combineTruncateWithSat(SDValue In,EVT VT,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineTruncateWithSat() argument
51000 combineConstantPoolLoads(SDNode * N,const SDLoc & dl,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineConstantPoolLoads() argument
51074 combineLoad(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineLoad() argument
51218 getParamsForOneTrueMaskedElt(MaskedLoadStoreSDNode * MaskedOp,SelectionDAG & DAG,SDValue & Addr,SDValue & Index,Align & Alignment,unsigned & Offset) getParamsForOneTrueMaskedElt() argument
51247 reduceMaskedLoadToScalarLoad(MaskedLoadSDNode * ML,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) reduceMaskedLoadToScalarLoad() argument
51288 combineMaskedLoadConstantMask(MaskedLoadSDNode * ML,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI) combineMaskedLoadConstantMask() argument
51336 combineMaskedLoad(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineMaskedLoad() argument
51384 reduceMaskedStoreToScalarStore(MaskedStoreSDNode * MS,SelectionDAG & DAG,const X86Subtarget & Subtarget) reduceMaskedStoreToScalarStore() argument
51415 combineMaskedStore(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineMaskedStore() argument
51463 combineStore(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineStore() argument
51735 combineVEXTRACT_STORE(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineVEXTRACT_STORE() argument
51772 isHorizontalBinOp(unsigned HOpcode,SDValue & LHS,SDValue & RHS,SelectionDAG & DAG,const X86Subtarget & Subtarget,bool IsCommutative,SmallVectorImpl<int> & PostShuffleMask,bool ForceHorizOp) isHorizontalBinOp() argument
51959 combineToHorizontalAddSub(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineToHorizontalAddSub() argument
52001 __anon0268aba8bc02(SelectionDAG &DAG, const SDLoc &DL, ArrayRef<SDValue> Ops) combineToHorizontalAddSub() argument
52031 combineFMulcFCMulc(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineFMulcFCMulc() argument
52072 combineFaddCFmul(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineFaddCFmul() argument
52147 combineFaddFsub(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineFaddFsub() argument
52158 combineLRINT_LLRINT(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineLRINT_LLRINT() argument
52179 combineTruncatedArithmetic(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget,const SDLoc & DL) combineTruncatedArithmetic() argument
52261 combinePMULH(SDValue Src,EVT VT,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) combinePMULH() argument
52344 detectPMADDUBSW(SDValue In,EVT VT,SelectionDAG & DAG,const X86Subtarget & Subtarget,const SDLoc & DL) detectPMADDUBSW() argument
52486 combineTruncate(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineTruncate() argument
52524 combineVTRUNC(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI) combineVTRUNC() argument
52552 isFNEG(SelectionDAG & DAG,SDNode * N,unsigned Depth=0) isFNEG() argument
52698 combineFneg(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineFneg() argument
52735 getNegatedExpression(SDValue Op,SelectionDAG & DAG,bool LegalOperations,bool ForCodeSize,NegatibleCost & Cost,unsigned Depth) const getNegatedExpression() argument
52802 lowerX86FPLogicOp(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) lowerX86FPLogicOp() argument
52833 foldXor1SetCC(SDNode * N,SelectionDAG & DAG) foldXor1SetCC() argument
52847 combineXorSubCTLZ(SDNode * N,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineXorSubCTLZ() argument
52903 combineXor(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineXor() argument
52993 combineBITREVERSE(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineBITREVERSE() argument
53021 combineAVG(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineAVG() argument
53045 combineBEXTR(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineBEXTR() argument
53072 getNullFPConstForNullVal(SDValue V,SelectionDAG & DAG,const X86Subtarget & Subtarget) getNullFPConstForNullVal() argument
53083 combineFAndFNotToFAndn(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineFAndFNotToFAndn() argument
53115 combineFAnd(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineFAnd() argument
53132 combineFAndn(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineFAndn() argument
53146 combineFOr(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineFOr() argument
53166 combineFMinFMax(SDNode * N,SelectionDAG & DAG) combineFMinFMax() argument
53187 combineFMinNumFMaxNum(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineFMinNumFMaxNum() argument
53253 combineX86INT_TO_FP(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI) combineX86INT_TO_FP() argument
53286 combineCVTP2I_CVTTP2I(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI) combineCVTP2I_CVTTP2I() argument
53323 combineAndnp(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineAndnp() argument
53441 combineBT(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI) combineBT() argument
53457 combineCVTPH2PS(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI) combineCVTPH2PS() argument
53498 combineSextInRegCmov(SDNode * N,SelectionDAG & DAG) combineSextInRegCmov() argument
53559 combineSignExtendInReg(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineSignExtendInReg() argument
53606 promoteExtBeforeAdd(SDNode * Ext,SelectionDAG & DAG,const X86Subtarget & Subtarget) promoteExtBeforeAdd() argument
53681 combineToExtendCMOV(SDNode * Extend,SelectionDAG & DAG) combineToExtendCMOV() argument
53728 combineExtSetcc(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineExtSetcc() argument
53772 combineSext(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineSext() argument
53829 getInvertedVectorForFMA(SDValue V,SelectionDAG & DAG) getInvertedVectorForFMA() argument
53876 combineFMA(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineFMA() argument
53964 combineFMADDSUB(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI) combineFMADDSUB() argument
53987 combineZext(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineZext() argument
54054 truncateAVX512SetCCNoBWI(EVT VT,EVT OpVT,SDValue LHS,SDValue RHS,ISD::CondCode CC,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) truncateAVX512SetCCNoBWI() argument
54066 combineSetCC(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineSetCC() argument
54355 combineMOVMSK(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineMOVMSK() argument
54472 combineTESTP(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineTESTP() argument
54487 combineX86GatherScatter(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI) combineX86GatherScatter() argument
54508 rebuildGatherScatter(MaskedGatherScatterSDNode * GorS,SDValue Index,SDValue Base,SDValue Scale,SelectionDAG & DAG) rebuildGatherScatter() argument
54530 combineGatherScatter(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI) combineGatherScatter() argument
54640 combineX86SetCC(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineX86SetCC() argument
54654 combineBrCond(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineBrCond() argument
54674 combineVectorCompareAndMaskUnaryOp(SDNode * N,SelectionDAG & DAG) combineVectorCompareAndMaskUnaryOp() argument
54731 combineToFPTruncExtElt(SDNode * N,SelectionDAG & DAG) combineToFPTruncExtElt() argument
54763 combineUIntToFP(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineUIntToFP() argument
54827 combineSIntToFP(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineSIntToFP() argument
55010 combineCMP(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineCMP() argument
55157 combineX86AddSub(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & ST) combineX86AddSub() argument
55200 combineSBB(SDNode * N,SelectionDAG & DAG) combineSBB() argument
55222 combineADC(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI) combineADC() argument
55280 matchPMADDWD(SelectionDAG & DAG,SDValue Op0,SDValue Op1,const SDLoc & DL,EVT VT,const X86Subtarget & Subtarget) matchPMADDWD() argument
55388 matchPMADDWD_2(SelectionDAG & DAG,SDValue N0,SDValue N1,const SDLoc & DL,EVT VT,const X86Subtarget & Subtarget) matchPMADDWD_2() argument
55498 __anon0268aba8d002(SelectionDAG &DAG, const SDLoc &DL, ArrayRef<SDValue> Ops) matchPMADDWD_2() argument
55528 combineAddOfPMADDWD(SelectionDAG & DAG,SDValue N0,SDValue N1,const SDLoc & DL,EVT VT) combineAddOfPMADDWD() argument
55573 pushAddIntoCmovOfConsts(SDNode * N,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) pushAddIntoCmovOfConsts() argument
55637 combineAdd(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineAdd() argument
55710 combineSubABS(SDNode * N,SelectionDAG & DAG) combineSubABS() argument
55747 combineSubSetcc(SDNode * N,SelectionDAG & DAG) combineSubSetcc() argument
55774 combineX86CloadCstore(SDNode * N,SelectionDAG & DAG) combineX86CloadCstore() argument
55800 combineSub(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineSub() argument
55868 combineVectorCompare(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineVectorCompare() argument
55938 combineConcatVectorOps(const SDLoc & DL,MVT VT,ArrayRef<SDValue> Ops,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineConcatVectorOps() argument
56592 combineCONCAT_VECTORS(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineCONCAT_VECTORS() argument
56628 combineINSERT_SUBVECTOR(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineINSERT_SUBVECTOR() argument
56789 narrowExtractedVectorSelect(SDNode * Ext,const SDLoc & DL,SelectionDAG & DAG) narrowExtractedVectorSelect() argument
56839 combineEXTRACT_SUBVECTOR(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineEXTRACT_SUBVECTOR() argument
57053 combineScalarToVector(SDNode * N,SelectionDAG & DAG) combineScalarToVector() argument
57136 combinePMULDQ(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combinePMULDQ() argument
57189 combineVPMADD(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI) combineVPMADD() argument
57234 combineEXTEND_VECTOR_INREG(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineEXTEND_VECTOR_INREG() argument
57302 combineKSHIFT(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI) combineKSHIFT() argument
57320 combineFP16_TO_FP(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineFP16_TO_FP() argument
57342 combineFP_EXTEND(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineFP_EXTEND() argument
57439 combineBROADCAST_LOAD(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI) combineBROADCAST_LOAD() argument
57475 combineFP_ROUND(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineFP_ROUND() argument
57566 combineMOVDQ2Q(SDNode * N,SelectionDAG & DAG) combineMOVDQ2Q() argument
57587 combinePDEP(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI) combinePDEP() argument
57599 SelectionDAG &DAG = DCI.DAG; PerformDAGCombine() local
[all...]
/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SelectionDAGInfo.cpp86 DAG.getMachineFunction().getSubtarget<AArch64Subtarget>(); in EmitStreamingCompatibleMemLibCall() argument
25 EmitMOPS(AArch64ISD::NodeType SDOpcode,SelectionDAG & DAG,const SDLoc & DL,SDValue Chain,SDValue Dst,SDValue SrcOrValue,SDValue Size,Align Alignment,bool isVolatile,MachinePointerInfo DstPtrInfo,MachinePointerInfo SrcPtrInfo) const EmitMOPS() argument
144 EmitTargetCodeForMemcpy(SelectionDAG & DAG,const SDLoc & DL,SDValue Chain,SDValue Dst,SDValue Src,SDValue Size,Align Alignment,bool isVolatile,bool AlwaysInline,MachinePointerInfo DstPtrInfo,MachinePointerInfo SrcPtrInfo) const EmitTargetCodeForMemcpy() argument
162 EmitTargetCodeForMemset(SelectionDAG & DAG,const SDLoc & dl,SDValue Chain,SDValue Dst,SDValue Src,SDValue Size,Align Alignment,bool isVolatile,bool AlwaysInline,MachinePointerInfo DstPtrInfo) const EmitTargetCodeForMemset() argument
180 EmitTargetCodeForMemmove(SelectionDAG & DAG,const SDLoc & dl,SDValue Chain,SDValue Dst,SDValue Src,SDValue Size,Align Alignment,bool isVolatile,MachinePointerInfo DstPtrInfo,MachinePointerInfo SrcPtrInfo) const EmitTargetCodeForMemmove() argument
199 EmitUnrolledSetTag(SelectionDAG & DAG,const SDLoc & dl,SDValue Chain,SDValue Ptr,uint64_t ObjSize,const MachineMemOperand * BaseMemOperand,bool ZeroData) EmitUnrolledSetTag() argument
252 EmitTargetCodeForSetTag(SelectionDAG & DAG,const SDLoc & dl,SDValue Chain,SDValue Addr,SDValue Size,MachinePointerInfo DstPtrInfo,bool ZeroData) const EmitTargetCodeForSetTag() argument
[all...]
H A DAArch64ISelLowering.cpp233 static inline bool isPackedVectorType(EVT VT, SelectionDAG &DAG) { in isPackedVectorType() argument
342 extractPtrauthBlendDiscriminators(SDValue Disc,SelectionDAG * DAG) extractPtrauthBlendDiscriminators() argument
2291 computeKnownBitsForTargetNode(const SDValue Op,KnownBits & Known,const APInt & DemandedElts,const SelectionDAG & DAG,unsigned Depth) const computeKnownBitsForTargetNode() argument
2417 ComputeNumSignBitsForTargetNode(SDValue Op,const APInt & DemandedElts,const SelectionDAG & DAG,unsigned Depth) const ComputeNumSignBitsForTargetNode() argument
3410 emitStrictFPComparison(SDValue LHS,SDValue RHS,const SDLoc & dl,SelectionDAG & DAG,SDValue Chain,bool IsSignaling) emitStrictFPComparison() argument
3431 emitComparison(SDValue LHS,SDValue RHS,ISD::CondCode CC,const SDLoc & dl,SelectionDAG & DAG) emitComparison() argument
3539 emitConditionalComparison(SDValue LHS,SDValue RHS,ISD::CondCode CC,SDValue CCOp,AArch64CC::CondCode Predicate,AArch64CC::CondCode OutCC,const SDLoc & DL,SelectionDAG & DAG) emitConditionalComparison() argument
3651 emitConjunctionRec(SelectionDAG & DAG,SDValue Val,AArch64CC::CondCode & OutCC,bool Negate,SDValue CCOp,AArch64CC::CondCode Predicate) emitConjunctionRec() argument
3763 emitConjunction(SelectionDAG & DAG,SDValue Val,AArch64CC::CondCode & OutCC) emitConjunction() argument
3812 getAArch64Cmp(SDValue LHS,SDValue RHS,ISD::CondCode CC,SDValue & AArch64cc,SelectionDAG & DAG,const SDLoc & dl) getAArch64Cmp() argument
3942 getAArch64XALUOOp(AArch64CC::CondCode & CC,SDValue Op,SelectionDAG & DAG) getAArch64XALUOOp() argument
4118 valueToCarryFlag(SDValue Value,SelectionDAG & DAG,bool Invert) valueToCarryFlag() argument
4130 carryFlagToValue(SDValue Glue,EVT VT,SelectionDAG & DAG,bool Invert) carryFlagToValue() argument
4142 overflowFlagToValue(SDValue Glue,EVT VT,SelectionDAG & DAG) overflowFlagToValue() argument
4153 lowerADDSUBO_CARRY(SDValue Op,SelectionDAG & DAG,unsigned Opcode,bool IsSigned) lowerADDSUBO_CARRY() argument
4179 LowerXALUO(SDValue Op,SelectionDAG & DAG) LowerXALUO() argument
4210 LowerPREFETCH(SDValue Op,SelectionDAG & DAG) LowerPREFETCH() argument
4933 addRequiredExtensionForVectorMULL(SDValue N,SelectionDAG & DAG,const EVT & OrigTy,const EVT & ExtTy,unsigned ExtOpcode) addRequiredExtensionForVectorMULL() argument
4966 isExtendedBUILD_VECTOR(SDValue N,SelectionDAG & DAG,bool isSigned) isExtendedBUILD_VECTOR() argument
4992 skipExtensionForVectorMULL(SDValue N,SelectionDAG & DAG) skipExtensionForVectorMULL() argument
5022 isSignExtended(SDValue N,SelectionDAG & DAG) isSignExtended() argument
5028 isZeroExtended(SDValue N,SelectionDAG & DAG) isZeroExtended() argument
5034 isAddSubSExt(SDValue N,SelectionDAG & DAG) isAddSubSExt() argument
5045 isAddSubZExt(SDValue N,SelectionDAG & DAG) isAddSubZExt() argument
5182 selectUmullSmull(SDValue & N0,SDValue & N1,SelectionDAG & DAG,SDLoc DL,bool & IsMLA) selectUmullSmull() argument
5324 getPTrue(SelectionDAG & DAG,SDLoc DL,EVT VT,int Pattern) getPTrue() argument
5332 optimizeIncrementingWhile(SDValue Op,SelectionDAG & DAG,bool IsSigned,bool IsEqual) optimizeIncrementingWhile() argument
5370 getSVEPredicateBitCast(EVT VT,SDValue Op,SelectionDAG & DAG) getSVEPredicateBitCast() argument
5407 getRuntimePStateSM(SelectionDAG & DAG,SDValue Chain,SDLoc DL,EVT VT) const getRuntimePStateSM() argument
5462 LowerSMELdrStr(SDValue N,SelectionDAG & DAG,bool IsLoad) LowerSMELdrStr() argument
5626 __anonb71a9e6e0402(SDValue N, std::optional<uint64_t> NLane, std::optional<uint64_t> OtherLane, const SDLoc &dl, SelectionDAG &DAG) LowerINTRINSIC_WO_CHAIN() argument
6361 LowerTruncateVectorStore(SDLoc DL,StoreSDNode * ST,EVT VT,EVT MemVT,SelectionDAG & DAG) LowerTruncateVectorStore() argument
6578 LowerBRCOND(SDValue Op,SelectionDAG & DAG) LowerBRCOND() argument
6596 LowerFunnelShift(SDValue Op,SelectionDAG & DAG) LowerFunnelShift() argument
6618 LowerFLDEXP(SDValue Op,SelectionDAG & DAG) LowerFLDEXP() argument
7070 isReassocProfitable(SelectionDAG & DAG,SDValue N0,SDValue N1) const isReassocProfitable() argument
7164 LowerFormalArguments(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & DL,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const LowerFormalArguments() argument
7613 saveVarArgRegisters(CCState & CCInfo,SelectionDAG & DAG,const SDLoc & DL,SDValue & Chain) const saveVarArgRegisters() argument
7711 LowerCallResult(SDValue Chain,SDValue InGlue,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<CCValAssign> & RVLocs,const SDLoc & DL,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals,bool isThisReturn,SDValue ThisVal,bool RequiresSMChange) const LowerCallResult() argument
7795 const SelectionDAG &DAG = CLI.DAG; analyzeCallOperands() local
7853 const SelectionDAG &DAG = CLI.DAG; isEligibleForTailCallOptimization() local
7999 addTokenForArgument(SDValue Chain,SelectionDAG & DAG,MachineFrameInfo & MFI,int ClobberedFI) const addTokenForArgument() argument
8036 checkZExtBool(SDValue Arg,const SelectionDAG & DAG) checkZExtBool() argument
8089 changeStreamingMode(SelectionDAG & DAG,SDLoc DL,bool Enable,SDValue Chain,SDValue InGlue,unsigned Condition,SDValue PStateSM) const changeStreamingMode() argument
8135 SelectionDAG &DAG = CLI.DAG; LowerCall() local
9047 getTargetNode(GlobalAddressSDNode * N,EVT Ty,SelectionDAG & DAG,unsigned Flag) const getTargetNode() argument
9054 getTargetNode(JumpTableSDNode * N,EVT Ty,SelectionDAG & DAG,unsigned Flag) const getTargetNode() argument
9060 getTargetNode(ConstantPoolSDNode * N,EVT Ty,SelectionDAG & DAG,unsigned Flag) const getTargetNode() argument
9067 getTargetNode(BlockAddressSDNode * N,EVT Ty,SelectionDAG & DAG,unsigned Flag) const getTargetNode() argument
9073 getTargetNode(ExternalSymbolSDNode * N,EVT Ty,SelectionDAG & DAG,unsigned Flag) const getTargetNode() argument
9080 getGOT(NodeTy * N,SelectionDAG & DAG,unsigned Flags) const getGOT() argument
9093 getAddrLarge(NodeTy * N,SelectionDAG & DAG,unsigned Flags) const getAddrLarge() argument
9109 getAddr(NodeTy * N,SelectionDAG & DAG,unsigned Flags) const getAddr() argument
9123 getAddrTiny(NodeTy * N,SelectionDAG & DAG,unsigned Flags) const getAddrTiny() argument
9841 __anonb71a9e6e0e02(EVT VT, SDValue Op, SelectionDAG &DAG) LowerFCOPYSIGN() argument
10145 performOrXorChainCombine(SDNode * N,SelectionDAG & DAG) performOrXorChainCombine() argument
11112 getEstimate(const AArch64Subtarget * ST,unsigned Opcode,SDValue Operand,SelectionDAG & DAG,int & ExtraSteps) getEstimate() argument
11142 getSqrtInputTest(SDValue Op,SelectionDAG & DAG,const DenormalMode & Mode) const getSqrtInputTest() argument
11158 getSqrtEstimate(SDValue Operand,SelectionDAG & DAG,int Enabled,int & ExtraSteps,bool & UseOneConst,bool Reciprocal) const getSqrtEstimate() argument
11191 getRecipEstimate(SDValue Operand,SelectionDAG & DAG,int Enabled,int & ExtraSteps) const getRecipEstimate() argument
11350 getSETCC(AArch64CC::CondCode CC,SDValue NZCV,const SDLoc & DL,SelectionDAG & DAG) getSETCC() argument
11728 WidenVector(SDValue V64Reg,SelectionDAG & DAG) WidenVector() argument
11749 ReconstructShuffleWithRuntimeMask(SDValue Op,SelectionDAG & DAG) ReconstructShuffleWithRuntimeMask() argument
12171 ReconstructTruncateFromBuildVector(SDValue V,SelectionDAG & DAG) ReconstructTruncateFromBuildVector() argument
12447 tryFormConcatFromShuffle(SDValue Op,SelectionDAG & DAG) tryFormConcatFromShuffle() argument
12482 GeneratePerfectShuffle(unsigned ID,SDValue V1,SDValue V2,unsigned PFEntry,SDValue LHS,SDValue RHS,SelectionDAG & DAG,const SDLoc & dl) GeneratePerfectShuffle() argument
12642 GenerateTBL(SDValue Op,ArrayRef<int> ShuffleMask,SelectionDAG & DAG) GenerateTBL() argument
12729 constructDup(SDValue V,int Lane,SDLoc dl,EVT VT,unsigned Opcode,SelectionDAG & DAG) constructDup() argument
12835 tryWidenMaskForShuffle(SDValue Op,SelectionDAG & DAG) tryWidenMaskForShuffle() argument
12870 tryToConvertShuffleOfTbl2ToTbl4(SDValue Op,ArrayRef<int> ShuffleMask,SelectionDAG & DAG) tryToConvertShuffleOfTbl2ToTbl4() argument
13209 tryAdvSIMDModImm64(unsigned NewOp,SDValue Op,SelectionDAG & DAG,const APInt & Bits) tryAdvSIMDModImm64() argument
13230 tryAdvSIMDModImm32(unsigned NewOp,SDValue Op,SelectionDAG & DAG,const APInt & Bits,const SDValue * LHS=nullptr) tryAdvSIMDModImm32() argument
13283 tryAdvSIMDModImm16(unsigned NewOp,SDValue Op,SelectionDAG & DAG,const APInt & Bits,const SDValue * LHS=nullptr) tryAdvSIMDModImm16() argument
13329 tryAdvSIMDModImm321s(unsigned NewOp,SDValue Op,SelectionDAG & DAG,const APInt & Bits) tryAdvSIMDModImm321s() argument
13359 tryAdvSIMDModImm8(unsigned NewOp,SDValue Op,SelectionDAG & DAG,const APInt & Bits) tryAdvSIMDModImm8() argument
13380 tryAdvSIMDModImmFP(unsigned NewOp,SDValue Op,SelectionDAG & DAG,const APInt & Bits) tryAdvSIMDModImmFP() argument
13438 isAllActivePredicate(SelectionDAG & DAG,SDValue N) isAllActivePredicate() argument
13483 tryLowerToSLI(SDNode * N,SelectionDAG & DAG) tryLowerToSLI() argument
13634 NormalizeBuildVector(SDValue Op,SelectionDAG & DAG) NormalizeBuildVector() argument
13664 ConstantBuildVector(SDValue Op,SelectionDAG & DAG,const AArch64Subtarget * ST) ConstantBuildVector() argument
14644 canLowerSRLToRoundingShiftForVT(SDValue Shift,EVT ResVT,SelectionDAG & DAG,unsigned & ShiftValue,SDValue & RShOperand) canLowerSRLToRoundingShiftForVT() argument
14756 EmitVectorComparison(SDValue LHS,SDValue RHS,AArch64CC::CondCode CC,bool NoNans,EVT VT,const SDLoc & dl,SelectionDAG & DAG) EmitVectorComparison() argument
14957 getReductionSDNode(unsigned Op,SDLoc DL,SDValue ScalarOp,SelectionDAG & DAG) getReductionSDNode() argument
14965 getVectorBitwiseReduce(unsigned Opcode,SDValue Vec,EVT VT,SDLoc DL,SelectionDAG & DAG) getVectorBitwiseReduce() argument
15264 LowerAVG(SDValue Op,SelectionDAG & DAG,unsigned NewOp) const LowerAVG() argument
17400 foldVectorXorShiftIntoCmp(SDNode * N,SelectionDAG & DAG,const AArch64Subtarget * Subtarget) foldVectorXorShiftIntoCmp() argument
17439 performVecReduceAddCombineWithUADDLP(SDNode * N,SelectionDAG & DAG) performVecReduceAddCombineWithUADDLP() argument
17519 performVecReduceAddCombine(SDNode * N,SelectionDAG & DAG,const AArch64Subtarget * ST) performVecReduceAddCombine() argument
17622 performUADDVAddCombine(SDValue A,SelectionDAG & DAG) performUADDVAddCombine() argument
17671 performUADDVZextCombine(SDValue A,SelectionDAG & DAG) performUADDVZextCombine() argument
17709 performUADDVCombine(SDNode * N,SelectionDAG & DAG) performUADDVCombine() argument
17720 performXorCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const AArch64Subtarget * Subtarget) performXorCombine() argument
17731 BuildSDIVPow2(SDNode * N,const APInt & Divisor,SelectionDAG & DAG,SmallVectorImpl<SDNode * > & Created) const BuildSDIVPow2() argument
17754 BuildSREMPow2(SDNode * N,const APInt & Divisor,SelectionDAG & DAG,SmallVectorImpl<SDNode * > & Created) const BuildSREMPow2() argument
17871 performBuildShuffleExtendCombine(SDValue BV,SelectionDAG & DAG) performBuildShuffleExtendCombine() argument
17935 performMulVectorExtendCombine(SDNode * Mul,SelectionDAG & DAG) performMulVectorExtendCombine() argument
17955 performMulVectorCmpZeroCombine(SDNode * N,SelectionDAG & DAG) performMulVectorCmpZeroCombine() argument
17992 performVectorExtCombine(SDNode * N,SelectionDAG & DAG) performVectorExtCombine() argument
18029 performMulCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const AArch64Subtarget * Subtarget) performMulCombine() argument
18280 performVectorCompareAndMaskUnaryOpCombine(SDNode * N,SelectionDAG & DAG) performVectorCompareAndMaskUnaryOpCombine() argument
18325 performIntToFpCombine(SDNode * N,SelectionDAG & DAG,const AArch64Subtarget * Subtarget) performIntToFpCombine() argument
18367 performFpToIntCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const AArch64Subtarget * Subtarget) performFpToIntCombine() argument
18439 SelectionDAG &DAG = DCI.DAG; tryCombineToBSL() local
18546 performANDORCSELCombine(SDNode * N,SelectionDAG & DAG) performANDORCSELCombine() argument
18617 SelectionDAG &DAG = DCI.DAG; performORCombine() local
18672 SelectionDAG &DAG = DCI.DAG; performSVEAndCombine() local
18791 SelectionDAG &DAG = DCI.DAG; performANDSETCCCombine() local
18824 SelectionDAG &DAG = DCI.DAG; performANDCombine() local
18887 SelectionDAG &DAG = DCI.DAG; performFADDCombine() local
18978 SelectionDAG &DAG = DCI.DAG; performFirstTrueTestVectorCombine() local
19015 SelectionDAG &DAG = DCI.DAG; performLastTrueTestVectorCombine() local
19029 SelectionDAG &DAG = DCI.DAG; performExtractVectorEltCombine() local
19092 performConcatVectorsCombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,SelectionDAG & DAG) performConcatVectorsCombine() argument
19319 performExtractSubvectorCombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,SelectionDAG & DAG) performExtractSubvectorCombine() argument
19342 performInsertSubvectorCombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,SelectionDAG & DAG) performInsertSubvectorCombine() argument
19384 tryCombineFixedPointConvert(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,SelectionDAG & DAG) tryCombineFixedPointConvert() argument
19445 tryExtendDUPToExtractHigh(SDValue N,SelectionDAG & DAG) tryExtendDUPToExtractHigh() argument
19586 performSetccAddFolding(SDNode * Op,SelectionDAG & DAG) performSetccAddFolding() argument
19633 performAddUADDVCombine(SDNode * N,SelectionDAG & DAG) performAddUADDVCombine() argument
19672 performAddCSelIntoCSinc(SDNode * N,SelectionDAG & DAG) performAddCSelIntoCSinc() argument
19745 performAddDotCombine(SDNode * N,SelectionDAG & DAG) performAddDotCombine() argument
19771 getNegatedInteger(SDValue Op,SelectionDAG & DAG) getNegatedInteger() argument
19785 performNegCSelCombine(SDNode * N,SelectionDAG & DAG) performNegCSelCombine() argument
19823 SelectionDAG &DAG = DCI.DAG; performAddSubLongCombine() local
19888 foldOverflowCheck(SDNode * Op,SelectionDAG & DAG,bool IsAdd) foldOverflowCheck() argument
19912 foldADCToCINC(SDNode * N,SelectionDAG & DAG) foldADCToCINC() argument
19930 performBuildVectorCombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,SelectionDAG & DAG) performBuildVectorCombine() argument
20065 performTruncateCombine(SDNode * N,SelectionDAG & DAG) performTruncateCombine() argument
20107 performAddCombineSubShift(SDNode * N,SDValue SUB,SDValue Z,SelectionDAG & DAG) performAddCombineSubShift() argument
20135 performAddCombineForShiftedOperands(SDNode * N,SelectionDAG & DAG) performAddCombineForShiftedOperands() argument
20175 performSubAddMULCombine(SDNode * N,SelectionDAG & DAG) performSubAddMULCombine() argument
20212 SelectionDAG &DAG = DCI.DAG; performSVEMulAddSubCombine() local
20260 performAddSubIntoVectorOp(SDNode * N,SelectionDAG & DAG) performAddSubIntoVectorOp() argument
20366 areLoadedOffsetButOtherwiseSame(SDValue Op0,SDValue Op1,SelectionDAG & DAG,unsigned & NumSubLoads) areLoadedOffsetButOtherwiseSame() argument
20420 performExtBinopLoadFold(SDNode * N,SelectionDAG & DAG) performExtBinopLoadFold() argument
20464 __anonb71a9e6e3102(SDValue Op0, SDValue Op1, SelectionDAG &DAG) performExtBinopLoadFold() argument
20575 tryCombineLongOpWithDup(unsigned IID,SDNode * N,TargetLowering::DAGCombinerInfo & DCI,SelectionDAG & DAG) tryCombineLongOpWithDup() argument
20606 tryCombineShiftImm(unsigned IID,SDNode * N,SelectionDAG & DAG) tryCombineShiftImm() argument
20700 tryCombineCRC32(unsigned Mask,SDNode * N,SelectionDAG & DAG) tryCombineCRC32() argument
20714 combineAcrossLanesIntrinsic(unsigned Opc,SDNode * N,SelectionDAG & DAG) combineAcrossLanesIntrinsic() argument
20723 LowerSVEIntrinsicIndex(SDNode * N,SelectionDAG & DAG) LowerSVEIntrinsicIndex() argument
20739 LowerSVEIntrinsicDUP(SDNode * N,SelectionDAG & DAG) LowerSVEIntrinsicDUP() argument
20753 LowerSVEIntrinsicEXT(SDNode * N,SelectionDAG & DAG) LowerSVEIntrinsicEXT() argument
20781 tryConvertSVEWideCompare(SDNode * N,ISD::CondCode CC,TargetLowering::DAGCombinerInfo & DCI,SelectionDAG & DAG) tryConvertSVEWideCompare() argument
20843 getPTest(SelectionDAG & DAG,EVT VT,SDValue Pg,SDValue Op,AArch64CC::CondCode Cond) getPTest() argument
20882 combineSVEReductionInt(SDNode * N,unsigned Opc,SelectionDAG & DAG) combineSVEReductionInt() argument
20901 combineSVEReductionFP(SDNode * N,unsigned Opc,SelectionDAG & DAG) combineSVEReductionFP() argument
20918 combineSVEReductionOrderedFP(SDNode * N,unsigned Opc,SelectionDAG & DAG) combineSVEReductionOrderedFP() argument
20944 convertMergedOpToPredOp(SDNode * N,unsigned Opc,SelectionDAG & DAG,bool UnpredOp=false,bool SwapOperands=false) convertMergedOpToPredOp() argument
21004 SelectionDAG &DAG = DCI.DAG; tryCombineWhileLo() local
21027 SelectionDAG &DAG = DCI.DAG; performIntrinsicCombine() local
21335 performSignExtendSetCCCombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,SelectionDAG & DAG) performSignExtendSetCCCombine() argument
21375 performExtendCombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,SelectionDAG & DAG) performExtendCombine() argument
21400 splitStoreSplat(SelectionDAG & DAG,StoreSDNode & St,SDValue SplatVal,unsigned NumVecElts) splitStoreSplat() argument
21470 performLD1Combine(SDNode * N,SelectionDAG & DAG,unsigned Opc) performLD1Combine() argument
21496 performLDNT1Combine(SDNode * N,SelectionDAG & DAG) performLDNT1Combine() argument
21522 performLD1ReplicateCombine(SDNode * N,SelectionDAG & DAG) performLD1ReplicateCombine() argument
21543 performST1Combine(SDNode * N,SelectionDAG & DAG) performST1Combine() argument
21569 performSTNT1Combine(SDNode * N,SelectionDAG & DAG) performSTNT1Combine() argument
21601 replaceZeroVectorStore(SelectionDAG & DAG,StoreSDNode & St) replaceZeroVectorStore() argument
21668 replaceSplatVectorStore(SelectionDAG & DAG,StoreSDNode & St) replaceSplatVectorStore() argument
21722 splitStores(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,SelectionDAG & DAG,const AArch64Subtarget * Subtarget) splitStores() argument
21792 performSpliceCombine(SDNode * N,SelectionDAG & DAG) performSpliceCombine() argument
21802 performUnpackCombine(SDNode * N,SelectionDAG & DAG,const AArch64Subtarget * Subtarget) performUnpackCombine() argument
21865 tryCombineExtendRShTrunc(SDNode * N,SelectionDAG & DAG) tryCombineExtendRShTrunc() argument
21905 trySimplifySrlAddToRshrnb(SDValue Srl,SelectionDAG & DAG,const AArch64Subtarget * Subtarget) trySimplifySrlAddToRshrnb() argument
21932 performUzpCombine(SDNode * N,SelectionDAG & DAG,const AArch64Subtarget * Subtarget) performUzpCombine() argument
22102 performGLD1Combine(SDNode * N,SelectionDAG & DAG) performGLD1Combine() argument
22193 performSunpkloCombine(SDNode * N,SelectionDAG & DAG) performSunpkloCombine() argument
22218 SelectionDAG &DAG = DCI.DAG; performPostLD1Combine() local
22330 performTBISimplification(SDValue Addr,TargetLowering::DAGCombinerInfo & DCI,SelectionDAG & DAG) performTBISimplification() argument
22343 foldTruncStoreOfExt(SelectionDAG & DAG,SDNode * N) foldTruncStoreOfExt() argument
22381 combineV3I8LoadExt(LoadSDNode * LD,SelectionDAG & DAG) combineV3I8LoadExt() argument
22425 performLOADCombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,SelectionDAG & DAG,const AArch64Subtarget * Subtarget) performLOADCombine() argument
22541 vectorToScalarBitmask(SDNode * N,SelectionDAG & DAG) vectorToScalarBitmask() argument
22613 combineBoolVectorAndTruncateStore(SelectionDAG & DAG,StoreSDNode * Store) combineBoolVectorAndTruncateStore() argument
22651 combineI8TruncStore(StoreSDNode * ST,SelectionDAG & DAG,const AArch64Subtarget * Subtarget) combineI8TruncStore() argument
22699 performSTORECombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,SelectionDAG & DAG,const AArch64Subtarget * Subtarget) performSTORECombine() argument
22757 performMSTORECombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,SelectionDAG & DAG,const AArch64Subtarget * Subtarget) performMSTORECombine() argument
22814 foldIndexIntoBase(SDValue & BasePtr,SDValue & Index,SDValue Scale,SDLoc DL,SelectionDAG & DAG) foldIndexIntoBase() argument
22865 findMoreOptimalIndexType(const MaskedGatherScatterSDNode * N,SDValue & BasePtr,SDValue & Index,SelectionDAG & DAG) findMoreOptimalIndexType() argument
22934 performMaskedGatherScatterCombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,SelectionDAG & DAG) performMaskedGatherScatterCombine() argument
22973 performNEONPostLDSTCombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,SelectionDAG & DAG) performNEONPostLDSTCombine() argument
23291 performSubsToAndsCombine(SDNode * N,SDNode * SubsNode,SDNode * AndNode,SelectionDAG & DAG,unsigned CCIndex,unsigned CmpIndex,unsigned CC) performSubsToAndsCombine() argument
23339 performCONDCombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,SelectionDAG & DAG,unsigned CCIndex,unsigned CmpIndex) performCONDCombine() argument
23418 performBRCONDCombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,SelectionDAG & DAG) performBRCONDCombine() argument
23478 foldCSELofCTTZ(SDNode * N,SelectionDAG & DAG) foldCSELofCTTZ() argument
23526 foldCSELOfCSEL(SDNode * Op,SelectionDAG & DAG) foldCSELOfCSEL() argument
23582 performCSELCombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,SelectionDAG & DAG) performCSELCombine() argument
23601 tryToWidenSetCCOperands(SDNode * Op,SelectionDAG & DAG) tryToWidenSetCCOperands() argument
23648 performVecReduceBitwiseCombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,SelectionDAG & DAG) performVecReduceBitwiseCombine() argument
23664 performSETCCCombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,SelectionDAG & DAG) performSETCCCombine() argument
23761 performSetCCPunpkCombine(SDNode * N,SelectionDAG & DAG) performSetCCPunpkCombine() argument
23804 SelectionDAG &DAG = DCI.DAG; performSetccMergeZeroCombine() local
23847 getTestBitOperand(SDValue Op,unsigned & Bit,bool & Invert,SelectionDAG & DAG) getTestBitOperand() argument
23921 performTBZCombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,SelectionDAG & DAG) performTBZCombine() argument
23950 trySwapVSelectOperands(SDNode * N,SelectionDAG & DAG) trySwapVSelectOperands() argument
23988 performVSelectCombine(SDNode * N,SelectionDAG & DAG) performVSelectCombine() argument
24061 SelectionDAG &DAG = DCI.DAG; performSelectCombine() local
24166 performNVCASTCombine(SDNode * N,SelectionDAG & DAG) performNVCASTCombine() argument
24179 performGlobalAddressCombine(SDNode * N,SelectionDAG & DAG,const AArch64Subtarget * Subtarget,const TargetMachine & TM) performGlobalAddressCombine() argument
24230 performCTLZCombine(SDNode * N,SelectionDAG & DAG,const AArch64Subtarget * Subtarget) performCTLZCombine() argument
24243 getScaledOffsetForBitWidth(SelectionDAG & DAG,SDValue Offset,SDLoc DL,unsigned BitWidth) getScaledOffsetForBitWidth() argument
24288 performScatterStoreCombine(SDNode * N,SelectionDAG & DAG,unsigned Opcode,bool OnlyPackedOffsets=true) performScatterStoreCombine() argument
24401 performGatherLoadCombine(SDNode * N,SelectionDAG & DAG,unsigned Opcode,bool OnlyPackedOffsets=true) performGatherLoadCombine() argument
24509 performSignExtendInRegCombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,SelectionDAG & DAG) performSignExtendInRegCombine() argument
24640 legalizeSVEGatherPrefetchOffsVec(SDNode * N,SelectionDAG & DAG) legalizeSVEGatherPrefetchOffsVec() argument
24663 combineSVEPrefetchVecBaseImmOff(SDNode * N,SelectionDAG & DAG,unsigned ScalarSizeInBytes) combineSVEPrefetchVecBaseImmOff() argument
24751 performFPExtendCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const AArch64Subtarget * Subtarget) performFPExtendCombine() argument
24789 performBSPExpandForSVE(SDNode * N,SelectionDAG & DAG,const AArch64Subtarget * Subtarget) performBSPExpandForSVE() argument
24809 performDupLane128Combine(SDNode * N,SelectionDAG & DAG) performDupLane128Combine() argument
24847 tryCombineMULLWithUZP1(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,SelectionDAG & DAG) tryCombineMULLWithUZP1() argument
24981 performMULLCombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,SelectionDAG & DAG) performMULLCombine() argument
24994 performScalarToVectorCombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,SelectionDAG & DAG) performScalarToVectorCombine() argument
25043 SelectionDAG &DAG = DCI.DAG; PerformDAGCombine() local
25544 replaceBoolVectorBitcast(SDNode * N,SmallVectorImpl<SDValue> & Results,SelectionDAG & DAG) replaceBoolVectorBitcast() argument
25571 CustomNonLegalBITCASTResults(SDNode * N,SmallVectorImpl<SDValue> & Results,SelectionDAG & DAG,EVT ExtendVT,EVT CastVT) CustomNonLegalBITCASTResults() argument
25638 ReplaceAddWithADDP(SDNode * N,SmallVectorImpl<SDValue> & Results,SelectionDAG & DAG,const AArch64Subtarget * Subtarget) ReplaceAddWithADDP() argument
25687 ReplaceReductionResults(SDNode * N,SmallVectorImpl<SDValue> & Results,SelectionDAG & DAG,unsigned InterOp,unsigned AcrossOp) ReplaceReductionResults() argument
25734 createGPRPairNode(SelectionDAG & DAG,SDValue V) createGPRPairNode() argument
25750 ReplaceCMP_SWAP_128Results(SDNode * N,SmallVectorImpl<SDValue> & Results,SelectionDAG & DAG,const AArch64Subtarget * Subtarget) ReplaceCMP_SWAP_128Results() argument
25913 ReplaceATOMIC_LOAD_128Results(SDNode * N,SmallVectorImpl<SDValue> & Results,SelectionDAG & DAG,const AArch64Subtarget * Subtarget) ReplaceATOMIC_LOAD_128Results() argument
26639 preferredShiftLegalizationStrategy(SelectionDAG & DAG,SDNode * N,unsigned int ExpansionFactor) const preferredShiftLegalizationStrategy() argument
26902 getContainerForFixedLengthVector(SelectionDAG & DAG,EVT VT) getContainerForFixedLengthVector() argument
26929 getPredicateForFixedLengthVector(SelectionDAG & DAG,SDLoc & DL,EVT VT) getPredicateForFixedLengthVector() argument
26974 getPredicateForScalableVector(SelectionDAG & DAG,SDLoc & DL,EVT VT) getPredicateForScalableVector() argument
26982 getPredicateForVector(SelectionDAG & DAG,SDLoc & DL,EVT VT) getPredicateForVector() argument
26990 convertToScalableVector(SelectionDAG & DAG,EVT VT,SDValue V) convertToScalableVector() argument
27001 convertFromScalableVector(SelectionDAG & DAG,EVT VT,SDValue V) convertFromScalableVector() argument
27052 convertFixedMaskToScalableVector(SDValue Mask,SelectionDAG & DAG) convertFixedMaskToScalableVector() argument
27342 LowerToPredicatedOp(SDValue Op,SelectionDAG & DAG,unsigned NewOp) const LowerToPredicatedOp() argument
27853 GenerateFixedLengthSVETBL(SDValue Op,SDValue Op1,SDValue Op2,ArrayRef<int> ShuffleMask,EVT VT,EVT ContainerVT,SelectionDAG & DAG) GenerateFixedLengthSVETBL() argument
28163 isAllActivePredicate(SelectionDAG & DAG,SDValue N) const isAllActivePredicate() argument
[all...]
/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp481 performANDCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget & Subtarget) performANDCombine() argument
596 performORCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget & Subtarget) performORCombine() argument
717 shouldTransformMulToShiftsAddsSubs(APInt C,EVT VT,SelectionDAG & DAG,const MipsSubtarget & Subtarget) shouldTransformMulToShiftsAddsSubs() argument
793 genConstMult(SDValue X,APInt C,const SDLoc & DL,EVT VT,EVT ShiftTy,SelectionDAG & DAG) genConstMult() argument
828 performMULCombine(SDNode * N,SelectionDAG & DAG,const TargetLowering::DAGCombinerInfo & DCI,const MipsSETargetLowering * TL,const MipsSubtarget & Subtarget) performMULCombine() argument
845 performDSPShiftCombine(unsigned Opc,SDNode * N,EVT Ty,SelectionDAG & DAG,const MipsSubtarget & Subtarget) performDSPShiftCombine() argument
869 performSHLCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget & Subtarget) performSHLCombine() argument
892 performSRACombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget & Subtarget) performSRACombine() argument
938 performSRLCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget & Subtarget) performSRLCombine() argument
967 performSETCCCombine(SDNode * N,SelectionDAG & DAG) performSETCCCombine() argument
980 performVSELECTCombine(SDNode * N,SelectionDAG & DAG) performVSELECTCombine() argument
997 performXORCombine(SDNode * N,SelectionDAG & DAG,const MipsSubtarget & Subtarget) performXORCombine() argument
1026 SelectionDAG &DAG = DCI.DAG; PerformDAGCombine() local
1284 initAccumulator(SDValue In,const SDLoc & DL,SelectionDAG & DAG) initAccumulator() argument
1290 extractLOHI(SDValue Op,const SDLoc & DL,SelectionDAG & DAG) extractLOHI() argument
1308 lowerDSPIntr(SDValue Op,SelectionDAG & DAG,unsigned Opc) lowerDSPIntr() argument
1356 lowerMSACopyIntr(SDValue Op,SelectionDAG & DAG,unsigned Opc) lowerMSACopyIntr() argument
1369 lowerMSASplatZExt(SDValue Op,unsigned OpNr,SelectionDAG & DAG) lowerMSASplatZExt() argument
1413 lowerMSASplatImm(SDValue Op,unsigned ImmOp,SelectionDAG & DAG,bool IsSigned=false) lowerMSASplatImm() argument
1423 getBuildVectorSplat(EVT VecTy,SDValue SplatValue,bool BigEndian,SelectionDAG & DAG) getBuildVectorSplat() argument
1458 lowerMSABinaryBitImmIntr(SDValue Op,SelectionDAG & DAG,unsigned Opc,SDValue Imm,bool BigEndian) lowerMSABinaryBitImmIntr() argument
1502 truncateVecElts(SDValue Op,SelectionDAG & DAG) truncateVecElts() argument
1515 lowerMSABitClear(SDValue Op,SelectionDAG & DAG) lowerMSABitClear() argument
1525 lowerMSABitClearImm(SDValue Op,SelectionDAG & DAG) lowerMSABitClearImm() argument
2288 lowerMSALoadIntr(SDValue Op,SelectionDAG & DAG,unsigned Intr,const MipsSubtarget & Subtarget) lowerMSALoadIntr() argument
2362 lowerMSAStoreIntr(SDValue Op,SelectionDAG & DAG,unsigned Intr,const MipsSubtarget & Subtarget) lowerMSAStoreIntr() argument
2550 lowerVECTOR_SHUFFLE_SHF(SDValue Op,EVT ResTy,SmallVector<int,16> Indices,SelectionDAG & DAG) lowerVECTOR_SHUFFLE_SHF() argument
2631 isVECTOR_SHUFFLE_SPLATI(SDValue Op,EVT ResTy,SmallVector<int,16> Indices,SelectionDAG & DAG) isVECTOR_SHUFFLE_SPLATI() argument
2663 lowerVECTOR_SHUFFLE_ILVEV(SDValue Op,EVT ResTy,SmallVector<int,16> Indices,SelectionDAG & DAG) lowerVECTOR_SHUFFLE_ILVEV() argument
2709 lowerVECTOR_SHUFFLE_ILVOD(SDValue Op,EVT ResTy,SmallVector<int,16> Indices,SelectionDAG & DAG) lowerVECTOR_SHUFFLE_ILVOD() argument
2756 lowerVECTOR_SHUFFLE_ILVR(SDValue Op,EVT ResTy,SmallVector<int,16> Indices,SelectionDAG & DAG) lowerVECTOR_SHUFFLE_ILVR() argument
2803 lowerVECTOR_SHUFFLE_ILVL(SDValue Op,EVT ResTy,SmallVector<int,16> Indices,SelectionDAG & DAG) lowerVECTOR_SHUFFLE_ILVL() argument
2851 lowerVECTOR_SHUFFLE_PCKEV(SDValue Op,EVT ResTy,SmallVector<int,16> Indices,SelectionDAG & DAG) lowerVECTOR_SHUFFLE_PCKEV() argument
2894 lowerVECTOR_SHUFFLE_PCKOD(SDValue Op,EVT ResTy,SmallVector<int,16> Indices,SelectionDAG & DAG) lowerVECTOR_SHUFFLE_PCKOD() argument
2930 lowerVECTOR_SHUFFLE_VSHF(SDValue Op,EVT ResTy,const SmallVector<int,16> & Indices,SelectionDAG & DAG) lowerVECTOR_SHUFFLE_VSHF() argument
[all...]
/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNSchedStrategy.h398 : GCNSchedStage(StageID, DAG) {} in PreRARematStage() argument
329 OccInitialScheduleStage(GCNSchedStageID StageID,GCNScheduleDAGMILive & DAG) OccInitialScheduleStage() argument
347 UnclusteredHighRPStage(GCNSchedStageID StageID,GCNScheduleDAGMILive & DAG) UnclusteredHighRPStage() argument
362 ClusteredLowOccStage(GCNSchedStageID StageID,GCNScheduleDAGMILive & DAG) ClusteredLowOccStage() argument
406 ILPInitialScheduleStage(GCNSchedStageID StageID,GCNScheduleDAGMILive & DAG) ILPInitialScheduleStage() argument
[all...]
H A DAMDGPUExportClustering.cpp59 static void buildCluster(ArrayRef<SUnit *> Exports, ScheduleDAGInstrs *DAG) { in buildCluster()
82 static void removeExportDependencies(ScheduleDAGInstrs *DAG, SUnit &SU) { in removeExportDependencies()
108 void ExportClustering::apply(ScheduleDAGInstrs *DAG) { in apply()
H A DAMDGPUISelLowering.cpp51 unsigned AMDGPUTargetLowering::numBitsUnsigned(SDValue Op, SelectionDAG &DAG) { in numBitsUnsigned() argument
55 unsigned AMDGPUTargetLowering::numBitsSigned(SDValue Op, SelectionDAG &DAG) { in numBitsSigned() argument
863 const SelectionDAG &DAG, in isLoadBitCastBeneficial() argument
915 getNegatedExpression(SDValue Op,SelectionDAG & DAG,bool LegalOperations,bool ForCodeSize,NegatibleCost & Cost,unsigned Depth) const getNegatedExpression() argument
1298 addTokenForArgument(SDValue Chain,SelectionDAG & DAG,MachineFrameInfo & MFI,int ClobberedFI) const addTokenForArgument() argument
1335 SelectionDAG &DAG = CLI.DAG; lowerUnhandledCall() local
1604 SelectionDAG &DAG = DCI.DAG; combineFMinMaxLegacyImpl() local
1678 SelectionDAG &DAG = DCI.DAG; combineFMinMaxLegacy() local
1911 LowerDIVREM24(SDValue Op,SelectionDAG & DAG,bool Sign) const LowerDIVREM24() argument
2027 LowerUDIVREM64(SDValue Op,SelectionDAG & DAG,SmallVectorImpl<SDValue> & Results) const LowerUDIVREM64() argument
2396 extractF64Exponent(SDValue Hi,const SDLoc & SL,SelectionDAG & DAG) extractF64Exponent() argument
2580 allowApproxFunc(const SelectionDAG & DAG,SDNodeFlags Flags) allowApproxFunc() argument
2588 needsDenormHandlingF32(const SelectionDAG & DAG,SDValue Src,SDNodeFlags Flags) needsDenormHandlingF32() argument
2597 getIsLtSmallestNormal(SelectionDAG & DAG,SDValue Src,SDNodeFlags Flags) const getIsLtSmallestNormal() argument
2615 getIsFinite(SelectionDAG & DAG,SDValue Src,SDNodeFlags Flags) const getIsFinite() argument
2632 getScaledLogInput(SelectionDAG & DAG,const SDLoc SL,SDValue Src,SDNodeFlags Flags) const getScaledLogInput() argument
2690 getMad(SelectionDAG & DAG,const SDLoc & SL,EVT VT,SDValue X,SDValue Y,SDValue C,SDNodeFlags Flags=SDNodeFlags ()) getMad() argument
2800 LowerFLOGUnsafe(SDValue Src,const SDLoc & SL,SelectionDAG & DAG,bool IsLog10,SDNodeFlags Flags) const LowerFLOGUnsafe() argument
2890 lowerFEXPUnsafe(SDValue X,const SDLoc & SL,SelectionDAG & DAG,SDNodeFlags Flags) const lowerFEXPUnsafe() argument
2930 lowerFEXP10Unsafe(SDValue X,const SDLoc & SL,SelectionDAG & DAG,SDNodeFlags Flags) const lowerFEXP10Unsafe() argument
3212 LowerINT_TO_FP32(SDValue Op,SelectionDAG & DAG,bool Signed) const LowerINT_TO_FP32() argument
3338 LowerINT_TO_FP64(SDValue Op,SelectionDAG & DAG,bool Signed) const LowerINT_TO_FP64() argument
3452 LowerFP_TO_INT64(SDValue Op,SelectionDAG & DAG,bool Signed) const LowerFP_TO_INT64() argument
3697 isU24(SDValue Op,SelectionDAG & DAG) isU24() argument
3701 isI24(SDValue Op,SelectionDAG & DAG) isI24() argument
3710 SelectionDAG &DAG = DCI.DAG; simplifyMul24() local
3760 constantFoldBFE(SelectionDAG & DAG,IntTy Src0,uint32_t Offset,uint32_t Width,const SDLoc & DL) constantFoldBFE() argument
3813 SelectionDAG &DAG = DCI.DAG; performLoadCombine() local
3869 SelectionDAG &DAG = DCI.DAG; performStoreCombine() local
3915 SelectionDAG &DAG = DCI.DAG; performAssertSZExtCombine() local
3976 SelectionDAG &DAG = DCI.DAG; splitBinaryBitConstantOpImpl() local
4009 SelectionDAG &DAG = DCI.DAG; performShlCombine() local
4072 SelectionDAG &DAG = DCI.DAG; performSraCombine() local
4107 SelectionDAG &DAG = DCI.DAG; performSrlCombine() local
4149 SelectionDAG &DAG = DCI.DAG; performTruncateCombine() local
4240 getMul24(SelectionDAG & DAG,const SDLoc & SL,SDValue N0,SDValue N1,unsigned Size,bool Signed) getMul24() argument
4281 SelectionDAG &DAG = DCI.DAG; performMulCombine() local
4355 SelectionDAG &DAG = DCI.DAG; performMulLoHiCombine() local
4409 SelectionDAG &DAG = DCI.DAG; performMulhsCombine() local
4442 SelectionDAG &DAG = DCI.DAG; performMulhuCombine() local
4459 getFFBX_U32(SelectionDAG & DAG,SDValue Op,const SDLoc & DL,unsigned Opc) const getFFBX_U32() argument
4492 SelectionDAG &DAG = DCI.DAG; performCtlz_CttzCombine() local
4526 SelectionDAG &DAG = DCI.DAG; distributeOpThroughSelect() local
4545 SelectionDAG &DAG = DCI.DAG; foldFreeOpFromSelect() local
4638 SelectionDAG &DAG = DCI.DAG; performSelectCombine() local
4747 SelectionDAG &DAG = DCI.DAG; performFNegCombine() local
5009 SelectionDAG &DAG = DCI.DAG; performFAbsCombine() local
5046 SelectionDAG &DAG = DCI.DAG; PerformDAGCombine() local
5291 CreateLiveInRegister(SelectionDAG & DAG,const TargetRegisterClass * RC,Register Reg,EVT VT,const SDLoc & SL,bool RawReg) const CreateLiveInRegister() argument
5327 loadStackInputValue(SelectionDAG & DAG,EVT VT,const SDLoc & SL,int64_t Offset) const loadStackInputValue() argument
5343 storeStackInputValue(SelectionDAG & DAG,const SDLoc & SL,SDValue Chain,SDValue ArgVal,int64_t Offset) const storeStackInputValue() argument
5362 loadInputValue(SelectionDAG & DAG,const TargetRegisterClass * RC,EVT VT,const SDLoc & SL,const ArgDescriptor & Arg) const loadInputValue() argument
5578 getSqrtEstimate(SDValue Operand,SelectionDAG & DAG,int Enabled,int & RefinementSteps,bool & UseOneConstNR,bool Reciprocal) const getSqrtEstimate() argument
5596 getRecipEstimate(SDValue Operand,SelectionDAG & DAG,int Enabled,int & RefinementSteps) const getRecipEstimate() argument
5631 computeKnownBitsForTargetNode(const SDValue Op,KnownBits & Known,const APInt & DemandedElts,const SelectionDAG & DAG,unsigned Depth) const computeKnownBitsForTargetNode() argument
5795 ComputeNumSignBitsForTargetNode(SDValue Op,const APInt & DemandedElts,const SelectionDAG & DAG,unsigned Depth) const ComputeNumSignBitsForTargetNode() argument
5893 isKnownNeverNaNForTargetNode(SDValue Op,const SelectionDAG & DAG,bool SNaN,unsigned Depth) const isKnownNeverNaNForTargetNode() argument
[all...]
H A DSIMachineScheduler.h59 SIScheduleDAGMI *DAG; variable
101 SIScheduleBlock(SIScheduleDAGMI *DAG, SIScheduleBlockCreator *BC, in SIScheduleBlock() argument
223 SIScheduleDAGMI *DAG; variable
319 SIScheduleDAGMI *DAG; variable
412 SIScheduleDAGMI *DAG; variable
416 SIScheduler(SIScheduleDAGMI *DAG) argument
[all...]
H A DAMDGPUIGroupLP.cpp154 ScheduleDAGInstrs *DAG; global() member in __anonc429d1160111::SchedGroup
235 SchedGroup(SchedGroupMask SGMask,std::optional<unsigned> MaxSize,ScheduleDAGInstrs * DAG,const SIInstrInfo * TII) SchedGroup() argument
241 SchedGroup(SchedGroupMask SGMask,std::optional<unsigned> MaxSize,int SyncID,ScheduleDAGInstrs * DAG,const SIInstrInfo * TII) SchedGroup() argument
248 resetEdges(SUnit & SU,ScheduleDAGInstrs * DAG) resetEdges() argument
277 ScheduleDAGMI *DAG; global() member in __anonc429d1160111::PipelineSolver
368 PipelineSolver(DenseMap<int,SmallVector<SchedGroup,4>> & SyncedSchedGroups,DenseMap<int,SUnitsToCandidateSGsMap> & SyncedInstrs,ScheduleDAGMI * DAG,bool IsBottomUp=1) PipelineSolver() argument
846 ScheduleDAGInstrs *DAG; global() member in __anonc429d1160111::IGLPStrategy
863 IGLPStrategy(ScheduleDAGInstrs * DAG,const SIInstrInfo * TII) IGLPStrategy() argument
877 shouldApplyStrategy(ScheduleDAGInstrs * DAG,AMDGPU::SchedulingPhase Phase) shouldApplyStrategy() argument
882 MFMASmallGemmOpt(ScheduleDAGInstrs * DAG,const SIInstrInfo * TII) MFMASmallGemmOpt() argument
949 auto DAG = SyncPipe[0].DAG; apply() local
984 auto DAG = SyncPipe[0].DAG; apply() local
1024 auto DAG = SyncPipe[0].DAG; apply() local
1240 auto DAG = SyncPipe[0].DAG; apply() local
1323 auto DAG = SyncPipe[0].DAG; apply() local
1351 MFMAExpInterleaveOpt(ScheduleDAGInstrs * DAG,const SIInstrInfo * TII) MFMAExpInterleaveOpt() argument
1554 shouldApplyStrategy(ScheduleDAGInstrs * DAG,AMDGPU::SchedulingPhase Phase) shouldApplyStrategy() argument
1880 auto DAG = SyncPipe[0].DAG; apply() local
2039 auto DAG = SyncPipe[0].DAG; apply() local
2057 shouldApplyStrategy(ScheduleDAGInstrs * DAG,AMDGPU::SchedulingPhase Phase) shouldApplyStrategy() argument
2062 MFMASmallGemmSingleWaveOpt(ScheduleDAGInstrs * DAG,const SIInstrInfo * TII) MFMASmallGemmSingleWaveOpt() argument
2318 createIGLPStrategy(IGLPStrategyID ID,ScheduleDAGInstrs * DAG,const SIInstrInfo * TII) createIGLPStrategy() argument
2336 ScheduleDAGMI *DAG; global() member in __anonc429d1160111::IGroupLPDAGMutation
[all...]
/llvm-project/llvm/lib/CodeGen/
H A DMacroFusion.cpp53 bool llvm::fuseInstructionPair(ScheduleDAGInstrs &DAG, SUnit &FirstSU, in fuseInstructionPair()
168 void MacroFusion::apply(ScheduleDAGInstrs *DAG) { in apply()
182 bool MacroFusion::scheduleAdjacentImpl(ScheduleDAGInstrs &DAG, SUnit &AnchorSU) { in scheduleAdjacentImpl()
/llvm-project/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.cpp39 EmitSpecializedLibcall(SelectionDAG & DAG,const SDLoc & dl,SDValue Chain,SDValue Dst,SDValue Src,SDValue Size,unsigned Align,RTLIB::Libcall LC) const EmitSpecializedLibcall() argument
142 shouldGenerateInlineTPLoop(const ARMSubtarget & Subtarget,const SelectionDAG & DAG,ConstantSDNode * ConstantSize,Align Alignment,bool IsMemcpy) shouldGenerateInlineTPLoop() argument
169 EmitTargetCodeForMemcpy(SelectionDAG & DAG,const SDLoc & dl,SDValue Chain,SDValue Dst,SDValue Src,SDValue Size,Align Alignment,bool isVolatile,bool AlwaysInline,MachinePointerInfo DstPtrInfo,MachinePointerInfo SrcPtrInfo) const EmitTargetCodeForMemcpy() argument
287 EmitTargetCodeForMemmove(SelectionDAG & DAG,const SDLoc & dl,SDValue Chain,SDValue Dst,SDValue Src,SDValue Size,Align Alignment,bool isVolatile,MachinePointerInfo DstPtrInfo,MachinePointerInfo SrcPtrInfo) const EmitTargetCodeForMemmove() argument
295 EmitTargetCodeForMemset(SelectionDAG & DAG,const SDLoc & dl,SDValue Chain,SDValue Dst,SDValue Src,SDValue Size,Align Alignment,bool isVolatile,bool AlwaysInline,MachinePointerInfo DstPtrInfo) const EmitTargetCodeForMemset() argument
[all...]
H A DARMISelLowering.cpp160 handleCMSEValue(const SDValue & Value,const ISD::InputArg & Arg,SelectionDAG & DAG,const SDLoc & DL) handleCMSEValue() argument
2047 isS16(const SDValue & Op,SelectionDAG & DAG) isS16() argument
2186 MoveToHPR(const SDLoc & dl,SelectionDAG & DAG,MVT LocVT,MVT ValVT,SDValue Val) const MoveToHPR() argument
2200 MoveFromHPR(const SDLoc & dl,SelectionDAG & DAG,MVT LocVT,MVT ValVT,SDValue Val) const MoveFromHPR() argument
2220 LowerCallResult(SDValue Chain,SDValue InGlue,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals,bool isThisReturn,SDValue ThisVal,bool isCmseNSCall) const LowerCallResult() argument
2315 computeAddrForCallArg(const SDLoc & dl,SelectionDAG & DAG,const CCValAssign & VA,SDValue StackPtr,bool IsTailCall,int SPDiff) const computeAddrForCallArg() argument
2341 PassF64ArgInRegs(const SDLoc & dl,SelectionDAG & DAG,SDValue Chain,SDValue & Arg,RegsToPassVector & RegsToPass,CCValAssign & VA,CCValAssign & NextVA,SDValue & StackPtr,SmallVectorImpl<SDValue> & MemOpChains,bool IsTailCall,int SPDiff) const PassF64ArgInRegs() argument
2382 SelectionDAG &DAG = CLI.DAG; LowerCall() local
3034 const SelectionDAG &DAG = CLI.DAG; IsEligibleForTailCallOptimization() local
3174 LowerInterruptReturn(SmallVectorImpl<SDValue> & RetOps,const SDLoc & DL,SelectionDAG & DAG) LowerInterruptReturn() argument
3467 LowerWRITE_REGISTER(SDValue Op,SelectionDAG & DAG) LowerWRITE_REGISTER() argument
3736 LowerToTLSExecModels(GlobalAddressSDNode * GA,SelectionDAG & DAG,TLSModel::Model model) const LowerToTLSExecModels() argument
3832 promoteToConstantPool(const ARMTargetLowering * TLI,const GlobalValue * GV,SelectionDAG & DAG,EVT PtrVT,const SDLoc & dl) promoteToConstantPool() argument
4097 LowerINTRINSIC_VOID(SDValue Op,SelectionDAG & DAG,const ARMSubtarget * Subtarget) const LowerINTRINSIC_VOID() argument
4137 LowerINTRINSIC_WO_CHAIN(SDValue Op,SelectionDAG & DAG,const ARMSubtarget * Subtarget) const LowerINTRINSIC_WO_CHAIN() argument
4280 LowerATOMIC_FENCE(SDValue Op,SelectionDAG & DAG,const ARMSubtarget * Subtarget) LowerATOMIC_FENCE() argument
4316 LowerPREFETCH(SDValue Op,SelectionDAG & DAG,const ARMSubtarget * Subtarget) LowerPREFETCH() argument
4343 LowerVASTART(SDValue Op,SelectionDAG & DAG) LowerVASTART() argument
4360 GetF64FormalArgument(CCValAssign & VA,CCValAssign & NextVA,SDValue & Root,SelectionDAG & DAG,const SDLoc & dl) const GetF64FormalArgument() argument
4402 StoreByValRegs(CCState & CCInfo,SelectionDAG & DAG,const SDLoc & dl,SDValue & Chain,const Value * OrigArg,unsigned InRegsParamRecordIdx,int ArgOffset,unsigned ArgSize) const StoreByValRegs() argument
4456 VarArgStyleRegisters(CCState & CCInfo,SelectionDAG & DAG,const SDLoc & dl,SDValue & Chain,unsigned ArgOffset,unsigned TotalArgRegsSaveSize,bool ForceMutable) const VarArgStyleRegisters() argument
4476 splitValueIntoRegisterParts(SelectionDAG & DAG,const SDLoc & DL,SDValue Val,SDValue * Parts,unsigned NumParts,MVT PartVT,std::optional<CallingConv::ID> CC) const splitValueIntoRegisterParts() argument
4492 joinRegisterPartsIntoValue(SelectionDAG & DAG,const SDLoc & DL,const SDValue * Parts,unsigned NumParts,MVT PartVT,EVT ValueVT,std::optional<CallingConv::ID> CC) const joinRegisterPartsIntoValue() argument
4510 LowerFormalArguments(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const LowerFormalArguments() argument
4763 getARMCmp(SDValue LHS,SDValue RHS,ISD::CondCode CC,SDValue & ARMcc,SelectionDAG & DAG,const SDLoc & dl) const getARMCmp() argument
4902 getVFPCmp(SDValue LHS,SDValue RHS,SelectionDAG & DAG,const SDLoc & dl,bool Signaling) const getVFPCmp() argument
4941 getARMXALUOOp(SDValue Op,SelectionDAG & DAG,SDValue & ARMcc) const getARMXALUOOp() argument
5034 ConvertBooleanCarryToCarryFlag(SDValue BoolCarry,SelectionDAG & DAG) ConvertBooleanCarryToCarryFlag() argument
5047 ConvertCarryFlagToBooleanCarry(SDValue Flags,EVT VT,SelectionDAG & DAG) ConvertCarryFlagToBooleanCarry() argument
5094 LowerADDSUBSAT(SDValue Op,SelectionDAG & DAG,const ARMSubtarget * Subtarget) LowerADDSUBSAT() argument
5333 LowerSaturatingConditional(SDValue Op,SelectionDAG & DAG) LowerSaturatingConditional() argument
5632 bitcastf32Toi32(SDValue Op,SelectionDAG & DAG) bitcastf32Toi32() argument
5644 expandf64Toi32(SDValue Op,SelectionDAG & DAG,SDValue & RetVal1,SDValue & RetVal2) expandf64Toi32() argument
5882 LowerVectorFP_TO_INT(SDValue Op,SelectionDAG & DAG) LowerVectorFP_TO_INT() argument
5951 LowerFP_TO_INT_SAT(SDValue Op,SelectionDAG & DAG,const ARMSubtarget * Subtarget) LowerFP_TO_INT_SAT() argument
5988 LowerVectorINT_TO_FP(SDValue Op,SelectionDAG & DAG) LowerVectorINT_TO_FP() argument
6192 ExpandREAD_REGISTER(SDNode * N,SmallVectorImpl<SDValue> & Results,SelectionDAG & DAG) ExpandREAD_REGISTER() argument
6217 CombineVMOVDRRCandidateWithVecOp(const SDNode * BC,SelectionDAG & DAG) CombineVMOVDRRCandidateWithVecOp() argument
6264 ExpandBITCAST(SDNode * N,SelectionDAG & DAG,const ARMSubtarget * Subtarget) const ExpandBITCAST() argument
6325 getZeroVector(EVT VT,SelectionDAG & DAG,const SDLoc & dl) getZeroVector() argument
6533 LowerCTTZ(SDNode * N,SelectionDAG & DAG,const ARMSubtarget * ST) LowerCTTZ() argument
6589 LowerCTPOP(SDNode * N,SelectionDAG & DAG,const ARMSubtarget * ST) LowerCTPOP() argument
6675 LowerShift(SDNode * N,SelectionDAG & DAG,const ARMSubtarget * ST) LowerShift() argument
6718 Expand64BitShift(SDNode * N,SelectionDAG & DAG,const ARMSubtarget * ST) Expand64BitShift() argument
6795 LowerVSETCC(SDValue Op,SelectionDAG & DAG,const ARMSubtarget * ST) LowerVSETCC() argument
6975 LowerSETCCCARRY(SDValue Op,SelectionDAG & DAG) LowerSETCCCARRY() argument
7009 isVMOVModifiedImm(uint64_t SplatBits,uint64_t SplatUndef,unsigned SplatBitSize,SelectionDAG & DAG,const SDLoc & dl,EVT & VT,EVT VectorVT,VMOVModImmType type) isVMOVModifiedImm() argument
7156 LowerConstantFP(SDValue Op,SelectionDAG & DAG,const ARMSubtarget * ST) const LowerConstantFP() argument
7682 LowerBuildVectorOfFPTrunc(SDValue BV,SelectionDAG & DAG,const ARMSubtarget * ST) LowerBuildVectorOfFPTrunc() argument
7735 LowerBuildVectorOfFPExt(SDValue BV,SelectionDAG & DAG,const ARMSubtarget * ST) LowerBuildVectorOfFPExt() argument
7777 IsSingleInstrConstant(SDValue N,SelectionDAG & DAG,const ARMSubtarget * ST,const SDLoc & dl) IsSingleInstrConstant() argument
7794 LowerBUILD_VECTOR_i1(SDValue Op,SelectionDAG & DAG,const ARMSubtarget * ST) LowerBUILD_VECTOR_i1() argument
7856 LowerBUILD_VECTORToVIDUP(SDValue Op,SelectionDAG & DAG,const ARMSubtarget * ST) LowerBUILD_VECTORToVIDUP() argument
7931 LowerBUILD_VECTOR(SDValue Op,SelectionDAG & DAG,const ARMSubtarget * ST) const LowerBUILD_VECTOR() argument
8494 GeneratePerfectShuffle(unsigned PFEntry,SDValue LHS,SDValue RHS,SelectionDAG & DAG,const SDLoc & dl) GeneratePerfectShuffle() argument
8552 LowerVECTOR_SHUFFLEv8i8(SDValue Op,ArrayRef<int> ShuffleMask,SelectionDAG & DAG) LowerVECTOR_SHUFFLEv8i8() argument
8570 LowerReverse_VECTOR_SHUFFLE(SDValue Op,SelectionDAG & DAG) LowerReverse_VECTOR_SHUFFLE() argument
8605 PromoteMVEPredVector(SDLoc dl,SDValue Pred,EVT VT,SelectionDAG & DAG) PromoteMVEPredVector() argument
8639 LowerVECTOR_SHUFFLE_i1(SDValue Op,SelectionDAG & DAG,const ARMSubtarget * ST) LowerVECTOR_SHUFFLE_i1() argument
8693 LowerVECTOR_SHUFFLEUsingMovs(SDValue Op,ArrayRef<int> ShuffleMask,SelectionDAG & DAG) LowerVECTOR_SHUFFLEUsingMovs() argument
8779 LowerVECTOR_SHUFFLEUsingOneOff(SDValue Op,ArrayRef<int> ShuffleMask,SelectionDAG & DAG) LowerVECTOR_SHUFFLEUsingOneOff() argument
8828 LowerVECTOR_SHUFFLE(SDValue Op,SelectionDAG & DAG,const ARMSubtarget * ST) LowerVECTOR_SHUFFLE() argument
9056 LowerINSERT_VECTOR_ELT_i1(SDValue Op,SelectionDAG & DAG,const ARMSubtarget * ST) LowerINSERT_VECTOR_ELT_i1() argument
9119 LowerEXTRACT_VECTOR_ELT_i1(SDValue Op,SelectionDAG & DAG,const ARMSubtarget * ST) LowerEXTRACT_VECTOR_ELT_i1() argument
9137 LowerEXTRACT_VECTOR_ELT(SDValue Op,SelectionDAG & DAG,const ARMSubtarget * ST) LowerEXTRACT_VECTOR_ELT() argument
9158 LowerCONCAT_VECTORS_i1(SDValue Op,SelectionDAG & DAG,const ARMSubtarget * ST) LowerCONCAT_VECTORS_i1() argument
9240 LowerCONCAT_VECTORS(SDValue Op,SelectionDAG & DAG,const ARMSubtarget * ST) LowerCONCAT_VECTORS() argument
9265 LowerEXTRACT_SUBVECTOR(SDValue Op,SelectionDAG & DAG,const ARMSubtarget * ST) LowerEXTRACT_SUBVECTOR() argument
9319 LowerTruncatei1(SDNode * N,SelectionDAG & DAG,const ARMSubtarget * ST) LowerTruncatei1() argument
9335 LowerTruncate(SDNode * N,SelectionDAG & DAG,const ARMSubtarget * Subtarget) LowerTruncate() argument
9395 LowerVectorExtend(SDNode * N,SelectionDAG & DAG,const ARMSubtarget * Subtarget) LowerVectorExtend() argument
9431 isExtendedBUILD_VECTOR(SDNode * N,SelectionDAG & DAG,bool isSigned) isExtendedBUILD_VECTOR() argument
9484 isSignExtended(SDNode * N,SelectionDAG & DAG) isSignExtended() argument
9494 isZeroExtended(SDNode * N,SelectionDAG & DAG) isZeroExtended() argument
9523 AddRequiredExtensionForVMULL(SDValue N,SelectionDAG & DAG,const EVT & OrigTy,const EVT & ExtTy,unsigned ExtOpcode) AddRequiredExtensionForVMULL() argument
9545 SkipLoadExtensionForVMULL(LoadSDNode * LD,SelectionDAG & DAG) SkipLoadExtensionForVMULL() argument
9569 SkipExtensionForVMULL(SDNode * N,SelectionDAG & DAG) SkipExtensionForVMULL() argument
9619 isAddSubSExt(SDNode * N,SelectionDAG & DAG) isAddSubSExt() argument
9630 isAddSubZExt(SDNode * N,SelectionDAG & DAG) isAddSubZExt() argument
9641 LowerMUL(SDValue Op,SelectionDAG & DAG) LowerMUL() argument
9717 LowerSDIV_v4i8(SDValue X,SDValue Y,const SDLoc & dl,SelectionDAG & DAG) LowerSDIV_v4i8() argument
9748 LowerSDIV_v4i16(SDValue N0,SDValue N1,const SDLoc & dl,SelectionDAG & DAG) LowerSDIV_v4i16() argument
9786 LowerSDIV(SDValue Op,SelectionDAG & DAG,const ARMSubtarget * ST) LowerSDIV() argument
9822 LowerUDIV(SDValue Op,SelectionDAG & DAG,const ARMSubtarget * ST) LowerUDIV() argument
9899 LowerUADDSUBO_CARRY(SDValue Op,SelectionDAG & DAG) LowerUADDSUBO_CARRY() argument
10018 LowerWindowsDIVLibCall(SDValue Op,SelectionDAG & DAG,bool Signed,SDValue & Chain) const LowerWindowsDIVLibCall() argument
10061 BuildSDIVPow2(SDNode * N,const APInt & Divisor,SelectionDAG & DAG,SmallVectorImpl<SDNode * > & Created) const BuildSDIVPow2() argument
10098 LowerDIV_Windows(SDValue Op,SelectionDAG & DAG,bool Signed) const LowerDIV_Windows() argument
10110 WinDBZCheckDenominator(SelectionDAG & DAG,SDNode * N,SDValue InChain) WinDBZCheckDenominator() argument
10122 ExpandDIV_Windows(SDValue Op,SelectionDAG & DAG,bool Signed,SmallVectorImpl<SDValue> & Results) const ExpandDIV_Windows() argument
10143 LowerPredicateLoad(SDValue Op,SelectionDAG & DAG) LowerPredicateLoad() argument
10201 LowerPredicateStore(SDValue Op,SelectionDAG & DAG) LowerPredicateStore() argument
10239 LowerSTORE(SDValue Op,SelectionDAG & DAG,const ARMSubtarget * Subtarget) LowerSTORE() argument
10278 LowerMLOAD(SDValue Op,SelectionDAG & DAG) LowerMLOAD() argument
10305 LowerVecReduce(SDValue Op,SelectionDAG & DAG,const ARMSubtarget * ST) LowerVecReduce() argument
10371 LowerVecReduceF(SDValue Op,SelectionDAG & DAG,const ARMSubtarget * ST) LowerVecReduceF() argument
10378 LowerVecReduceMinMax(SDValue Op,SelectionDAG & DAG,const ARMSubtarget * ST) LowerVecReduceMinMax() argument
10452 LowerAtomicLoadStore(SDValue Op,SelectionDAG & DAG) LowerAtomicLoadStore() argument
10464 ReplaceREADCYCLECOUNTER(SDNode * N,SmallVectorImpl<SDValue> & Results,SelectionDAG & DAG,const ARMSubtarget * Subtarget) ReplaceREADCYCLECOUNTER() argument
10485 createGPRPairNode(SelectionDAG & DAG,SDValue V) createGPRPairNode() argument
10502 ReplaceCMP_SWAP_64Results(SDNode * N,SmallVectorImpl<SDValue> & Results,SelectionDAG & DAG) ReplaceCMP_SWAP_64Results() argument
10712 ReplaceLongIntrinsic(SDNode * N,SmallVectorImpl<SDValue> & Results,SelectionDAG & DAG) ReplaceLongIntrinsic() argument
12536 isConditionalZeroOrAllOnes(SDNode * N,bool AllOnes,SDValue & CC,bool & Invert,SDValue & OtherOp,SelectionDAG & DAG) isConditionalZeroOrAllOnes() argument
12609 SelectionDAG &DAG = DCI.DAG; combineSelectAndUse() local
12670 SelectionDAG &DAG = DCI.DAG; AddCombineToVPADD() local
12710 SelectionDAG &DAG = DCI.DAG; AddCombineVUZPToVPADDL() local
12804 SelectionDAG &DAG = DCI.DAG; AddCombineBUILD_VECTORToVPADDL() local
12878 SelectionDAG &DAG = DCI.DAG; AddCombineTo64BitSMLAL16() local
13036 SelectionDAG &DAG = DCI.DAG; AddCombineTo64bitMLAL() local
13124 SelectionDAG &DAG = DCI.DAG; AddCombineTo64bitUMAAL() local
13140 PerformUMLALCombine(SDNode * N,SelectionDAG & DAG,const ARMSubtarget * Subtarget) PerformUMLALCombine() argument
13165 SelectionDAG &DAG(DCI.DAG); PerformAddcSubcCombine() local
13199 SelectionDAG &DAG = DCI.DAG; PerformAddeSubeCombine() local
13334 PerformVQDMULHCombine(SDNode * N,SelectionDAG & DAG) PerformVQDMULHCombine() argument
13581 TryDistrubutionADDVecReduce(SDNode * N,SelectionDAG & DAG) TryDistrubutionADDVecReduce() argument
13726 PerformADDVecReduce(SDNode * N,SelectionDAG & DAG,const ARMSubtarget * Subtarget) PerformADDVecReduce() argument
14020 SelectionDAG &DAG = DCI.DAG; PerformSHLSimplify() local
14060 PerformSubCSINCCombine(SDNode * N,SelectionDAG & DAG) PerformSubCSINCCombine() argument
14139 SelectionDAG &DAG = DCI.DAG; PerformVMULCombine() local
14164 PerformMVEVMULLCombine(SDNode * N,SelectionDAG & DAG,const ARMSubtarget * Subtarget) PerformMVEVMULLCombine() argument
14232 SelectionDAG &DAG = DCI.DAG; PerformMULCombine() local
14357 SelectionDAG &DAG = DCI.DAG; CombineANDShift() local
14434 SelectionDAG &DAG = DCI.DAG; PerformANDCombine() local
14515 SelectionDAG &DAG = DCI.DAG; PerformORCombineToSMULWBT() local
14547 SelectionDAG &DAG = DCI.DAG; PerformORCombineToBFI() local
14694 PerformORCombine_i1(SDNode * N,SelectionDAG & DAG,const ARMSubtarget * Subtarget) PerformORCombine_i1() argument
14727 SelectionDAG &DAG = DCI.DAG; PerformORCombine() local
14824 SelectionDAG &DAG = DCI.DAG; PerformXORCombine() local
14925 PerformBFICombine(SDNode * N,SelectionDAG & DAG) PerformBFICombine() argument
15033 PerformCMPZCombine(SDNode * N,SelectionDAG & DAG) PerformCMPZCombine() argument
15046 PerformCSETCombine(SDNode * N,SelectionDAG & DAG) PerformCSETCombine() argument
15085 SelectionDAG &DAG = DCI.DAG; PerformVMOVRRDCombine() local
15160 PerformVMOVDRRCombine(SDNode * N,SelectionDAG & DAG) PerformVMOVDRRCombine() argument
15238 PerformVMOVrhCombine(SDNode * N,SelectionDAG & DAG) PerformVMOVrhCombine() argument
15292 SelectionDAG &DAG = DCI.DAG; PerformBUILD_VECTORCombine() local
15371 SelectionDAG &DAG = DCI.DAG; PerformARMBUILD_VECTORCombine() local
15442 PerformVECTOR_REG_CASTCombine(SDNode * N,SelectionDAG & DAG,const ARMSubtarget * ST) PerformVECTOR_REG_CASTCombine() argument
15467 PerformVCMPCombine(SDNode * N,SelectionDAG & DAG,const ARMSubtarget * Subtarget) PerformVCMPCombine() argument
15509 SelectionDAG &DAG = DCI.DAG; PerformInsertEltCombine() local
15650 PerformSignExtendInregCombine(SDNode * N,SelectionDAG & DAG) PerformSignExtendInregCombine() argument
15707 PerformShuffleVMOVNCombine(ShuffleVectorSDNode * N,SelectionDAG & DAG) PerformShuffleVMOVNCombine() argument
15731 PerformVECTOR_SHUFFLECombine(SDNode * N,SelectionDAG & DAG) PerformVECTOR_SHUFFLECombine() argument
15806 SelectionDAG &DAG = DCI.DAG; TryCombineBaseUpdate() local
16106 getPointerConstIncrement(unsigned Opcode,SDValue Ptr,SDValue Inc,const SelectionDAG & DAG) getPointerConstIncrement() argument
16273 SelectionDAG &DAG = DCI.DAG; PerformMVEVLDCombine() local
16393 SelectionDAG &DAG = DCI.DAG; CombineVLDDUP() local
16513 PerformVDUPCombine(SDNode * N,SelectionDAG & DAG,const ARMSubtarget * Subtarget) PerformVDUPCombine() argument
16568 PerformTruncatingStoreCombine(StoreSDNode * St,SelectionDAG & DAG) PerformTruncatingStoreCombine() argument
16653 PerformSplittingToNarrowingStores(StoreSDNode * St,SelectionDAG & DAG) PerformSplittingToNarrowingStores() argument
16746 PerformSplittingMVETruncToNarrowingStores(StoreSDNode * St,SelectionDAG & DAG) PerformSplittingMVETruncToNarrowingStores() argument
16787 PerformExtractFpToIntStores(StoreSDNode * St,SelectionDAG & DAG) PerformExtractFpToIntStores() argument
16853 SelectionDAG &DAG = DCI.DAG; PerformSTORECombine() local
16876 SelectionDAG &DAG = DCI.DAG; PerformSTORECombine() local
16912 PerformVCVTCombine(SDNode * N,SelectionDAG & DAG,const ARMSubtarget * Subtarget) PerformVCVTCombine() argument
16960 PerformFAddVSelectCombine(SDNode * N,SelectionDAG & DAG,const ARMSubtarget * Subtarget) PerformFAddVSelectCombine() argument
17003 PerformFADDVCMLACombine(SDNode * N,SelectionDAG & DAG) PerformFADDVCMLACombine() argument
17034 PerformFADDCombine(SDNode * N,SelectionDAG & DAG,const ARMSubtarget * Subtarget) PerformFADDCombine() argument
17052 PerformVMulVCTPCombine(SDNode * N,SelectionDAG & DAG,const ARMSubtarget * Subtarget) PerformVMulVCTPCombine() argument
17110 PerformVECREDUCE_ADDCombine(SDNode * N,SelectionDAG & DAG,const ARMSubtarget * ST) PerformVECREDUCE_ADDCombine() argument
17370 PerformReduceShuffleCombine(SDNode * N,SelectionDAG & DAG) PerformReduceShuffleCombine() argument
17480 PerformLongShiftCombine(SDNode * N,SelectionDAG & DAG) PerformLongShiftCombine() argument
17511 SelectionDAG &DAG = DCI.DAG; PerformIntrinsicCombine() local
17739 SelectionDAG &DAG = DCI.DAG; PerformShiftCombine() local
17813 PerformSplittingToWideningLoad(SDNode * N,SelectionDAG & DAG) PerformSplittingToWideningLoad() argument
17894 PerformExtendCombine(SDNode * N,SelectionDAG & DAG,const ARMSubtarget * ST) PerformExtendCombine() argument
17937 PerformFPExtendCombine(SDNode * N,SelectionDAG & DAG,const ARMSubtarget * ST) PerformFPExtendCombine() argument
17948 PerformMinMaxToSatCombine(SDValue Op,SelectionDAG & DAG,const ARMSubtarget * Subtarget) PerformMinMaxToSatCombine() argument
17989 PerformMinMaxCombine(SDNode * N,SelectionDAG & DAG,const ARMSubtarget * ST) PerformMinMaxCombine() argument
18301 SelectionDAG &DAG = DCI.DAG; PerformHWLoopCombine() local
18310 __anon6f7513dc2c02(SDNode *Br, SDValue Dest, SelectionDAG &DAG) PerformHWLoopCombine() argument
18587 SelectionDAG &DAG = DCI.DAG; PerformBITCASTCombine() local
18624 SelectionDAG &DAG = DCI.DAG; PerformMVETruncCombine() local
18725 PerformSplittingMVEEXTToWideningLoad(SDNode * N,SelectionDAG & DAG) PerformSplittingMVEEXTToWideningLoad() argument
18793 SelectionDAG &DAG = DCI.DAG; PerformMVEExtCombine() local
19803 getARMIndexedAddressParts(SDNode * Ptr,EVT VT,bool isSEXTLoad,SDValue & Base,SDValue & Offset,bool & isInc,SelectionDAG & DAG) getARMIndexedAddressParts() argument
19862 getT2IndexedAddressParts(SDNode * Ptr,EVT VT,bool isSEXTLoad,SDValue & Base,SDValue & Offset,bool & isInc,SelectionDAG & DAG) getT2IndexedAddressParts() argument
19887 getMVEIndexedAddressParts(SDNode * Ptr,EVT VT,Align Alignment,bool isSEXTLoad,bool IsMasked,bool isLE,SDValue & Base,SDValue & Offset,bool & isInc,SelectionDAG & DAG) getMVEIndexedAddressParts() argument
20093 computeKnownBitsForTargetNode(const SDValue Op,KnownBits & Known,const APInt & DemandedElts,const SelectionDAG & DAG,unsigned Depth) const computeKnownBitsForTargetNode() argument
21537 preferredShiftLegalizationStrategy(SelectionDAG & DAG,SDNode * N,unsigned ExpansionFactor) const preferredShiftLegalizationStrategy() argument
[all...]
/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp199 convertValVTToLocVT(SelectionDAG & DAG,SDValue Val,const CCValAssign & VA,const SDLoc & DL) convertValVTToLocVT() argument
215 convertLocVTToValVT(SelectionDAG & DAG,SDValue Val,const CCValAssign & VA,const SDLoc & DL) convertLocVTToValVT() argument
230 unpackFromRegLoc(const CSKYSubtarget & Subtarget,SelectionDAG & DAG,SDValue Chain,const CCValAssign & VA,const SDLoc & DL) unpackFromRegLoc() argument
261 unpackFromMemLoc(SelectionDAG & DAG,SDValue Chain,const CCValAssign & VA,const SDLoc & DL) unpackFromMemLoc() argument
288 unpack64(SelectionDAG & DAG,SDValue Chain,const CCValAssign & VA,const SDLoc & DL) unpack64() argument
330 LowerFormalArguments(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & DL,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const LowerFormalArguments() argument
507 SelectionDAG &DAG = CLI.DAG; LowerCall() local
784 getTargetConstantPoolValue(GlobalAddressSDNode * N,EVT Ty,SelectionDAG & DAG,unsigned Flags) const getTargetConstantPoolValue() argument
1045 getTargetConstantPoolValue(ExternalSymbolSDNode * N,EVT Ty,SelectionDAG & DAG,unsigned Flags) const getTargetConstantPoolValue() argument
1056 getTargetConstantPoolValue(JumpTableSDNode * N,EVT Ty,SelectionDAG & DAG,unsigned Flags) const getTargetConstantPoolValue() argument
1066 getTargetConstantPoolValue(BlockAddressSDNode * N,EVT Ty,SelectionDAG & DAG,unsigned Flags) const getTargetConstantPoolValue() argument
1077 getTargetConstantPoolValue(ConstantPoolSDNode * N,EVT Ty,SelectionDAG & DAG,unsigned Flags) const getTargetConstantPoolValue() argument
1087 getTargetNode(GlobalAddressSDNode * N,SDLoc DL,EVT Ty,SelectionDAG & DAG,unsigned Flags) const getTargetNode() argument
1093 getTargetNode(ExternalSymbolSDNode * N,SDLoc DL,EVT Ty,SelectionDAG & DAG,unsigned Flags) const getTargetNode() argument
1099 getTargetNode(JumpTableSDNode * N,SDLoc DL,EVT Ty,SelectionDAG & DAG,unsigned Flags) const getTargetNode() argument
1105 getTargetNode(BlockAddressSDNode * N,SDLoc DL,EVT Ty,SelectionDAG & DAG,unsigned Flags) const getTargetNode() argument
1112 getTargetNode(ConstantPoolSDNode * N,SDLoc DL,EVT Ty,SelectionDAG & DAG,unsigned Flags) const getTargetNode() argument
1299 getStaticTLSAddr(GlobalAddressSDNode * N,SelectionDAG & DAG,bool UseGOT) const getStaticTLSAddr() argument
[all...]
/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp760 getTargetNode(GlobalAddressSDNode * N,SDLoc DL,EVT Ty,SelectionDAG & DAG,unsigned Flags) getTargetNode() argument
765 getTargetNode(BlockAddressSDNode * N,SDLoc DL,EVT Ty,SelectionDAG & DAG,unsigned Flags) getTargetNode() argument
771 getTargetNode(ConstantPoolSDNode * N,SDLoc DL,EVT Ty,SelectionDAG & DAG,unsigned Flags) getTargetNode() argument
777 getTargetNode(JumpTableSDNode * N,SDLoc DL,EVT Ty,SelectionDAG & DAG,unsigned Flags) getTargetNode() argument
782 getAddr(NodeTy * N,SelectionDAG & DAG,CodeModel::Model M,bool IsLocal) const getAddr() argument
879 getStaticTLSAddr(GlobalAddressSDNode * N,SelectionDAG & DAG,unsigned Opc,bool UseGOT,bool Large) const getStaticTLSAddr() argument
910 getDynamicTLSAddr(GlobalAddressSDNode * N,SelectionDAG & DAG,unsigned Opc,bool Large) const getDynamicTLSAddr() argument
945 getTLSDescAddr(GlobalAddressSDNode * N,SelectionDAG & DAG,unsigned Opc,bool Large) const getTLSDescAddr() argument
1024 checkIntrinsicImmArg(SDValue Op,unsigned ImmOp,SelectionDAG & DAG,bool IsSigned=false) checkIntrinsicImmArg() argument
1319 emitIntrinsicWithChainErrorMessage(SDValue Op,StringRef ErrorMsg,SelectionDAG & DAG) emitIntrinsicWithChainErrorMessage() argument
1441 emitIntrinsicErrorMessage(SDValue Op,StringRef ErrorMsg,SelectionDAG & DAG) emitIntrinsicErrorMessage() argument
1653 lowerShiftRightParts(SDValue Op,SelectionDAG & DAG,bool IsSRA) const lowerShiftRightParts() argument
1736 customLegalizeToWOp(SDNode * N,SelectionDAG & DAG,int NumOp,unsigned ExtOpc=ISD::ANY_EXTEND) customLegalizeToWOp() argument
1770 customLegalizeToWOpWithSExt(SDNode * N,SelectionDAG & DAG) customLegalizeToWOpWithSExt() argument
1783 emitErrorAndReplaceIntrinsicResults(SDNode * N,SmallVectorImpl<SDValue> & Results,SelectionDAG & DAG,StringRef ErrorMsg,bool WithChain=true) emitErrorAndReplaceIntrinsicResults() argument
1795 replaceVPICKVE2GRResults(SDNode * Node,SmallVectorImpl<SDValue> & Results,SelectionDAG & DAG,const LoongArchSubtarget & Subtarget,unsigned ResOp) replaceVPICKVE2GRResults() argument
1817 replaceVecCondBranchResults(SDNode * N,SmallVectorImpl<SDValue> & Results,SelectionDAG & DAG,const LoongArchSubtarget & Subtarget,unsigned ResOp) replaceVecCondBranchResults() argument
1830 replaceINTRINSIC_WO_CHAINResults(SDNode * N,SmallVectorImpl<SDValue> & Results,SelectionDAG & DAG,const LoongArchSubtarget & Subtarget) replaceINTRINSIC_WO_CHAINResults() argument
2192 performANDCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const LoongArchSubtarget & Subtarget) performANDCombine() argument
2278 performSRLCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const LoongArchSubtarget & Subtarget) performSRLCombine() argument
2319 performORCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const LoongArchSubtarget & Subtarget) performORCombine() argument
2540 performBITREV_WCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const LoongArchSubtarget & Subtarget) performBITREV_WCombine() argument
2556 legalizeIntrinsicImmArg(SDNode * Node,unsigned ImmOp,SelectionDAG & DAG,const LoongArchSubtarget & Subtarget,bool IsSigned=false) legalizeIntrinsicImmArg() argument
2573 lowerVectorSplatImm(SDNode * Node,unsigned ImmOp,SelectionDAG & DAG,bool IsSigned=false) lowerVectorSplatImm() argument
2591 truncateVecElts(SDNode * Node,SelectionDAG & DAG) truncateVecElts() argument
2599 lowerVectorBitClear(SDNode * Node,SelectionDAG & DAG) lowerVectorBitClear() argument
2611 lowerVectorBitClearImm(SDNode * Node,SelectionDAG & DAG) lowerVectorBitClearImm() argument
2629 lowerVectorBitSetImm(SDNode * Node,SelectionDAG & DAG) lowerVectorBitSetImm() argument
2646 lowerVectorBitRevImm(SDNode * Node,SelectionDAG & DAG) lowerVectorBitRevImm() argument
2663 performINTRINSIC_WO_CHAINCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const LoongArchSubtarget & Subtarget) performINTRINSIC_WO_CHAINCombine() argument
3158 SelectionDAG &DAG = DCI.DAG; PerformDAGCombine() local
3824 convertLocVTToValVT(SelectionDAG & DAG,SDValue Val,const CCValAssign & VA,const SDLoc & DL) convertLocVTToValVT() argument
3842 unpackFromRegLoc(SelectionDAG & DAG,SDValue Chain,const CCValAssign & VA,const SDLoc & DL,const ISD::InputArg & In,const LoongArchTargetLowering & TLI) unpackFromRegLoc() argument
3875 unpackFromMemLoc(SelectionDAG & DAG,SDValue Chain,const CCValAssign & VA,const SDLoc & DL) unpackFromMemLoc() argument
3900 convertValVTToLocVT(SelectionDAG & DAG,SDValue Val,const CCValAssign & VA,const SDLoc & DL) convertValVTToLocVT() argument
3965 LowerFormalArguments(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & DL,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const LowerFormalArguments() argument
4171 getPrefTypeAlign(EVT VT,SelectionDAG & DAG) getPrefTypeAlign() argument
4181 SelectionDAG &DAG = CLI.DAG; LowerCall() local
[all...]
/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp420 LowerFormalArguments(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & DL,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const LowerFormalArguments() argument
434 LowerFormalArguments_32(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const LowerFormalArguments_32() argument
629 LowerFormalArguments_64(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & DL,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const LowerFormalArguments_64() argument
766 hasReturnsTwiceAttr(SelectionDAG & DAG,SDValue Callee,const CallBase * Call) hasReturnsTwiceAttr() argument
824 SelectionDAG &DAG = CLI.DAG; LowerCall_32() local
1226 SelectionDAG &DAG = CLI.DAG; LowerCall_64() local
2069 computeKnownBitsForTargetNode(const SDValue Op,KnownBits & Known,const APInt & DemandedElts,const SelectionDAG & DAG,unsigned Depth) const computeKnownBitsForTargetNode() argument
2352 LowerF128Op(SDValue Op,SelectionDAG & DAG,const char * LibFuncName,unsigned numArgs) const LowerF128Op() argument
2504 LowerF128_FPEXTEND(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI) LowerF128_FPEXTEND() argument
2520 LowerF128_FPROUND(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI) LowerF128_FPROUND() argument
2537 LowerFP_TO_SINT(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,bool hasHardQuad) LowerFP_TO_SINT() argument
2566 LowerSINT_TO_FP(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,bool hasHardQuad) LowerSINT_TO_FP() argument
2594 LowerFP_TO_UINT(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,bool hasHardQuad) LowerFP_TO_UINT() argument
2615 LowerUINT_TO_FP(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,bool hasHardQuad) LowerUINT_TO_FP() argument
2634 LowerBR_CC(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,bool hasHardQuad,bool isV9,bool is64Bit) LowerBR_CC() argument
2685 LowerSELECT_CC(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,bool hasHardQuad,bool isV9,bool is64Bit) LowerSELECT_CC() argument
2739 LowerVASTART(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI) LowerVASTART() argument
2759 LowerVAARG(SDValue Op,SelectionDAG & DAG) LowerVAARG() argument
2783 LowerDYNAMIC_STACKALLOC(SDValue Op,SelectionDAG & DAG,const SparcSubtarget * Subtarget) LowerDYNAMIC_STACKALLOC() argument
2848 getFLUSHW(SDValue Op,SelectionDAG & DAG) getFLUSHW() argument
2855 getFRAMEADDR(uint64_t depth,SDValue Op,SelectionDAG & DAG,const SparcSubtarget * Subtarget,bool AlwaysFlush=false) getFRAMEADDR() argument
2888 LowerFRAMEADDR(SDValue Op,SelectionDAG & DAG,const SparcSubtarget * Subtarget) LowerFRAMEADDR() argument
2897 LowerRETURNADDR(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,const SparcSubtarget * Subtarget) LowerRETURNADDR() argument
2932 LowerF64Op(SDValue SrcReg64,const SDLoc & dl,SelectionDAG & DAG,unsigned opcode) LowerF64Op() argument
2966 LowerF128Load(SDValue Op,SelectionDAG & DAG) LowerF128Load() argument
3007 LowerLOAD(SDValue Op,SelectionDAG & DAG) LowerLOAD() argument
3019 LowerF128Store(SDValue Op,SelectionDAG & DAG) LowerF128Store() argument
3055 LowerSTORE(SDValue Op,SelectionDAG & DAG) LowerSTORE() argument
3078 LowerFNEGorFABS(SDValue Op,SelectionDAG & DAG,bool isV9) LowerFNEGorFABS() argument
3121 LowerADDC_ADDE_SUBC_SUBE(SDValue Op,SelectionDAG & DAG) LowerADDC_ADDE_SUBC_SUBE() argument
3172 LowerUMULO_SMULO(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI) LowerUMULO_SMULO() argument
3225 LowerATOMIC_LOAD_STORE(SDValue Op,SelectionDAG & DAG) LowerATOMIC_LOAD_STORE() argument
[all...]

12345