Lines Matching defs:DAG
1 //=- LoongArchISelLowering.cpp - LoongArch DAG Lowering Implementation ---===//
10 // a selection DAG.
355 // Set DAG combine for LA32 and LA64.
362 // Set DAG combine for 'LSX' feature.
406 SelectionDAG &DAG) const {
409 return lowerATOMIC_FENCE(Op, DAG);
411 return lowerEH_DWARF_CFA(Op, DAG);
413 return lowerGlobalAddress(Op, DAG);
415 return lowerGlobalTLSAddress(Op, DAG);
417 return lowerINTRINSIC_WO_CHAIN(Op, DAG);
419 return lowerINTRINSIC_W_CHAIN(Op, DAG);
421 return lowerINTRINSIC_VOID(Op, DAG);
423 return lowerBlockAddress(Op, DAG);
425 return lowerJumpTable(Op, DAG);
427 return lowerShiftLeftParts(Op, DAG);
429 return lowerShiftRightParts(Op, DAG, true);
431 return lowerShiftRightParts(Op, DAG, false);
433 return lowerConstantPool(Op, DAG);
435 return lowerFP_TO_SINT(Op, DAG);
437 return lowerBITCAST(Op, DAG);
439 return lowerUINT_TO_FP(Op, DAG);
441 return lowerSINT_TO_FP(Op, DAG);
443 return lowerVASTART(Op, DAG);
445 return lowerFRAMEADDR(Op, DAG);
447 return lowerRETURNADDR(Op, DAG);
449 return lowerWRITE_REGISTER(Op, DAG);
451 return lowerINSERT_VECTOR_ELT(Op, DAG);
453 return lowerEXTRACT_VECTOR_ELT(Op, DAG);
455 return lowerBUILD_VECTOR(Op, DAG);
457 return lowerVECTOR_SHUFFLE(Op, DAG);
459 return lowerBITREVERSE(Op, DAG);
461 return lowerSCALAR_TO_VECTOR(Op, DAG);
468 SelectionDAG &DAG) const {
472 SDValue Vector = DAG.getUNDEF(OpVT);
474 SDValue Idx = DAG.getConstant(0, DL, Subtarget.getGRLenVT());
476 return DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, OpVT, Vector, Val, Idx);
480 SelectionDAG &DAG) const {
489 SDValue NewSrc = DAG.getNode(ISD::BITCAST, DL, NewVT, Src);
493 SDValue Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i64, NewSrc,
494 DAG.getConstant(i, DL, MVT::i64));
498 Ops.push_back(DAG.getNode(RevOp, DL, MVT::i64, Op));
501 DAG.getNode(ISD::BITCAST, DL, ResTy, DAG.getBuildVector(NewVT, DL, Ops));
517 return DAG.getVectorShuffle(ResTy, DL, Res, DAG.getUNDEF(ResTy), Mask);
556 SelectionDAG &DAG) {
566 return DAG.getUNDEF(VT);
571 return DAG.getNode(LoongArchISD::VREPLVEI, DL, VT, V1,
572 DAG.getConstant(Imm, DL, MVT::i64));
598 SelectionDAG &DAG) {
640 return DAG.getNode(LoongArchISD::VSHUF4I, DL, VT, V1,
641 DAG.getConstant(Imm, DL, MVT::i64));
661 SelectionDAG &DAG) {
681 return DAG.getNode(LoongArchISD::VPACKEV, DL, VT, V2, V1);
701 SelectionDAG &DAG) {
721 return DAG.getNode(LoongArchISD::VPACKOD, DL, VT, V2, V1);
742 SelectionDAG &DAG) {
764 return DAG.getNode(LoongArchISD::VILVH, DL, VT, V2, V1);
785 SelectionDAG &DAG) {
805 return DAG.getNode(LoongArchISD::VILVL, DL, VT, V2, V1);
825 SelectionDAG &DAG) {
847 return DAG.getNode(LoongArchISD::VPICKEV, DL, VT, V2, V1);
867 SelectionDAG &DAG) {
888 return DAG.getNode(LoongArchISD::VPICKOD, DL, VT, V2, V1);
897 SelectionDAG &DAG) {
901 Ops.push_back(DAG.getConstant(M, DL, MVT::i64));
904 SDValue MaskVec = DAG.getBuildVector(MaskVecTy, DL, Ops);
913 return DAG.getNode(LoongArchISD::VSHUF, DL, VT, MaskVec, V2, V1);
921 SDValue V1, SDValue V2, SelectionDAG &DAG) {
935 if ((Result = lowerVECTOR_SHUFFLE_VREPLVEI(DL, Mask, VT, V1, V2, DAG)))
937 if ((Result = lowerVECTOR_SHUFFLE_VSHUF4I(DL, Mask, VT, V1, V2, DAG)))
947 if ((Result = lowerVECTOR_SHUFFLE_VPACKEV(DL, Mask, VT, V1, V2, DAG)))
949 if ((Result = lowerVECTOR_SHUFFLE_VPACKOD(DL, Mask, VT, V1, V2, DAG)))
951 if ((Result = lowerVECTOR_SHUFFLE_VILVH(DL, Mask, VT, V1, V2, DAG)))
953 if ((Result = lowerVECTOR_SHUFFLE_VILVL(DL, Mask, VT, V1, V2, DAG)))
955 if ((Result = lowerVECTOR_SHUFFLE_VPICKEV(DL, Mask, VT, V1, V2, DAG)))
957 if ((Result = lowerVECTOR_SHUFFLE_VPICKOD(DL, Mask, VT, V1, V2, DAG)))
959 if ((Result = lowerVECTOR_SHUFFLE_VSHUF(DL, Mask, VT, V1, V2, DAG)))
976 SelectionDAG &DAG) {
986 return DAG.getUNDEF(VT);
997 return DAG.getNode(LoongArchISD::VREPLVEI, DL, VT, V1,
998 DAG.getConstant(Imm, DL, MVT::i64));
1007 SelectionDAG &DAG) {
1012 return lowerVECTOR_SHUFFLE_VSHUF4I(DL, Mask, VT, V1, V2, DAG);
1018 SelectionDAG &DAG) {
1019 return lowerVECTOR_SHUFFLE_VPACKEV(DL, Mask, VT, V1, V2, DAG);
1025 SelectionDAG &DAG) {
1026 return lowerVECTOR_SHUFFLE_VPACKOD(DL, Mask, VT, V1, V2, DAG);
1032 SelectionDAG &DAG) {
1065 return DAG.getNode(LoongArchISD::VILVH, DL, VT, V2, V1);
1071 SelectionDAG &DAG) {
1099 return DAG.getNode(LoongArchISD::VILVL, DL, VT, V2, V1);
1105 SelectionDAG &DAG) {
1134 return DAG.getNode(LoongArchISD::VPICKEV, DL, VT, V2, V1);
1140 SelectionDAG &DAG) {
1170 return DAG.getNode(LoongArchISD::VPICKOD, DL, VT, V2, V1);
1176 SelectionDAG &DAG) {
1196 MaskAlloc.push_back(DAG.getTargetConstant(0, DL, MVT::i64));
1200 MaskAlloc.push_back(DAG.getTargetConstant(M, DL, MVT::i64));
1208 MaskAlloc.push_back(DAG.getTargetConstant(0, DL, MVT::i64));
1212 MaskAlloc.push_back(DAG.getTargetConstant(M, DL, MVT::i64));
1219 SDValue MaskVec = DAG.getBuildVector(MaskVecTy, DL, MaskAlloc);
1220 return DAG.getNode(LoongArchISD::VSHUF, DL, VT, MaskVec, V2, V1);
1245 SelectionDAG &DAG) {
1286 V1 = DAG.getBitcast(MVT::v4i64, V1);
1287 V1 = DAG.getNode(LoongArchISD::XVPERMI, DL, MVT::v4i64, V1,
1288 DAG.getConstant(0b01001110, DL, MVT::i64));
1289 V1 = DAG.getBitcast(VT, V1);
1292 V2 = DAG.getBitcast(MVT::v4i64, V2);
1293 V2 = DAG.getNode(LoongArchISD::XVPERMI, DL, MVT::v4i64, V2,
1294 DAG.getConstant(0b01001110, DL, MVT::i64));
1295 V2 = DAG.getBitcast(VT, V2);
1305 V1 = DAG.getBitcast(MVT::v4i64, V1);
1306 V1 = DAG.getNode(LoongArchISD::XVPERMI, DL, MVT::v4i64, V1,
1307 DAG.getConstant(0b11101110, DL, MVT::i64));
1308 V1 = DAG.getBitcast(VT, V1);
1311 V2 = DAG.getBitcast(MVT::v4i64, V2);
1312 V2 = DAG.getNode(LoongArchISD::XVPERMI, DL, MVT::v4i64, V2,
1313 DAG.getConstant(0b11101110, DL, MVT::i64));
1314 V2 = DAG.getBitcast(VT, V2);
1321 V1 = DAG.getBitcast(MVT::v4i64, V1);
1322 V1 = DAG.getNode(LoongArchISD::XVPERMI, DL, MVT::v4i64, V1,
1323 DAG.getConstant(0b01000100, DL, MVT::i64));
1324 V1 = DAG.getBitcast(VT, V1);
1327 V2 = DAG.getBitcast(MVT::v4i64, V2);
1328 V2 = DAG.getNode(LoongArchISD::XVPERMI, DL, MVT::v4i64, V2,
1329 DAG.getConstant(0b01000100, DL, MVT::i64));
1330 V2 = DAG.getBitcast(VT, V2);
1346 SDValue V1, SDValue V2, SelectionDAG &DAG) {
1360 canonicalizeShuffleVectorByLane(DL, NewMask, VT, V1, V2, DAG);
1365 if ((Result = lowerVECTOR_SHUFFLE_XVREPLVEI(DL, NewMask, VT, V1, V2, DAG)))
1367 if ((Result = lowerVECTOR_SHUFFLE_XVSHUF4I(DL, NewMask, VT, V1, V2, DAG)))
1377 if ((Result = lowerVECTOR_SHUFFLE_XVPACKEV(DL, NewMask, VT, V1, V2, DAG)))
1379 if ((Result = lowerVECTOR_SHUFFLE_XVPACKOD(DL, NewMask, VT, V1, V2, DAG)))
1381 if ((Result = lowerVECTOR_SHUFFLE_XVILVH(DL, NewMask, VT, V1, V2, DAG)))
1383 if ((Result = lowerVECTOR_SHUFFLE_XVILVL(DL, NewMask, VT, V1, V2, DAG)))
1385 if ((Result = lowerVECTOR_SHUFFLE_XVPICKEV(DL, NewMask, VT, V1, V2, DAG)))
1387 if ((Result = lowerVECTOR_SHUFFLE_XVPICKOD(DL, NewMask, VT, V1, V2, DAG)))
1389 if ((Result = lowerVECTOR_SHUFFLE_XVSHUF(DL, NewMask, VT, V1, V2, DAG)))
1396 SelectionDAG &DAG) const {
1408 return DAG.getUNDEF(VT);
1414 return DAG.getCommutedVectorShuffle(*SVOp);
1425 return DAG.getVectorShuffle(VT, DL, V1, V2, NewMask);
1437 return lower128BitShuffle(DL, OrigMask, VT, V1, V2, DAG);
1440 return lower256BitShuffle(DL, OrigMask, VT, V1, V2, DAG);
1463 SelectionDAG &DAG) const {
1505 SDValue Result = DAG.getConstant(SplatValue, DL, ViaVecTy);
1509 Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result);
1514 if (DAG.isSplatValue(Op, /*AllowUndefs=*/false))
1526 SDValue Vector = DAG.getUNDEF(ResTy);
1528 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
1530 DAG.getConstant(i, DL, Subtarget.getGRLenVT()));
1540 SelectionDAG &DAG) const {
1556 SelectionDAG &DAG) const {
1563 SelectionDAG &DAG) const {
1573 return DAG.getNode(ISD::MEMBARRIER, DL, MVT::Other, Op.getOperand(0));
1579 SelectionDAG &DAG) const {
1582 DAG.getContext()->emitError(
1588 DAG.getContext()->emitError(
1597 SelectionDAG &DAG) const {
1599 DAG.getContext()->emitError("argument to '__builtin_frame_address' must "
1604 MachineFunction &MF = DAG.getMachineFunction();
1609 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, FrameReg, VT);
1615 SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
1616 DAG.getSignedConstant(Offset, DL, VT));
1618 DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
1624 SelectionDAG &DAG) const {
1625 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
1630 DAG.getContext()->emitError(
1635 MachineFunction &MF = DAG.getMachineFunction();
1643 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, GRLenVT);
1647 SelectionDAG &DAG) const {
1648 MachineFunction &MF = DAG.getMachineFunction();
1651 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
1655 SelectionDAG &DAG) const {
1656 MachineFunction &MF = DAG.getMachineFunction();
1660 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1666 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
1671 SelectionDAG &DAG) const {
1700 makeLibCall(DAG, LC, Op.getValueType(), Op0, CallOptions, DL, Chain);
1705 SelectionDAG &DAG) const {
1725 makeLibCall(DAG, LC, Op.getValueType(), Op0, CallOptions, DL, Chain);
1730 SelectionDAG &DAG) const {
1737 SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
1738 return DAG.getNode(LoongArchISD::MOVGR2FR_W_LA64, DL, MVT::f32, NewOp0);
1744 SelectionDAG &DAG) const {
1750 Op0 = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Op0);
1754 SDValue Dst = DAG.getNode(LoongArchISD::FTINT, DL, MVT::f32, Op0);
1755 return DAG.getNode(LoongArchISD::MOVFR2GR_S_LA64, DL, MVT::i64, Dst);
1759 SDValue Trunc = DAG.getNode(LoongArchISD::FTINT, DL, FPTy, Op0);
1760 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Trunc);
1764 SelectionDAG &DAG, unsigned Flags) {
1765 return DAG.getTargetGlobalAddress(N->getGlobal(), DL, Ty, 0, Flags);
1769 SelectionDAG &DAG, unsigned Flags) {
1770 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, N->getOffset(),
1775 SelectionDAG &DAG, unsigned Flags) {
1776 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlign(),
1781 SelectionDAG &DAG, unsigned Flags) {
1782 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flags);
1786 SDValue LoongArchTargetLowering::getAddr(NodeTy *N, SelectionDAG &DAG,
1790 EVT Ty = getPointerTy(DAG.getDataLayout());
1791 SDValue Addr = getTargetNode(N, DL, Ty, DAG, 0);
1803 SDValue Tmp = DAG.getConstant(0, DL, Ty);
1807 Load = SDValue(DAG.getMachineNode(LoongArch::PseudoLA_PCREL_LARGE, DL, Ty,
1814 DAG.getMachineNode(LoongArch::PseudoLA_GOT_LARGE, DL, Ty, Tmp, Addr),
1826 DAG.getMachineNode(LoongArch::PseudoLA_PCREL, DL, Ty, Addr), 0);
1831 SDValue(DAG.getMachineNode(LoongArch::PseudoLA_GOT, DL, Ty, Addr), 0);
1837 MachineFunction &MF = DAG.getMachineFunction();
1843 DAG.setNodeMemRefs(cast<MachineSDNode>(Load.getNode()), {MemOp});
1850 SelectionDAG &DAG) const {
1851 return getAddr(cast<BlockAddressSDNode>(Op), DAG,
1852 DAG.getTarget().getCodeModel());
1856 SelectionDAG &DAG) const {
1857 return getAddr(cast<JumpTableSDNode>(Op), DAG,
1858 DAG.getTarget().getCodeModel());
1862 SelectionDAG &DAG) const {
1863 return getAddr(cast<ConstantPoolSDNode>(Op), DAG,
1864 DAG.getTarget().getCodeModel());
1868 SelectionDAG &DAG) const {
1871 auto CM = DAG.getTarget().getCodeModel();
1879 return getAddr(N, DAG, CM, GV->isDSOLocal());
1883 SelectionDAG &DAG,
1887 EVT Ty = getPointerTy(DAG.getDataLayout());
1892 SDValue Tmp = DAG.getConstant(0, DL, Ty);
1893 SDValue Addr = DAG.getTargetGlobalAddress(N->getGlobal(), DL, Ty, 0, 0);
1897 ? SDValue(DAG.getMachineNode(Opc, DL, Ty, Tmp, Addr), 0)
1898 : SDValue(DAG.getMachineNode(Opc, DL, Ty, Addr), 0);
1907 MachineFunction &MF = DAG.getMachineFunction();
1913 DAG.setNodeMemRefs(cast<MachineSDNode>(Offset.getNode()), {MemOp});
1917 return DAG.getNode(ISD::ADD, DL, Ty, Offset,
1918 DAG.getRegister(LoongArch::R2, GRLenVT));
1922 SelectionDAG &DAG,
1926 EVT Ty = getPointerTy(DAG.getDataLayout());
1927 IntegerType *CallTy = Type::getIntNTy(*DAG.getContext(), Ty.getSizeInBits());
1931 SDValue Tmp = DAG.getConstant(0, DL, Ty);
1934 SDValue Addr = DAG.getTargetGlobalAddress(N->getGlobal(), DL, Ty, 0, 0);
1935 SDValue Load = Large ? SDValue(DAG.getMachineNode(Opc, DL, Ty, Tmp, Addr), 0)
1936 : SDValue(DAG.getMachineNode(Opc, DL, Ty, Addr), 0);
1946 TargetLowering::CallLoweringInfo CLI(DAG);
1948 .setChain(DAG.getEntryNode())
1950 DAG.getExternalSymbol("__tls_get_addr", Ty),
1957 SelectionDAG &DAG, unsigned Opc,
1960 EVT Ty = getPointerTy(DAG.getDataLayout());
1965 SDValue Tmp = DAG.getConstant(0, DL, Ty);
1969 SDValue Addr = DAG.getTargetGlobalAddress(GV, DL, Ty, 0, 0);
1970 return Large ? SDValue(DAG.getMachineNode(Opc, DL, Ty, Tmp, Addr), 0)
1971 : SDValue(DAG.getMachineNode(Opc, DL, Ty, Addr), 0);
1976 SelectionDAG &DAG) const {
1977 if (DAG.getMachineFunction().getFunction().getCallingConv() ==
1981 bool Large = DAG.getTarget().getCodeModel() == CodeModel::Large;
1987 if (DAG.getTarget().useEmulatedTLS())
1991 bool IsDesc = DAG.getTarget().useTLSDESC();
1999 return getDynamicTLSAddr(N, DAG,
2008 return getDynamicTLSAddr(N, DAG,
2015 return getStaticTLSAddr(N, DAG,
2024 return getStaticTLSAddr(N, DAG, LoongArch::PseudoLA_TLS_LE,
2028 return getTLSDescAddr(N, DAG,
2036 SelectionDAG &DAG, bool IsSigned = false) {
2041 DAG.getContext()->emitError(Op->getOperationName(0) +
2043 return DAG.getNode(ISD::UNDEF, SDLoc(Op), Op.getValueType());
2050 SelectionDAG &DAG) const {
2056 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2057 return DAG.getRegister(LoongArch::R2, PtrVT);
2063 return checkIntrinsicImmArg<1>(Op, 2, DAG);
2070 return checkIntrinsicImmArg<2>(Op, 2, DAG);
2072 return checkIntrinsicImmArg<2>(Op, 3, DAG);
2091 return checkIntrinsicImmArg<3>(Op, 2, DAG);
2093 return checkIntrinsicImmArg<3>(Op, 3, DAG);
2110 return checkIntrinsicImmArg<4>(Op, 2, DAG);
2135 return checkIntrinsicImmArg<4>(Op, 3, DAG);
2170 return checkIntrinsicImmArg<5>(Op, 2, DAG);
2195 return checkIntrinsicImmArg<5>(Op, 2, DAG, /*IsSigned=*/true);
2224 return checkIntrinsicImmArg<5>(Op, 3, DAG);
2235 return checkIntrinsicImmArg<6>(Op, 2, DAG);
2260 return checkIntrinsicImmArg<6>(Op, 3, DAG);
2285 return checkIntrinsicImmArg<7>(Op, 3, DAG);
2295 return checkIntrinsicImmArg<8>(Op, 2, DAG);
2311 return checkIntrinsicImmArg<8>(Op, 3, DAG);
2320 return checkIntrinsicImmArg<10>(Op, 1, DAG, /*IsSigned=*/true);
2323 return checkIntrinsicImmArg<13>(Op, 1, DAG, /*IsSigned=*/true);
2331 SelectionDAG &DAG) {
2332 DAG.getContext()->emitError(Op->getOperationName(0) + ": " + ErrorMsg + ".");
2333 return DAG.getMergeValues({DAG.getUNDEF(Op.getValueType()), Op.getOperand(0)},
2339 SelectionDAG &DAG) const {
2359 return emitIntrinsicWithChainErrorMessage(Op, ErrorMsgReqLA64, DAG);
2364 ? emitIntrinsicWithChainErrorMessage(Op, ErrorMsgOOR, DAG)
2365 : DAG.getNode(LoongArchISD::CSRRD, DL, {GRLenVT, MVT::Other},
2366 {Chain, DAG.getConstant(Imm, DL, GRLenVT)});
2372 ? emitIntrinsicWithChainErrorMessage(Op, ErrorMsgOOR, DAG)
2373 : DAG.getNode(LoongArchISD::CSRWR, DL, {GRLenVT, MVT::Other},
2375 DAG.getConstant(Imm, DL, GRLenVT)});
2381 ? emitIntrinsicWithChainErrorMessage(Op, ErrorMsgOOR, DAG)
2382 : DAG.getNode(LoongArchISD::CSRXCHG, DL, {GRLenVT, MVT::Other},
2384 DAG.getConstant(Imm, DL, GRLenVT)});
2387 return DAG.getNode(
2389 {Chain, DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op.getOperand(2))});
2393 return DAG.getNode(LoongArchISD::NODE, DL, {GRLenVT, MVT::Other}, \
2401 return DAG.getNode(LoongArchISD::CPUCFG, DL, {GRLenVT, MVT::Other},
2407 ? emitIntrinsicWithChainErrorMessage(Op, ErrorMsgOOR, DAG)
2412 return emitIntrinsicWithChainErrorMessage(Op, ErrorMsgReqF, DAG);
2415 ? emitIntrinsicWithChainErrorMessage(Op, ErrorMsgOOR, DAG)
2416 : DAG.getNode(LoongArchISD::MOVFCSR2GR, DL, {VT, MVT::Other},
2417 {Chain, DAG.getConstant(Imm, DL, GRLenVT)});
2424 ? emitIntrinsicWithChainErrorMessage(Op, ErrorMsgOOR, DAG)
2431 Op, "argument out of range or not a multiple of 2", DAG)
2438 Op, "argument out of range or not a multiple of 4", DAG)
2445 Op, "argument out of range or not a multiple of 8", DAG)
2453 SelectionDAG &DAG) {
2455 DAG.getContext()->emitError(Op->getOperationName(0) + ": " + ErrorMsg + ".");
2460 SelectionDAG &DAG) const {
2478 return emitIntrinsicErrorMessage(Op, ErrorMsgReqLA64, DAG);
2480 return emitIntrinsicErrorMessage(Op, ErrorMsgReqLA32, DAG);
2485 return emitIntrinsicErrorMessage(Op, ErrorMsgOOR, DAG);
2491 ? emitIntrinsicErrorMessage(Op, ErrorMsgOOR, DAG)
2492 : DAG.getNode(LoongArchISD::DBAR, DL, MVT::Other, Chain,
2493 DAG.getConstant(Imm, DL, GRLenVT));
2498 ? emitIntrinsicErrorMessage(Op, ErrorMsgOOR, DAG)
2499 : DAG.getNode(LoongArchISD::IBAR, DL, MVT::Other, Chain,
2500 DAG.getConstant(Imm, DL, GRLenVT));
2505 ? emitIntrinsicErrorMessage(Op, ErrorMsgOOR, DAG)
2506 : DAG.getNode(LoongArchISD::BREAK, DL, MVT::Other, Chain,
2507 DAG.getConstant(Imm, DL, GRLenVT));
2511 return emitIntrinsicErrorMessage(Op, ErrorMsgReqF, DAG);
2514 ? emitIntrinsicErrorMessage(Op, ErrorMsgOOR, DAG)
2515 : DAG.getNode(LoongArchISD::MOVGR2FCSR, DL, MVT::Other, Chain,
2516 DAG.getConstant(Imm, DL, GRLenVT),
2517 DAG.getNode(ISD::ANY_EXTEND, DL, GRLenVT,
2523 ? emitIntrinsicErrorMessage(Op, ErrorMsgOOR, DAG)
2524 : DAG.getNode(LoongArchISD::SYSCALL, DL, MVT::Other, Chain,
2525 DAG.getConstant(Imm, DL, GRLenVT));
2531 ? DAG.getNode(LoongArchISD::NODE, DL, MVT::Other, Chain, \
2532 DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2), \
2533 DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op3)) \
2534 : DAG.getNode(LoongArchISD::NODE, DL, MVT::Other, Chain, Op2, \
2543 ? emitIntrinsicErrorMessage(Op, ErrorMsgReqLA64, DAG)
2544 : DAG.getNode(LoongArchISD::IOCSRWR_D, DL, MVT::Other, Chain,
2546 DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64,
2552 ? emitIntrinsicErrorMessage(Op, ErrorMsgReqLA64, DAG) \
2561 ? emitIntrinsicErrorMessage(Op, ErrorMsgReqLA64, DAG)
2562 : !isUInt<8>(Imm) ? emitIntrinsicErrorMessage(Op, ErrorMsgOOR, DAG)
2568 ? emitIntrinsicErrorMessage(Op, ErrorMsgOOR, DAG)
2573 ? emitIntrinsicErrorMessage(Op, ErrorMsgOOR, DAG)
2578 ? emitIntrinsicErrorMessage(Op, ErrorMsgOOR, DAG)
2585 Op, "argument out of range or not a multiple of 2", DAG)
2592 Op, "argument out of range or not a multiple of 2", DAG)
2599 Op, "argument out of range or not a multiple of 4", DAG)
2606 Op, "argument out of range or not a multiple of 4", DAG)
2613 Op, "argument out of range or not a multiple of 8", DAG)
2620 Op, "argument out of range or not a multiple of 8", DAG)
2626 SelectionDAG &DAG) const {
2640 SDValue Zero = DAG.getConstant(0, DL, VT);
2641 SDValue One = DAG.getConstant(1, DL, VT);
2643 DAG.getSignedConstant(-(int)Subtarget.getGRLen(), DL, VT);
2644 SDValue GRLenMinus1 = DAG.getConstant(Subtarget.getGRLen() - 1, DL, VT);
2645 SDValue ShamtMinusGRLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusGRLen);
2646 SDValue GRLenMinus1Shamt = DAG.getNode(ISD::XOR, DL, VT, Shamt, GRLenMinus1);
2648 SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
2649 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, One);
2651 DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, GRLenMinus1Shamt);
2652 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
2653 SDValue HiTrue = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2654 SDValue HiFalse = DAG.getNode(ISD::SHL, DL, VT, Lo, ShamtMinusGRLen);
2656 SDValue CC = DAG.getSetCC(DL, VT, ShamtMinusGRLen, Zero, ISD::SETLT);
2658 Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, Zero);
2659 Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);
2662 return DAG.getMergeValues(Parts, DL);
2666 SelectionDAG &DAG,
2692 SDValue Zero = DAG.getConstant(0, DL, VT);
2693 SDValue One = DAG.getConstant(1, DL, VT);
2695 DAG.getSignedConstant(-(int)Subtarget.getGRLen(), DL, VT);
2696 SDValue GRLenMinus1 = DAG.getConstant(Subtarget.getGRLen() - 1, DL, VT);
2697 SDValue ShamtMinusGRLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusGRLen);
2698 SDValue GRLenMinus1Shamt = DAG.getNode(ISD::XOR, DL, VT, Shamt, GRLenMinus1);
2700 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
2701 SDValue ShiftLeftHi1 = DAG.getNode(ISD::SHL, DL, VT, Hi, One);
2703 DAG.getNode(ISD::SHL, DL, VT, ShiftLeftHi1, GRLenMinus1Shamt);
2704 SDValue LoTrue = DAG.getNode(ISD::OR, DL, VT, ShiftRightLo, ShiftLeftHi);
2705 SDValue HiTrue = DAG.getNode(ShiftRightOp, DL, VT, Hi, Shamt);
2706 SDValue LoFalse = DAG.getNode(ShiftRightOp, DL, VT, Hi, ShamtMinusGRLen);
2708 IsSRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, GRLenMinus1) : Zero;
2710 SDValue CC = DAG.getSetCC(DL, VT, ShamtMinusGRLen, Zero, ISD::SETLT);
2712 Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, LoFalse);
2713 Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);
2716 return DAG.getMergeValues(Parts, DL);
2754 static SDValue customLegalizeToWOp(SDNode *N, SelectionDAG &DAG, int NumOp,
2764 NewOp0 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(0));
2765 NewRes = DAG.getNode(WOpcode, DL, MVT::i64, NewOp0);
2769 NewOp0 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(0));
2770 SDValue NewOp1 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(1));
2772 SDValue TmpOp = DAG.getConstant(32, DL, MVT::i64);
2773 NewOp1 = DAG.getNode(ISD::SUB, DL, MVT::i64, TmpOp, NewOp1);
2775 NewRes = DAG.getNode(WOpcode, DL, MVT::i64, NewOp0, NewOp1);
2783 return DAG.getNode(ISD::TRUNCATE, DL, N->getValueType(0), NewRes);
2788 static SDValue customLegalizeToWOpWithSExt(SDNode *N, SelectionDAG &DAG) {
2790 SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0));
2791 SDValue NewOp1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
2792 SDValue NewWOp = DAG.getNode(N->getOpcode(), DL, MVT::i64, NewOp0, NewOp1);
2793 SDValue NewRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i64, NewWOp,
2794 DAG.getValueType(MVT::i32));
2795 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, NewRes);
2801 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG,
2803 DAG.getContext()->emitError(N->getOperationName(0) + ": " + ErrorMsg + ".");
2804 Results.push_back(DAG.getUNDEF(N->getValueType(0)));
2813 SelectionDAG &DAG, const LoongArchSubtarget &Subtarget,
2818 emitErrorAndReplaceIntrinsicResults(Node, Results, DAG, ErrorMsgOOR,
2826 DAG.getNode(ResOp, DL, Subtarget.getGRLenVT(), Vec,
2827 DAG.getConstant(Imm, DL, Subtarget.getGRLenVT()),
2828 DAG.getValueType(Vec.getValueType().getVectorElementType()));
2829 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, Node->getValueType(0),
2835 SelectionDAG &DAG,
2841 SDValue CB = DAG.getNode(ResOp, DL, Subtarget.getGRLenVT(), Vec);
2843 DAG.getNode(ISD::TRUNCATE, DL, N->getValueType(0), CB.getValue(0)));
2848 SelectionDAG &DAG,
2854 replaceVPICKVE2GRResults<4>(N, Results, DAG, Subtarget,
2859 replaceVPICKVE2GRResults<3>(N, Results, DAG, Subtarget,
2863 replaceVPICKVE2GRResults<2>(N, Results, DAG, Subtarget,
2867 replaceVPICKVE2GRResults<4>(N, Results, DAG, Subtarget,
2872 replaceVPICKVE2GRResults<3>(N, Results, DAG, Subtarget,
2876 replaceVPICKVE2GRResults<2>(N, Results, DAG, Subtarget,
2887 replaceVecCondBranchResults(N, Results, DAG, Subtarget,
2892 replaceVecCondBranchResults(N, Results, DAG, Subtarget,
2903 replaceVecCondBranchResults(N, Results, DAG, Subtarget,
2908 replaceVecCondBranchResults(N, Results, DAG, Subtarget,
2916 SelectionDAG &DAG) {
2937 auto CmpVal = DAG.SplitScalar(N->getOperand(2), DL, MVT::i64, MVT::i64);
2938 auto NewVal = DAG.SplitScalar(N->getOperand(3), DL, MVT::i64, MVT::i64);
2942 SDNode *CmpSwap = DAG.getMachineNode(
2943 Opcode, SDLoc(N), DAG.getVTList(MVT::i64, MVT::i64, MVT::i64, MVT::Other),
2945 DAG.setNodeMemRefs(cast<MachineSDNode>(CmpSwap), {MemOp});
2946 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i128,
2952 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
2962 Results.push_back(customLegalizeToWOpWithSExt(N, DAG));
2970 Results.push_back(customLegalizeToWOp(N, DAG, 2,
2981 Results.push_back(customLegalizeToWOp(N, DAG, 2));
2989 Results.push_back(customLegalizeToWOp(N, DAG, 2));
2996 if (getTypeAction(*DAG.getContext(), Src.getValueType()) !=
2999 Src = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Src);
3000 SDValue Dst = DAG.getNode(LoongArchISD::FTINT, DL, FVT, Src);
3001 Results.push_back(DAG.getNode(ISD::BITCAST, DL, VT, Dst));
3014 makeLibCall(DAG, LC, VT, Src, CallOptions, DL, Chain);
3024 DAG.getNode(LoongArchISD::MOVFR2GR_S_LA64, DL, MVT::i64, Src);
3025 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Dst));
3032 auto &TLI = DAG.getTargetLoweringInfo();
3034 TLI.expandFP_TO_UINT(N, Tmp1, Tmp2, DAG);
3035 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Tmp1));
3043 SDValue NewSrc = DAG.getNode(ISD::ANY_EXTEND, DL, GRLenVT, Src);
3049 Tmp = DAG.getNode(LoongArchISD::REVB_2H, DL, GRLenVT, NewSrc);
3054 Tmp = DAG.getNode(LoongArchISD::REVB_2W, DL, GRLenVT, NewSrc);
3057 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, Tmp));
3065 SDValue NewSrc = DAG.getNode(ISD::ANY_EXTEND, DL, GRLenVT, Src);
3071 Tmp = DAG.getNode(LoongArchISD::BITREV_4B, DL, GRLenVT, NewSrc);
3074 Tmp = DAG.getNode(LoongArchISD::BITREV_W, DL, GRLenVT, NewSrc);
3077 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, Tmp));
3084 Results.push_back(customLegalizeToWOp(N, DAG, 1));
3100 emitErrorAndReplaceIntrinsicResults(N, Results, DAG, ErrorMsgReqF);
3105 emitErrorAndReplaceIntrinsicResults(N, Results, DAG, ErrorMsgOOR);
3108 SDValue MOVFCSR2GRResults = DAG.getNode(
3110 {Chain, DAG.getConstant(Imm, DL, GRLenVT)});
3112 DAG.getNode(ISD::TRUNCATE, DL, VT, MOVFCSR2GRResults.getValue(0)));
3118 SDValue NODE = DAG.getNode( \
3120 {Chain, DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2), \
3121 DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(3))}); \
3122 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, NODE.getValue(0))); \
3136 SDValue NODE = DAG.getNode( \
3139 DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(3))}); \
3140 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, NODE.getValue(0))); \
3150 emitErrorAndReplaceIntrinsicResults(N, Results, DAG, ErrorMsgReqLA64); \
3161 emitErrorAndReplaceIntrinsicResults(N, Results, DAG, ErrorMsgOOR);
3165 DAG.getNode(LoongArchISD::CSRRD, DL, {GRLenVT, MVT::Other},
3166 {Chain, DAG.getConstant(Imm, DL, GRLenVT)});
3168 DAG.getNode(ISD::TRUNCATE, DL, VT, CSRRDResults.getValue(0)));
3175 emitErrorAndReplaceIntrinsicResults(N, Results, DAG, ErrorMsgOOR);
3179 DAG.getNode(LoongArchISD::CSRWR, DL, {GRLenVT, MVT::Other},
3180 {Chain, DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2),
3181 DAG.getConstant(Imm, DL, GRLenVT)});
3183 DAG.getNode(ISD::TRUNCATE, DL, VT, CSRWRResults.getValue(0)));
3190 emitErrorAndReplaceIntrinsicResults(N, Results, DAG, ErrorMsgOOR);
3193 SDValue CSRXCHGResults = DAG.getNode(
3195 {Chain, DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2),
3196 DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(3)),
3197 DAG.getConstant(Imm, DL, GRLenVT)});
3199 DAG.getNode(ISD::TRUNCATE, DL, VT, CSRXCHGResults.getValue(0)));
3206 DAG.getNode(LoongArchISD::NODE, DL, {MVT::i64, MVT::Other}, \
3207 {Chain, DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2)}); \
3209 DAG.getNode(ISD::TRUNCATE, DL, VT, IOCSRRDResults.getValue(0))); \
3219 DAG.getNode(LoongArchISD::CPUCFG, DL, {GRLenVT, MVT::Other},
3220 {Chain, DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2)});
3222 DAG.getNode(ISD::TRUNCATE, DL, VT, CPUCFGResults.getValue(0)));
3228 emitErrorAndReplaceIntrinsicResults(N, Results, DAG, ErrorMsgReqLA64);
3238 DAG.getContext()->emitError(
3241 DAG.getContext()->emitError(
3243 Results.push_back(DAG.getUNDEF(VT));
3248 replaceINTRINSIC_WO_CHAINResults(N, Results, DAG, Subtarget);
3258 SDValue Result = makeLibCall(DAG, LC, MVT::i64, Op0, CallOptions, DL).first;
3259 Result = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Result);
3264 replaceCMP_XCHG_128Results(N, Results, DAG);
3270 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
3344 SDValue NR0 = DAG.getNode(LoongArchISD::BSTRPICK, DL, ValTy, NewOperand,
3345 DAG.getConstant(msb, DL, GRLenVT),
3346 DAG.getConstant(lsb, DL, GRLenVT));
3352 return DAG.getNode(ISD::SHL, DL, ValTy, NR0,
3353 DAG.getConstant(lsb, DL, GRLenVT));
3356 static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
3389 return DAG.getNode(LoongArchISD::BSTRPICK, DL, ValTy,
3391 DAG.getConstant(MaskIdx + MaskLen - 1, DL, GRLenVT),
3392 DAG.getConstant(Shamt, DL, GRLenVT));
3397 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
3433 return DAG.getNode(LoongArchISD::BSTRINS, DL, ValTy, N0.getOperand(0),
3435 DAG.getConstant((MaskIdx0 + MaskLen0 - 1), DL, GRLenVT),
3436 DAG.getConstant(MaskIdx0, DL, GRLenVT));
3455 return DAG.getNode(LoongArchISD::BSTRINS, DL, ValTy, N0.getOperand(0),
3457 DAG.getConstant((MaskIdx0 + MaskLen0 - 1), DL, GRLenVT),
3458 DAG.getConstant(MaskIdx0, DL, GRLenVT));
3474 return DAG.getNode(LoongArchISD::BSTRINS, DL, ValTy, N0.getOperand(0),
3475 DAG.getNode(ISD::SRL, DL, N1->getValueType(0), N1,
3476 DAG.getConstant(MaskIdx0, DL, GRLenVT)),
3477 DAG.getConstant(ValBits == 32
3481 DAG.getConstant(MaskIdx0, DL, GRLenVT));
3497 return DAG.getNode(LoongArchISD::BSTRINS, DL, ValTy, N0.getOperand(0),
3499 DAG.getConstant((ValBits - 1), DL, GRLenVT),
3500 DAG.getConstant(Shamt, DL, GRLenVT));
3515 return DAG.getNode(
3517 DAG.getConstant(CN1->getSExtValue() >> MaskIdx0, DL, ValTy),
3518 DAG.getConstant(ValBits == 32 ? (MaskIdx0 + (MaskLen0 & 31) - 1)
3521 DAG.getConstant(MaskIdx0, DL, GRLenVT));
3542 if (ShMask.isSubsetOf(DAG.computeKnownBits(N0).Zero)) {
3544 return DAG.getNode(LoongArchISD::BSTRINS, DL, ValTy, N0,
3546 DAG.getConstant(Shamt + MaskLen - 1, DL, GRLenVT),
3547 DAG.getConstant(Shamt, DL, GRLenVT));
3566 if (ShMask.isSubsetOf(DAG.computeKnownBits(N0).Zero)) {
3568 return DAG.getNode(LoongArchISD::BSTRINS, DL, ValTy, N0,
3570 DAG.getConstant(MaskIdx + MaskLen - 1, DL, GRLenVT),
3571 DAG.getConstant(MaskIdx, DL, GRLenVT));
3597 if (ShMask.isSubsetOf(DAG.computeKnownBits(N0).Zero)) {
3599 return DAG.getNode(LoongArchISD::BSTRINS, DL, ValTy, N0,
3600 DAG.getNode(ISD::SRL, DL, N1->getValueType(0),
3602 DAG.getConstant(MaskIdx, DL, GRLenVT)),
3603 DAG.getConstant(MaskIdx + MaskLen - 1, DL, GRLenVT),
3604 DAG.getConstant(MaskIdx, DL, GRLenVT));
3712 static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG,
3772 SDValue NewAnd = DAG.getNode(ISD::AND, SDLoc(N), AndNode->getValueType(0),
3775 DAG.getSetCC(SDLoc(N), N->getValueType(0), NewAnd, TruncInputValue2, CC);
3776 DAG.ReplaceAllUsesWith(N, NewSetCC.getNode());
3781 static SDValue performBITREV_WCombine(SDNode *N, SelectionDAG &DAG,
3791 return DAG.getNode(LoongArchISD::BITREV_4B, SDLoc(N), N->getValueType(0),
3797 SelectionDAG &DAG,
3805 DAG.getContext()->emitError(Node->getOperationName(0) +
3807 return DAG.getNode(ISD::UNDEF, DL, Subtarget.getGRLenVT());
3809 return DAG.getConstant(CImm->getZExtValue(), DL, Subtarget.getGRLenVT());
3814 SelectionDAG &DAG, bool IsSigned = false) {
3822 DAG.getContext()->emitError(Node->getOperationName(0) +
3824 return DAG.getNode(ISD::UNDEF, DL, ResTy);
3826 return DAG.getConstant(
3832 static SDValue truncateVecElts(SDNode *Node, SelectionDAG &DAG) {
3836 SDValue Mask = DAG.getConstant(Vec.getScalarValueSizeInBits() - 1, DL, ResTy);
3837 return DAG.getNode(ISD::AND, DL, ResTy, Vec, Mask);
3840 static SDValue lowerVectorBitClear(SDNode *Node, SelectionDAG &DAG) {
3843 SDValue One = DAG.getConstant(1, DL, ResTy);
3845 DAG.getNode(ISD::SHL, DL, ResTy, One, truncateVecElts(Node, DAG));
3847 return DAG.getNode(ISD::AND, DL, ResTy, Node->getOperand(1),
3848 DAG.getNOT(DL, Bit, ResTy));
3852 static SDValue lowerVectorBitClearImm(SDNode *Node, SelectionDAG &DAG) {
3858 DAG.getContext()->emitError(Node->getOperationName(0) +
3860 return DAG.getNode(ISD::UNDEF, DL, ResTy);
3864 SDValue Mask = DAG.getConstant(~BitImm, DL, ResTy);
3866 return DAG.getNode(ISD::AND, DL, ResTy, Node->getOperand(1), Mask);
3870 static SDValue lowerVectorBitSetImm(SDNode *Node, SelectionDAG &DAG) {
3876 DAG.getContext()->emitError(Node->getOperationName(0) +
3878 return DAG.getNode(ISD::UNDEF, DL, ResTy);
3882 SDValue BitImm = DAG.getConstant(Imm, DL, ResTy);
3883 return DAG.getNode(ISD::OR, DL, ResTy, Node->getOperand(1), BitImm);
3887 static SDValue lowerVectorBitRevImm(SDNode *Node, SelectionDAG &DAG) {
3893 DAG.getContext()->emitError(Node->getOperationName(0) +
3895 return DAG.getNode(ISD::UNDEF, DL, ResTy);
3899 SDValue BitImm = DAG.getConstant(Imm, DL, ResTy);
3900 return DAG.getNode(ISD::XOR, DL, ResTy, Node->getOperand(1), BitImm);
3904 performINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
3919 return DAG.getNode(ISD::ADD, DL, N->getValueType(0), N->getOperand(1),
3929 return DAG.getNode(ISD::ADD, DL, N->getValueType(0), N->getOperand(1),
3930 lowerVectorSplatImm<5>(N, 2, DAG));
3939 return DAG.getNode(ISD::SUB, DL, N->getValueType(0), N->getOperand(1),
3949 return DAG.getNode(ISD::SUB, DL, N->getValueType(0), N->getOperand(1),
3950 lowerVectorSplatImm<5>(N, 2, DAG));
3959 return DAG.getNode(
3961 DAG.getConstant(
3974 return DAG.getNode(ISD::SMAX, DL, N->getValueType(0), N->getOperand(1),
3984 return DAG.getNode(ISD::UMAX, DL, N->getValueType(0), N->getOperand(1),
3994 return DAG.getNode(ISD::SMAX, DL, N->getValueType(0), N->getOperand(1),
3995 lowerVectorSplatImm<5>(N, 2, DAG, /*IsSigned=*/true));
4004 return DAG.getNode(ISD::UMAX, DL, N->getValueType(0), N->getOperand(1),
4005 lowerVectorSplatImm<5>(N, 2, DAG));
4014 return DAG.getNode(ISD::SMIN, DL, N->getValueType(0), N->getOperand(1),
4024 return DAG.getNode(ISD::UMIN, DL, N->getValueType(0), N->getOperand(1),
4034 return DAG.getNode(ISD::SMIN, DL, N->getValueType(0), N->getOperand(1),
4035 lowerVectorSplatImm<5>(N, 2, DAG, /*IsSigned=*/true));
4044 return DAG.getNode(ISD::UMIN, DL, N->getValueType(0), N->getOperand(1),
4045 lowerVectorSplatImm<5>(N, 2, DAG));
4054 return DAG.getNode(ISD::MUL, DL, N->getValueType(0), N->getOperand(1),
4065 return DAG.getNode(ISD::ADD, SDLoc(N), ResTy, N->getOperand(1),
4066 DAG.getNode(ISD::MUL, SDLoc(N), ResTy, N->getOperand(2),
4078 return DAG.getNode(ISD::SUB, SDLoc(N), ResTy, N->getOperand(1),
4079 DAG.getNode(ISD::MUL, SDLoc(N), ResTy, N->getOperand(2),
4090 return DAG.getNode(ISD::SDIV, DL, N->getValueType(0), N->getOperand(1),
4100 return DAG.getNode(ISD::UDIV, DL, N->getValueType(0), N->getOperand(1),
4110 return DAG.getNode(ISD::SREM, DL, N->getValueType(0), N->getOperand(1),
4120 return DAG.getNode(ISD::UREM, DL, N->getValueType(0), N->getOperand(1),
4124 return DAG.getNode(ISD::AND, DL, N->getValueType(0), N->getOperand(1),
4128 return DAG.getNode(ISD::OR, DL, N->getValueType(0), N->getOperand(1),
4132 return DAG.getNode(ISD::XOR, DL, N->getValueType(0), N->getOperand(1),
4136 SDValue Res = DAG.getNode(ISD::OR, DL, N->getValueType(0), N->getOperand(1),
4138 return DAG.getNOT(DL, Res, Res->getValueType(0));
4142 return DAG.getNode(ISD::AND, DL, N->getValueType(0), N->getOperand(1),
4143 lowerVectorSplatImm<8>(N, 2, DAG));
4146 return DAG.getNode(ISD::OR, DL, N->getValueType(0), N->getOperand(1),
4147 lowerVectorSplatImm<8>(N, 2, DAG));
4150 return DAG.getNode(ISD::XOR, DL, N->getValueType(0), N->getOperand(1),
4151 lowerVectorSplatImm<8>(N, 2, DAG));
4160 return DAG.getNode(ISD::SHL, DL, N->getValueType(0), N->getOperand(1),
4161 truncateVecElts(N, DAG));
4164 return DAG.getNode(ISD::SHL, DL, N->getValueType(0), N->getOperand(1),
4165 lowerVectorSplatImm<3>(N, 2, DAG));
4168 return DAG.getNode(ISD::SHL, DL, N->getValueType(0), N->getOperand(1),
4169 lowerVectorSplatImm<4>(N, 2, DAG));
4172 return DAG.getNode(ISD::SHL, DL, N->getValueType(0), N->getOperand(1),
4173 lowerVectorSplatImm<5>(N, 2, DAG));
4176 return DAG.getNode(ISD::SHL, DL, N->getValueType(0), N->getOperand(1),
4177 lowerVectorSplatImm<6>(N, 2, DAG));
4186 return DAG.getNode(ISD::SRL, DL, N->getValueType(0), N->getOperand(1),
4187 truncateVecElts(N, DAG));
4190 return DAG.getNode(ISD::SRL, DL, N->getValueType(0), N->getOperand(1),
4191 lowerVectorSplatImm<3>(N, 2, DAG));
4194 return DAG.getNode(ISD::SRL, DL, N->getValueType(0), N->getOperand(1),
4195 lowerVectorSplatImm<4>(N, 2, DAG));
4198 return DAG.getNode(ISD::SRL, DL, N->getValueType(0), N->getOperand(1),
4199 lowerVectorSplatImm<5>(N, 2, DAG));
4202 return DAG.getNode(ISD::SRL, DL, N->getValueType(0), N->getOperand(1),
4203 lowerVectorSplatImm<6>(N, 2, DAG));
4212 return DAG.getNode(ISD::SRA, DL, N->getValueType(0), N->getOperand(1),
4213 truncateVecElts(N, DAG));
4216 return DAG.getNode(ISD::SRA, DL, N->getValueType(0), N->getOperand(1),
4217 lowerVectorSplatImm<3>(N, 2, DAG));
4220 return DAG.getNode(ISD::SRA, DL, N->getValueType(0), N->getOperand(1),
4221 lowerVectorSplatImm<4>(N, 2, DAG));
4224 return DAG.getNode(ISD::SRA, DL, N->getValueType(0), N->getOperand(1),
4225 lowerVectorSplatImm<5>(N, 2, DAG));
4228 return DAG.getNode(ISD::SRA, DL, N->getValueType(0), N->getOperand(1),
4229 lowerVectorSplatImm<6>(N, 2, DAG));
4238 return DAG.getNode(ISD::CTLZ, DL, N->getValueType(0), N->getOperand(1));
4247 return DAG.getNode(ISD::CTPOP, DL, N->getValueType(0), N->getOperand(1));
4256 return lowerVectorBitClear(N, DAG);
4259 return lowerVectorBitClearImm<3>(N, DAG);
4262 return lowerVectorBitClearImm<4>(N, DAG);
4265 return lowerVectorBitClearImm<5>(N, DAG);
4268 return lowerVectorBitClearImm<6>(N, DAG);
4278 SDValue One = DAG.getConstant(1, DL, VecTy);
4279 return DAG.getNode(
4281 DAG.getNode(ISD::SHL, DL, VecTy, One, truncateVecElts(N, DAG)));
4285 return lowerVectorBitSetImm<3>(N, DAG);
4288 return lowerVectorBitSetImm<4>(N, DAG);
4291 return lowerVectorBitSetImm<5>(N, DAG);
4294 return lowerVectorBitSetImm<6>(N, DAG);
4304 SDValue One = DAG.getConstant(1, DL, VecTy);
4305 return DAG.getNode(
4307 DAG.getNode(ISD::SHL, DL, VecTy, One, truncateVecElts(N, DAG)));
4311 return lowerVectorBitRevImm<3>(N, DAG);
4314 return lowerVectorBitRevImm<4>(N, DAG);
4317 return lowerVectorBitRevImm<5>(N, DAG);
4320 return lowerVectorBitRevImm<6>(N, DAG);
4325 return DAG.getNode(ISD::FADD, DL, N->getValueType(0), N->getOperand(1),
4331 return DAG.getNode(ISD::FSUB, DL, N->getValueType(0), N->getOperand(1),
4337 return DAG.getNode(ISD::FMUL, DL, N->getValueType(0), N->getOperand(1),
4343 return DAG.getNode(ISD::FDIV, DL, N->getValueType(0), N->getOperand(1),
4349 return DAG.getNode(ISD::FMA, DL, N->getValueType(0), N->getOperand(1),
4352 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), N->getValueType(0),
4354 legalizeIntrinsicImmArg<4>(N, 3, DAG, Subtarget));
4357 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), N->getValueType(0),
4359 legalizeIntrinsicImmArg<3>(N, 3, DAG, Subtarget));
4362 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), N->getValueType(0),
4364 legalizeIntrinsicImmArg<2>(N, 3, DAG, Subtarget));
4366 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), N->getValueType(0),
4368 legalizeIntrinsicImmArg<1>(N, 3, DAG, Subtarget));
4377 return DAG.getNode(LoongArchISD::VREPLGR2VR, DL, N->getValueType(0),
4378 DAG.getNode(ISD::ANY_EXTEND, DL, Subtarget.getGRLenVT(),
4388 return DAG.getNode(LoongArchISD::VREPLVE, DL, N->getValueType(0),
4390 DAG.getNode(ISD::ANY_EXTEND, DL, Subtarget.getGRLenVT(),
4398 SelectionDAG &DAG = DCI.DAG;
4403 return performANDCombine(N, DAG, DCI, Subtarget);
4405 return performORCombine(N, DAG, DCI, Subtarget);
4407 return performSETCCCombine(N, DAG, DCI, Subtarget);
4409 return performSRLCombine(N, DAG, DCI, Subtarget);
4411 return performBITREV_WCombine(N, DAG, DCI, Subtarget);
4413 return performINTRINSIC_WO_CHAINCombine(N, DAG, DCI, Subtarget);
5136 static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDValue Val,
5146 Val = DAG.getNode(LoongArchISD::MOVGR2FR_W_LA64, DL, MVT::f32, Val);
5148 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
5154 static SDValue unpackFromRegLoc(SelectionDAG &DAG, SDValue Chain,
5158 MachineFunction &MF = DAG.getMachineFunction();
5165 Val = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
5182 return convertLocVTToValVT(DAG, Val, VA, DL);
5187 static SDValue unpackFromMemLoc(SelectionDAG &DAG, SDValue Chain,
5189 MachineFunction &MF = DAG.getMachineFunction();
5194 SDValue FIN = DAG.getFrameIndex(
5195 FI, MVT::getIntegerVT(DAG.getDataLayout().getPointerSizeInBits(0)));
5207 return DAG.getExtLoad(
5209 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), ValVT);
5212 static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDValue Val,
5223 Val = DAG.getNode(LoongArchISD::MOVFR2GR_S_LA64, DL, MVT::i64, Val);
5225 Val = DAG.getNode(ISD::BITCAST, DL, LocVT, Val);
5277 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
5279 MachineFunction &MF = DAG.getMachineFunction();
5294 EVT PtrVT = getPointerTy(DAG.getDataLayout());
5302 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
5313 ArgValue = unpackFromRegLoc(DAG, Chain, VA, DL, Ins[i], *this);
5315 ArgValue = unpackFromMemLoc(DAG, Chain, VA, DL);
5319 InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, ArgValue,
5327 SDValue Offset = DAG.getIntPtrConstant(PartOffset, DL);
5328 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, ArgValue, Offset);
5329 InVals.push_back(DAG.getLoad(PartVA.getValVT(), DL, Chain, Address,
5381 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, GRLenVT);
5383 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
5384 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
5398 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
5483 static Align getPrefTypeAlign(EVT VT, SelectionDAG &DAG) {
5484 return DAG.getDataLayout().getPrefTypeAlign(
5485 VT.getTypeForEVT(*DAG.getContext()));
5493 SelectionDAG &DAG = CLI.DAG;
5502 EVT PtrVT = getPointerTy(DAG.getDataLayout());
5506 MachineFunction &MF = DAG.getMachineFunction();
5510 CCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
5543 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
5544 SDValue SizeNode = DAG.getConstant(Size, DL, GRLenVT);
5546 Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Alignment,
5554 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, CLI.DL);
5570 std::max(getPrefTypeAlign(Outs[i].ArgVT, DAG),
5571 getPrefTypeAlign(ArgValue.getValueType(), DAG));
5585 SDValue Offset = DAG.getIntPtrConstant(PartOffset, DL);
5589 StackAlign = std::max(StackAlign, getPrefTypeAlign(PartVT, DAG));
5593 SDValue SpillSlot = DAG.CreateStackTemporary(StoredSize, StackAlign);
5596 DAG.getStore(Chain, DL, ArgValue, SpillSlot,
5602 DAG.getNode(ISD::ADD, DL, PtrVT, SpillSlot, PartOffset);
5604 DAG.getStore(Chain, DL, PartValue, Address,
5609 ArgValue = convertValVTToLocVT(DAG, ArgValue, VA, DL);
5626 StackPtr = DAG.getCopyFromReg(Chain, DL, LoongArch::R3, PtrVT);
5628 DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
5629 DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
5633 DAG.getStore(Chain, DL, ArgValue, Address, MachinePointerInfo()));
5639 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
5645 Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, Glue);
5657 Callee = DAG.getTargetGlobalAddress(S->getGlobal(), DL, PtrVT, 0, OpFlags);
5662 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, OpFlags);
5673 Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
5680 Ops.push_back(DAG.getRegisterMask(Mask));
5688 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
5690 switch (DAG.getTarget().getCodeModel()) {
5708 SDValue Ret = DAG.getNode(Op, DL, NodeTys, Ops);
5709 DAG.addNoMergeSiteInfo(Ret.getNode(), CLI.NoMerge);
5713 Chain = DAG.getNode(Op, DL, NodeTys, Ops);
5714 DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge);
5718 Chain = DAG.getCALLSEQ_END(Chain, NumBytes, 0, Glue, DL);
5723 CCState RetCCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
5730 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), Glue);
5735 RetValue = convertLocVTToValVT(DAG, RetValue, VA, DL);
5765 SelectionDAG &DAG) const {
5770 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
5771 *DAG.getContext());
5773 analyzeOutputArgs(DAG.getMachineFunction(), CCInfo, Outs, /*IsRet=*/true,
5786 SDValue Val = convertValVTToLocVT(DAG, OutVals[i], VA, DL);
5787 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue);
5791 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5800 return DAG.getNode(LoongArchISD::RET, DL, MVT::Other, RetOps);
6163 SelectionDAG &DAG, int Enabled,
6180 SDValue Estimate = DAG.getNode(LoongArchISD::FRSQRTE, DL, VT, Operand);
6182 Estimate = DAG.getNode(ISD::FMUL, DL, VT, Operand, Estimate);
6192 SelectionDAG &DAG,
6208 return DAG.getNode(LoongArchISD::FRECIPE, DL, VT, Operand);
6335 SelectionDAG &DAG) const {
6344 Ops.push_back(DAG.getSignedTargetConstant(CVal, SDLoc(Op),
6353 Ops.push_back(DAG.getSignedTargetConstant(CVal, SDLoc(Op),
6362 DAG.getTargetConstant(0, SDLoc(Op), Subtarget.getGRLenVT()));
6370 DAG.getTargetConstant(CVal, SDLoc(Op), Subtarget.getGRLenVT()));
6377 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);