| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64GlobalISelUtils.cpp | 100 changeFCMPPredToAArch64CC(const CmpInst::Predicate P,AArch64CC::CondCode & CondCode,AArch64CC::CondCode & CondCode2) changeFCMPPredToAArch64CC() argument
160 changeVectorFCMPPredToAArch64CC(const CmpInst::Predicate P,AArch64CC::CondCode & CondCode,AArch64CC::CondCode & CondCode2,bool & Invert) changeVectorFCMPPredToAArch64CC() argument
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| H A D | AArch64InstructionSelector.cpp | 1357 changeFPCCToORAArch64CC(CmpInst::Predicate CC,AArch64CC::CondCode & CondCode,AArch64CC::CondCode & CondCode2) changeFPCCToORAArch64CC() argument
1414 changeFPCCToANDAArch64CC(CmpInst::Predicate CC,AArch64CC::CondCode & CondCode,AArch64CC::CondCode & CondCode2) changeFPCCToANDAArch64CC() argument
5107 AArch64CC::CondCode CondCode; tryOptSelect() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiCondCode.h | 10 enum CondCode { enum
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| H A D | LanaiInstrInfo.cpp | 520 unsigned CondCode = MI.getOperand(3).getImm(); optimizeSelect() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/ARC/MCTargetDesc/ |
| H A D | ARCInfo.h | 24 enum CondCode { enum
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.h | 35 enum CondCode { global() enum
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kInstrInfo.h | 34 enum CondCode { enum
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| H A D | M68kISelLowering.cpp | 2281 unsigned CondCode = Cond.getConstantOperandVal(0); LowerSELECT() local
2378 unsigned CondCode = CC->getAsZExtVal(); LowerSELECT() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SpeculationHardening.cpp | 226 MachineBasicBlock &SplitEdgeBB, AArch64CC::CondCode &CondCode, in insertTrackingCode()
247 AArch64CC::CondCode CondCode; in instrumentControlFlow() local
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| H A D | AArch64ISelLowering.cpp | 2696 unsigned CondCode = MI.getOperand(3).getImm(); EmitF128CSEL() local
3001 changeFPCCToAArch64CC(ISD::CondCode CC,AArch64CC::CondCode & CondCode,AArch64CC::CondCode & CondCode2) changeFPCCToAArch64CC() argument
3064 changeFPCCToANDAArch64CC(ISD::CondCode CC,AArch64CC::CondCode & CondCode,AArch64CC::CondCode & CondCode2) changeFPCCToANDAArch64CC() argument
3094 changeVectorFPCCToAArch64CC(ISD::CondCode CC,AArch64CC::CondCode & CondCode,AArch64CC::CondCode & CondCode2,bool & Invert) changeVectorFPCCToAArch64CC() argument
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsInstPrinter.h | 32 enum CondCode { enum
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VE.h | 42 enum CondCode { enum
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreInstrInfo.cpp | 37 enum CondCode { enum
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Lanai/AsmParser/ |
| H A D | LanaiAsmParser.cpp | 1062 LPCC::CondCode CondCode = splitMnemonic() local
1082 LPCC::CondCode CondCode = LPCC::suffixToLanaiCondCode(Mnemonic); splitMnemonic() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/MSP430/AsmParser/ |
| H A D | MSP430AsmParser.cpp | 334 unsigned CondCode; in parseJccInstruction() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 255 enum CondCode { // Meaning (integer) Meaning (floating-point) enum
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86BaseInfo.h | 75 enum CondCode { global() enum
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelDAGToDAG.cpp | 553 getPTXCmpMode(const CondCodeSDNode & CondCode,bool FTZ) getPTXCmpMode() argument
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| /freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1506 enum CondCode { global() enum
[all...] |
| H A D | TargetLowering.h | 5382 isXAndYEqZeroPreferableToXAndYEqY(ISD::CondCode,EVT) isXAndYEqZeroPreferableToXAndYEqY() argument
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/VE/AsmParser/ |
| H A D | VEAsmParser.cpp | 859 VECC::CondCode CondCode = in parseCC() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 2049 FPCCToARMCC(ISD::CondCode CC,ARMCC::CondCodes & CondCode,ARMCC::CondCodes & CondCode2) FPCCToARMCC() argument
4836 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); getARMCmp() local
5185 checkVSELConstraints(ISD::CondCode CC,ARMCC::CondCodes & CondCode,bool & swpCmpOps,bool & swpVselOps) checkVSELConstraints() argument
5522 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); LowerSELECT_CC() local
5539 ARMCC::CondCodes CondCode, CondCode2; LowerSELECT_CC() local
5684 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); OptimizeVFPBrcond() local
5718 ARMCC::CondCodes CondCode = LowerBRCOND() local
5771 ARMCC::CondCodes CondCode = LowerBR_CC() local
5797 ARMCC::CondCodes CondCode, CondCode2; LowerBR_CC() local
10519 ARMCC::CondCodes CondCode, CondCode2; LowerFSETCC() local
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| H A D | ARMBaseInstrInfo.cpp | 2375 unsigned CondCode = MI.getOperand(3).getImm(); optimizeSelect() local
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 2871 unsigned BaseOpc, CondCode; fastLowerIntrinsicCall() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 6076 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl); Select() local
[all...] |