Lines Matching defs:CondCode
2886 unsigned CondCode = MI.getOperand(3).getImm();
2899 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
3252 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
3280 static void changeFPCCToAArch64CC(ISD::CondCode CC,
3281 AArch64CC::CondCode &CondCode,
3282 AArch64CC::CondCode &CondCode2) {
3289 CondCode = AArch64CC::EQ;
3293 CondCode = AArch64CC::GT;
3297 CondCode = AArch64CC::GE;
3300 CondCode = AArch64CC::MI;
3303 CondCode = AArch64CC::LS;
3306 CondCode = AArch64CC::MI;
3310 CondCode = AArch64CC::VC;
3313 CondCode = AArch64CC::VS;
3316 CondCode = AArch64CC::EQ;
3320 CondCode = AArch64CC::HI;
3323 CondCode = AArch64CC::PL;
3327 CondCode = AArch64CC::LT;
3331 CondCode = AArch64CC::LE;
3335 CondCode = AArch64CC::NE;
3343 static void changeFPCCToANDAArch64CC(ISD::CondCode CC,
3344 AArch64CC::CondCode &CondCode,
3345 AArch64CC::CondCode &CondCode2) {
3349 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
3356 CondCode = AArch64CC::VC;
3363 CondCode = AArch64CC::PL;
3373 static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
3374 AArch64CC::CondCode &CondCode,
3375 AArch64CC::CondCode &CondCode2,
3381 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
3387 CondCode = AArch64CC::MI;
3399 CondCode, CondCode2);
3427 static bool isCMN(SDValue Op, ISD::CondCode CC, SelectionDAG &DAG) {
3455 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
3562 ISD::CondCode CC, SDValue CCOp,
3563 AArch64CC::CondCode Predicate,
3564 AArch64CC::CondCode OutCC,
3597 AArch64CC::CondCode InvOutCC = AArch64CC::getInvertedCondCode(OutCC);
3680 AArch64CC::CondCode &OutCC, bool Negate, SDValue CCOp,
3681 AArch64CC::CondCode Predicate) {
3687 ISD::CondCode CC = cast<CondCodeSDNode>(Val->getOperand(2))->get();
3697 AArch64CC::CondCode ExtraCC;
3777 AArch64CC::CondCode RHSCC;
3792 AArch64CC::CondCode &OutCC) {
3839 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
3922 AArch64CC::CondCode AArch64CC;
3975 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
4087 AArch64CC::CondCode CC;
4107 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get();
4218 AArch64CC::CondCode CC;
6616 AArch64CC::CondCode CC;
9803 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
9839 AArch64CC::CondCode OFCC;
9924 AArch64CC::CondCode CC1, CC2;
10154 ISD::CondCode CC;
10285 ISD::CondCode Cond = cast<CondCodeSDNode>(N->getOperand(2))->get();
10322 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(OpNo + 2))->get();
10368 AArch64CC::CondCode CC1, CC2;
10417 ISD::CondCode Cond = cast<CondCodeSDNode>(Op.getOperand(3))->get();
10418 ISD::CondCode CondInv = ISD::getSetCCInverse(Cond, VT);
10427 SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue LHS,
10583 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
10594 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
10617 AArch64CC::CondCode CC1, CC2;
10694 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
10743 AArch64CC::CondCode OFCC;
10753 ISD::CondCode CC;
11529 static AArch64CC::CondCode parseConstraintCode(llvm::StringRef Constraint) {
11530 AArch64CC::CondCode Cond = StringSwitch<AArch64CC::CondCode>(Constraint)
11553 static SDValue getSETCC(AArch64CC::CondCode CC, SDValue NZCV, const SDLoc &DL,
11565 AArch64CC::CondCode Cond = parseConstraintCode(OpInfo.ConstraintCode);
14959 AArch64CC::CondCode CC, bool NoNans, EVT VT,
15079 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
15087 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
15133 AArch64CC::CondCode CC1, CC2;
18780 AArch64CC::CondCode CC0 = (AArch64CC::CondCode)CSel0.getConstantOperandVal(2);
18781 AArch64CC::CondCode CC1 = (AArch64CC::CondCode)CSel1.getConstantOperandVal(2);
18798 AArch64CC::CondCode InvCC0 = AArch64CC::getInvertedCondCode(CC0);
18802 AArch64CC::CondCode InvCC1 = AArch64CC::getInvertedCondCode(CC1);
19019 AArch64CC::CondCode CC;
19025 AArch64CC::CondCode InvertedCC = AArch64CC::getInvertedCondCode(CC);
19148 AArch64CC::CondCode Cond);
19715 ISD::CondCode CC;
19721 AArch64CC::CondCode CC;
19764 static_cast<AArch64CC::CondCode>(Op.getConstantOperandVal(2));
19907 AArch64CC::CondCode AArch64CC =
19908 static_cast<AArch64CC::CondCode>(LHS.getConstantOperandVal(2));
20084 static std::optional<AArch64CC::CondCode> getCSETCondCode(SDValue Op) {
20087 auto CC = static_cast<AArch64CC::CondCode>(Op.getConstantOperandVal(2));
20993 static SDValue tryConvertSVEWideCompare(SDNode *N, ISD::CondCode CC,
21058 AArch64CC::CondCode Cond) {
21566 ISD::CondCode Code =
23743 AArch64CC::CondCode OpCC =
23744 static_cast<AArch64CC::CondCode>(Op->getConstantOperandVal(2));
23772 AArch64CC::CondCode CC =
23773 static_cast<AArch64CC::CondCode>(CmpLHS->getConstantOperandVal(2));
23840 ISD::CondCode CC = cast<CondCodeSDNode>(Op->getOperand(2))->get();
23882 ISD::CondCode Cond = cast<CondCodeSDNode>(N->getOperand(2))->get();
23896 static_cast<AArch64CC::CondCode>(LHS.getConstantOperandVal(2));
23982 ISD::CondCode Cond = cast<CondCodeSDNode>(N->getOperand(3))->get();
24022 ISD::CondCode Cond = cast<CondCodeSDNode>(N->getOperand(3))->get();
24186 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
24187 ISD::CondCode InverseCC =