Lines Matching defs:CondCode
521 const ISD::CondCode Cond;
592 const ISD::CondCode Cond;
689 const ISD::CondCode Cond;
2040 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
2057 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
2063 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
2065 case ISD::SETOGT: CondCode = ARMCC::GT; break;
2067 case ISD::SETOGE: CondCode = ARMCC::GE; break;
2068 case ISD::SETOLT: CondCode = ARMCC::MI; break;
2069 case ISD::SETOLE: CondCode = ARMCC::LS; break;
2070 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
2071 case ISD::SETO: CondCode = ARMCC::VC; break;
2072 case ISD::SETUO: CondCode = ARMCC::VS; break;
2073 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
2074 case ISD::SETUGT: CondCode = ARMCC::HI; break;
2075 case ISD::SETUGE: CondCode = ARMCC::PL; break;
2077 case ISD::SETULT: CondCode = ARMCC::LT; break;
2079 case ISD::SETULE: CondCode = ARMCC::LE; break;
2081 case ISD::SETUNE: CondCode = ARMCC::NE; break;
4162 DAG.getSetCC(dl, MVT::i1, CLSHi, Constant31, ISD::CondCode::SETEQ);
4164 DAG.getSetCC(dl, MVT::i1, Hi, Constant0, ISD::CondCode::SETEQ);
4747 SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
4853 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
4859 switch (CondCode) {
4862 CondCode = ARMCC::PL;
4865 CondCode = ARMCC::MI;
4871 switch (CondCode) {
4881 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5202 static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
5208 CondCode = ARMCC::GE;
5213 CondCode = ARMCC::GT;
5233 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
5239 CondCode = ARMCC::VS;
5247 CondCode = ARMCC::EQ;
5278 static bool isGTorGE(ISD::CondCode CC) {
5282 static bool isLTorLE(ISD::CondCode CC) {
5294 const ISD::CondCode CC, const SDValue K) {
5324 ISD::CondCode CC1 = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5334 ISD::CondCode CC2 = cast<CondCodeSDNode>(Op2.getOperand(4))->get();
5389 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5459 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5539 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5540 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
5541 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
5556 ARMCC::CondCodes CondCode, CondCode2;
5557 FPCCToARMCC(CC, CondCode, CondCode2);
5570 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
5572 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
5573 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
5581 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5663 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5701 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5702 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5735 ARMCC::CondCodes CondCode =
5737 CondCode = ARMCC::getOppositeCondition(CondCode);
5738 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
5750 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5788 ARMCC::CondCodes CondCode =
5790 CondCode = ARMCC::getOppositeCondition(CondCode);
5791 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
5814 ARMCC::CondCodes CondCode, CondCode2;
5815 FPCCToARMCC(CC, CondCode, CondCode2);
5817 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
6790 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
10519 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(3))->get();
10536 ARMCC::CondCodes CondCode, CondCode2;
10537 FPCCToARMCC(CC, CondCode, CondCode2);
10546 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
13218 ISD::CondCode CC;
13472 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
18183 static SDValue SearchLoopIntrinsic(SDValue N, ISD::CondCode &CC, int &Imm,
18235 ISD::CondCode CC;
18266 auto IsTrueIfZero = [](ISD::CondCode CC, int Imm) {
18273 auto IsFalseIfZero = [](ISD::CondCode CC, int Imm) {