| /llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCOptAddrMode.cpp | 297 Register BaseReg = Ldst->getOperand(BasePos).getReg(); in canJoinInstructions() local
353 MachineOperand &Incr, unsigned BaseReg) { in canFixPastUses()
459 Register BaseReg = Ldst.getOperand(BasePos).getReg(); in changeToAddrMode() local
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| H A D | ARCRegisterInfo.cpp | 46 unsigned BaseReg = FrameReg; in replaceFrameIndex() local
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FixupLEAs.cpp | 458 Register BaseReg = LeaI->getOperand(1 + X86::AddrBaseReg).getReg(); in checkRegUsage() local
507 Register BaseReg = I->getOperand(1 + X86::AddrBaseReg).getReg(); in optLEAALU() local
566 Register BaseReg = Base.getReg(); in optTwoAddrLEA() local
759 Register BaseReg = Base.getReg(); in processInstrForSlow3OpLEA() local
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| H A D | X86AsmPrinter.cpp | 377 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintLeaMemReference() local
473 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintIntelMemReference() local
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| H A D | X86InsertPrefetch.cpp | 85 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) || in IsMemOpCompatibleWithPrefetch() local
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| /llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.h | 49 auto BaseReg = MI.getOperand(0).getReg(); in isLDMBaseRegInList() local
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| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64StorePairSuppress.cpp | 168 Register BaseReg = BaseOp->getReg(); in runOnMachineFunction() local
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| H A D | AArch64FalkorHWPFFix.cpp | 214 Register BaseReg; member
643 Register BaseReg = MI.getOperand(BaseRegIdx).getReg(); in getLoadInfo() local
[all...] |
| H A D | AArch64RegisterInfo.cpp | 792 isFrameOffsetLegal(const MachineInstr * MI,Register BaseReg,int64_t Offset) const isFrameOffsetLegal() argument
814 Register BaseReg = MRI.createVirtualRegister(&AArch64::GPR64spRegClass); materializeFrameBaseRegister() local
826 resolveFrameIndex(MachineInstr & MI,Register BaseReg,int64_t Offset) const resolveFrameIndex() argument
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| H A D | AArch64LoadStoreOptimizer.cpp | 1299 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(LoadMI).getReg(); findMatchingStore() local
1694 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(FirstMI).getReg(); findMatchingInsn() local
2055 isMatchingUpdateInsn(MachineInstr & MemMI,MachineInstr & MI,unsigned BaseReg,int Offset) isMatchingUpdateInsn() argument
2106 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(MemMI).getReg(); findMatchingUpdateInsnForward() local
2184 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(MemMI).getReg(); findMatchingUpdateInsnBackward() local
[all...] |
| /llvm-project/llvm/lib/CodeGen/ |
| H A D | LocalStackSlotAllocation.cpp | 291 lookupCandidateBaseReg(unsigned BaseReg, in lookupCandidateBaseReg() argument
364 Register BaseReg; in insertFrameReferenceRegisters() local
[all...] |
| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ThumbRegisterInfo.cpp | 126 emitThumbRegPlusImmInReg(MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,const DebugLoc & dl,Register DestReg,Register BaseReg,int NumBytes,bool CanChangeCC,const TargetInstrInfo & TII,const ARMBaseRegisterInfo & MRI,unsigned MIFlags=MachineInstr::NoFlags) emitThumbRegPlusImmInReg() argument
254 emitThumbRegPlusImmediate(MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,const DebugLoc & dl,Register DestReg,Register BaseReg,int NumBytes,const TargetInstrInfo & TII,const ARMBaseRegisterInfo & MRI,unsigned MIFlags) emitThumbRegPlusImmediate() argument
521 resolveFrameIndex(MachineInstr & MI,Register BaseReg,int64_t Offset) const resolveFrameIndex() argument
[all...] |
| H A D | Thumb2SizeReduction.cpp | 527 if (MO.getReg() == BaseReg) in ReduceLoadStore() local
497 Register BaseReg = MI->getOperand(0).getReg(); ReduceLoadStore() local
535 Register BaseReg = MI->getOperand(1).getReg(); ReduceLoadStore() local
548 Register BaseReg = MI->getOperand(1).getReg(); ReduceLoadStore() local
[all...] |
| H A D | ARMBaseRegisterInfo.cpp | 722 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); in isFrameOffsetLegal() argument
681 Register BaseReg = MRI.createVirtualRegister(&ARM::GPRRegClass); materializeFrameBaseRegister() local
693 resolveFrameIndex(MachineInstr & MI,Register BaseReg,int64_t Offset) const resolveFrameIndex() argument
[all...] |
| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelDAGToDAG.cpp | 90 SelectGlobalValueVariableOffset(SDValue Addr,SDValue & BaseReg,SDValue & Offset) SelectGlobalValueVariableOffset() argument
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| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVRegisterInfo.cpp | 649 isFrameOffsetLegal(const MachineInstr * MI,Register BaseReg,int64_t Offset) const isFrameOffsetLegal() argument
676 Register BaseReg = MFI.createVirtualRegister(&RISCV::GPRRegClass); materializeFrameBaseRegister() local
685 resolveFrameIndex(MachineInstr & MI,Register BaseReg,int64_t Offset) const resolveFrameIndex() argument
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| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenMemAbsolute.cpp | 143 unsigned BaseReg = BaseOp->getReg(); runOnMachineFunction() local
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| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LoadStoreOpt.cpp | 87 if (!mi_match(Ptr, MRI, m_GPtrAdd(m_Reg(BaseReg), m_Reg(PtrAddRHS)))) { in getPointerInfo() local
204 Register BaseReg; instMayAlias() local
744 Register BaseReg; mergeTruncStore() local
[all...] |
| /llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 130 emitMask(BaseReg, LoadStoreStackMaskReg, STI); in sandboxLoadStoreStackChange() local
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| /llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86IntelInstPrinter.cpp | 383 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); printMemReference() local
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| H A D | X86ATTInstPrinter.cpp | 426 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg); printMemReference() local
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| H A D | X86MCTargetDesc.cpp | 665 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg); evaluateMemoryOperandAddress() local
691 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg); getMemoryOperandRelocationOffset() local
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| /llvm-project/bolt/lib/Passes/ |
| H A D | JTFootprintReduction.cpp | 175 MCPhysReg BaseReg; in tryOptimizePIC() local
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| /llvm-project/llvm/tools/llvm-exegesis/lib/X86/ |
| H A D | Target.cpp | 295 for (const unsigned BaseReg : PossibleBaseRegs.set_bits()) { in generateLEATemplatesCommon() local
360 __anona615e0730202(unsigned BaseReg, unsigned IndexReg, BitVector &CandidateDestRegs) generateCodeTemplates() argument
420 __anona615e0730402(unsigned BaseReg, unsigned IndexReg, BitVector &CandidateDestRegs) generateCodeTemplates() argument
[all...] |
| /llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiMemAluCombiner.cpp | 373 BaseReg = MBBIter->getOperand(1).getReg(); in combineMemAluInBasicBlock() local
|