Lines Matching defs:BaseReg
295 for (const unsigned BaseReg : PossibleBaseRegs.set_bits()) {
302 setMemOp(IT, 1, MCOperand::createReg(BaseReg));
311 RestrictDestRegs(BaseReg, IndexReg, PossibleDestRegsNow);
321 CT.Config = formatv("{3}(%{0}, %{1}, {2})", RegInfo.getName(BaseReg),
359 [this](unsigned BaseReg, unsigned IndexReg,
364 State.getRATC().getRegister(BaseReg).aliasedBits();
419 [this](unsigned BaseReg, unsigned IndexReg,
423 State.getRATC().getRegister(BaseReg).aliasedBits());
493 .addReg(X86::RSP) // BaseReg
507 .addReg(X86::RSP) // BaseReg
571 .addReg(X86::RSP) // BaseReg
587 .addReg(X86::RSP) // BaseReg
608 .addReg(X86::RSP) // BaseReg
921 setMemOp(IT, MemOpIdx + 0, MCOperand::createReg(Reg)); // BaseReg