Lines Matching defs:BaseReg

202                             unsigned BaseReg, int Offset);
1419   Register BaseReg = AArch64InstrInfo::getLdStBaseOp(LoadMI).getReg();
1444     // it's unnecessary to check if BaseReg is modified by the store itself.
1448         BaseReg == AArch64InstrInfo::getLdStBaseOp(MI).getReg() &&
1464     if (!ModifiedRegUnits.available(BaseReg))
1817   Register BaseReg = AArch64InstrInfo::getLdStBaseOp(FirstMI).getReg();
1888       if (BaseReg == MIBaseReg) {
1962         // If the BaseReg has been modified, then we cannot do the optimization.
1968         if (!ModifiedRegUnits.available(BaseReg))
2063     if (!ModifiedRegUnits.available(BaseReg)) {
2207   Register BaseReg = AArch64InstrInfo::getLdStBaseOp(MemMI).getReg();
2211   // Add IndexReg, BaseReg, High (the BaseReg may be SP)
2215           .addUse(BaseReg)
2253                                                unsigned BaseReg, int Offset) {
2269     if (MI.getOperand(0).getReg() != BaseReg ||
2270         MI.getOperand(1).getReg() != BaseReg)
2334   Register BaseReg = AArch64InstrInfo::getLdStBaseOp(MemMI).getReg();
2354       if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg))
2368   const bool BaseRegSP = BaseReg == AArch64::SP;
2386     if (isMatchingUpdateInsn(*I, MI, BaseReg, UnscaledOffset))
2396     if (!ModifiedRegUnits.available(BaseReg) ||
2397         !UsedRegUnits.available(BaseReg) ||
2412   Register BaseReg = AArch64InstrInfo::getLdStBaseOp(MemMI).getReg();
2428       if (DestReg[i] == BaseReg || TRI->isSubRegister(BaseReg, DestReg[i]))
2432   const bool BaseRegSP = BaseReg == AArch64::SP;
2461     if (isMatchingUpdateInsn(*I, MI, BaseReg, Offset)) {
2474     if (!ModifiedRegUnits.available(BaseReg) ||
2475         !UsedRegUnits.available(BaseReg))