| /llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelDAGToDAG.cpp | 238 const APInt &AndMask = N->getConstantOperandAPInt(1); selectShiftMask() local
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| /llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| H A D | AMDGPUInstPrinter.cpp | 1577 printSwizzleBitmask(const uint16_t AndMask,const uint16_t OrMask,const uint16_t XorMask,raw_ostream & O) printSwizzleBitmask() argument
1634 uint16_t AndMask = (Imm >> BITMASK_AND_SHIFT) & BITMASK_MASK; printSwizzle() local
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| /llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVInstructionSelector.cpp | 178 APInt AndMask; selectShiftMask() local
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| /llvm-project/llvm/lib/Transforms/Instrumentation/ |
| H A D | DataFlowSanitizer.cpp | 282 uint64_t AndMask; member
1907 IRB.CreateAnd(OffsetLong, ConstantInt::get(IntptrTy, ~AndMask)); in getShadowOffset() local
[all...] |
| H A D | MemorySanitizer.cpp | 383 uint64_t AndMask; global() member
1712 if (uint64_t AndMask = MS.MapParams->AndMask) getShadowPtrOffset() local
[all...] |
| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 748 APInt AndMask = RHSC->getAPIntValue(); SelectShiftedRegisterFromAnd() local
836 uint64_t AndMask = CSD->getZExtValue(); getExtendTypeForNode() local
2493 uint64_t AndMask = 0; isSeveralBitsExtractOpFromShr() local
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| H A D | AArch64FrameLowering.cpp | 759 const uint64_t AndMask = ~(MaxAlign - 1); allocateStackSpace() local
2104 uint64_t AndMask = ~(MFI.getMaxAlign().value() - 1); emitPrologue() local
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| H A D | AArch64ISelLowering.cpp | 20095 uint64_t AndMask = CSD->getZExtValue(); isExtendOrShiftOperand() local
[all...] |
| /llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelDAGToDAG.cpp | 760 uint64_t AndMask = MaskNode->getZExtValue(); in detectOrAndInsertion() local
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| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 895 preferedOpcodeForCmpEqPiecesOfOperand(EVT VT,unsigned ShiftOpc,bool MayTransformRotate,const APInt & ShiftOrRotateAmt,const std::optional<APInt> & AndMask) preferedOpcodeForCmpEqPiecesOfOperand() argument
3378 shouldFoldSelectWithSingleBitTest(EVT VT,const APInt & AndMask) shouldFoldSelectWithSingleBitTest() argument
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| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 2759 const APInt &AndMask = ShAmt.getConstantOperandAPInt(1); selectShiftMask() local
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| /llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineSelect.cpp | 135 APInt AndMask; in foldSelectICmpAnd() local
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| /llvm-project/llvm/lib/Transforms/Utils/ |
| H A D | Local.cpp | 3853 const APInt &AndMask = *C; collectBitParts() local
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| /llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 7911 encodeBitmaskPerm(const unsigned AndMask,const unsigned OrMask,const unsigned XorMask) encodeBitmaskPerm() argument
8063 unsigned AndMask = 0; parseSwizzleBitmaskPerm() local
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| /llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 7461 uint64_t AndMask = *MaybeAndMask; getExtendTypeForInst() local
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 5577 auto AndMask = B.buildConstant(S32, 0x0000ffff); legalizePointerAsRsrcIntrin() local
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| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 25988 SmallVector<SDValue, 16> AndMask(NumElts, DAG.getUNDEF(IntSVT)); visitVECTOR_SHUFFLE() local
27643 const APInt &AndMask = ConstAndRHS->getAPIntValue(); SimplifySelectCC() local
[all...] |
| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 17759 uint32_t AndMask = static_cast<uint32_t>(AndMaskNode->getZExtValue()); PerformShiftCombine() local
|