/llvm-project/llvm/lib/Target/LoongArch/ |
H A D | LoongArchExpandAtomicPseudoInsts.cpp | 154 Register AddrReg = MI.getOperand(2).getReg(); doAtomicBinOpExpansion() local 245 Register AddrReg = MI.getOperand(2).getReg(); doMaskedAtomicBinOpExpansion() local 384 Register AddrReg = MI.getOperand(3).getReg(); expandAtomicMinMaxOp() local 498 Register AddrReg = MI.getOperand(2).getReg(); expandAtomicCmpXchg() local [all...] |
H A D | LoongArchExpandPseudoInsts.cpp | 722 Register AddrReg = IsTailCall ? LoongArch::R19 : LoongArch::R1; expandFunctionCALL() local
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/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsNaClELFStreamer.cpp | 101 emitMask(unsigned AddrReg,unsigned MaskReg,const MCSubtargetInfo & STI) emitMask() argument 114 unsigned AddrReg = MI.getOperand(0).getReg(); sandboxIndirectJump() local
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/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVExpandAtomicPseudoInsts.cpp | 267 Register AddrReg = MI.getOperand(2).getReg(); in doAtomicBinOpExpansion() local 332 Register AddrReg = MI.getOperand(2).getReg(); in doMaskedAtomicBinOpExpansion() local 473 Register AddrReg = MI.getOperand(3).getReg(); in expandAtomicMinMaxOp() local 637 Register AddrReg = MI.getOperand(2).getReg(); in expandAtomicCmpXchg() local
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H A D | RISCVAsmPrinter.cpp | 379 const MachineOperand &AddrReg = MI->getOperand(OpNo); PrintAsmMemoryOperand() local 531 Register AddrReg = MI.getOperand(0).getReg(); LowerKCFI_CHECK() local
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/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCExpandPseudos.cpp | 65 Register AddrReg = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in expandStore() local
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/llvm-project/llvm/lib/Target/M68k/GISel/ |
H A D | M68kCallLowering.cpp | 85 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress() local 178 MachineInstrBuilder AddrReg = MIRBuilder.buildFrameIndex(FramePtr, FI); in getStackAddress() local
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/llvm-project/llvm/lib/Target/PowerPC/GISel/ |
H A D | PPCCallLowering.cpp | 179 MachineInstrBuilder AddrReg = MIRBuilder.buildFrameIndex(FramePtr, FI); getStackAddress() local
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H A D | PPCInstructionSelector.cpp | 750 Register AddrReg = I.getOperand(1).getReg(); in select() local
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/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ExpandPseudoInsts.cpp | 247 Register AddrReg = MI.getOperand(2).getReg(); expandCMP_SWAP() local 327 Register AddrReg = MI.getOperand(3).getReg(); expandCMP_SWAP_128() local
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H A D | AArch64SIMDInstrOpt.cpp | 508 unsigned SeqReg, AddrReg; in optimizeLdStInterleave() local
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H A D | AArch64FastISel.cpp | 2056 emitStoreRelease(MVT VT,unsigned SrcReg,unsigned AddrReg,MachineMemOperand * MMO) emitStoreRelease() argument 2196 Register AddrReg = getRegForValue(PtrV); selectStore() local 2515 Register AddrReg = getRegForValue(BI->getOperand(0)); selectIndirectBr() local 5069 const Register AddrReg = constrainOperandRegClass( selectAtomicCmpXchg() local [all...] |
H A D | AArch64AsmPrinter.cpp | 468 Register AddrReg = MI.getOperand(0).getReg(); LowerKCFI_CHECK() local [all...] |
/llvm-project/llvm/lib/Target/X86/GISel/ |
H A D | X86CallLowering.cpp | 103 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); getStackAddress() local
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H A D | X86InstructionSelector.cpp | 1522 Register AddrReg = MRI.createVirtualRegister(&X86::GR64RegClass); materializeFP() local
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/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMCallLowering.cpp | 106 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); getStackAddress() local
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H A D | ARMExpandPseudoInsts.cpp | 1819 Register AddrReg = MI.getOperand(2).getReg(); ExpandCMP_SWAP() local 1949 Register AddrReg = MI.getOperand(2).getReg(); ExpandCMP_SWAP_64() local
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/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SILoadStoreOptimizer.cpp | 121 const MachineOperand *AddrReg[MaxAddressRegs]; global() member 1274 const auto *AddrReg = TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr); mergeRead2Pair() local 1349 const MachineOperand *AddrReg = mergeWrite2Pair() local [all...] |
H A D | R600InstrInfo.cpp | 1099 unsigned AddrReg; buildIndirectWrite() local 1131 unsigned AddrReg; buildIndirectRead() local [all...] |
H A D | AMDGPUCallLowering.cpp | 114 auto AddrReg = MIRBuilder.buildFrameIndex( getStackAddress() local 228 auto AddrReg = MIRBuilder.buildPtrAdd(PtrTy, SPReg, OffsetReg); getStackAddress() local
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/llvm-project/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64CallLowering.cpp | 151 auto AddrReg = MIRBuilder.buildFrameIndex(LLT::pointer(0, 64), FI); getStackAddress() local 273 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); getStackAddress() local
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/llvm-project/llvm/lib/Target/RISCV/GISel/ |
H A D | RISCVCallLowering.cpp | 82 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); getStackAddress() local
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/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsCallLowering.cpp | 240 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress() local
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/llvm-project/llvm/lib/Target/X86/ |
H A D | X86SpeculativeLoadHardening.cpp | 1160 BuildMI(MBB, InsertPt, DebugLoc(), TII->get(X86::LEA64r), AddrReg) in tracePredStateThroughIndirectBranches() local
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H A D | X86MCInstLower.cpp | 918 const Register AddrReg = MI.getOperand(0).getReg(); LowerKCFI_CHECK() local
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