History log of /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll (Results 1 – 25 of 35)
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Revision tags: llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3
# 0fee2115 14-Feb-2024 Luke Lau <luke@igalia.com>

[RISCV] Remove -riscv-v-fixed-length-vector-lmul-max from tests. NFC (#78299)

Some fixed vector tests in test/CodeGen/RISCV/rvv have multiple run
lines that
check various configurations of -riscv-

[RISCV] Remove -riscv-v-fixed-length-vector-lmul-max from tests. NFC (#78299)

Some fixed vector tests in test/CodeGen/RISCV/rvv have multiple run
lines that
check various configurations of -riscv-v-fixed-length-vector-lmul-max.
From
what I understand this flag was introduced in the early days of fixed
length
vector support, but now that fixed vector codegen has matured I'm not
sure if
it's as relevant today.

This patch proposes to remove the various lmul-max run lines from the
tests to
make them more readable, and any changes to fixed vector codegen easier
to
review.

We have removed them before for the same reason, so this would take care
of the
remaining test cases: https://reviews.llvm.org/D157973#4593268

(I don't have any strong motivation to remove the actual flag itself, my
own
personal motivation is just to clean up the tests)

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Revision tags: llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0
# 74f985b7 06-Sep-2023 Luke Lau <luke@igalia.com>

[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)

V implies Zvl128b, but a lot of the fixed vector tests also redundantly
specify -riscv-v-vector-bits-min=128. This patch removes them

[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)

V implies Zvl128b, but a lot of the fixed vector tests also redundantly
specify -riscv-v-vector-bits-min=128. This patch removes them where
there isn't another minimum vlen being tested for, and for cases where
Zve* is being used Zvl128b was added to maintain the old test diff (and
because an awkward vlen probably isn't interesting to test for). Other
places where -risc-v-vector-bits-min were being used were replaced with
Zvl.

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Revision tags: llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3
# 67b71ad0 18-Aug-2023 Philip Reames <preames@rivosinc.com>

[DAG] Fold insert_subvector undef, (extract_subvector X, 0), 0 with non-matching types

We have an existing DAG combine for when an insert/extract subvector pair is entirely a nop, but we hadn't hand

[DAG] Fold insert_subvector undef, (extract_subvector X, 0), 0 with non-matching types

We have an existing DAG combine for when an insert/extract subvector pair is entirely a nop, but we hadn't handled the case where the net result was either an insert or an extract (but not both). The transform is restricted to index = 0 to avoid having to adjust indices after the transform.

Differential Revision: https://reviews.llvm.org/D158201

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# bbbb93eb 18-Aug-2023 Craig Topper <craig.topper@sifive.com>

Revert "[DAG] Fold insert_subvector undef, (extract_subvector X, 0), 0 with non-matching types"

This reverts commit 770be43f6782dab84d215d01b37396d63a9c2b6e.

Forgot to remove from my tree while exp

Revert "[DAG] Fold insert_subvector undef, (extract_subvector X, 0), 0 with non-matching types"

This reverts commit 770be43f6782dab84d215d01b37396d63a9c2b6e.

Forgot to remove from my tree while experimenting.

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# 770be43f 18-Aug-2023 Craig Topper <craig.topper@sifive.com>

[DAG] Fold insert_subvector undef, (extract_subvector X, 0), 0 with non-matching types

We have an existing DAG combine for when an insert/extract subvector pair is entirely a nop, but we hadn't hand

[DAG] Fold insert_subvector undef, (extract_subvector X, 0), 0 with non-matching types

We have an existing DAG combine for when an insert/extract subvector pair is entirely a nop, but we hadn't handled the case where the net result was either an insert or an extract (but not both). The transform is restricted to index = 0 to avoid having to adjust indices after the transform.

Reviews, a couple comments on the test changes:
* Mostly RISCV, mostly schedule reordering.
* One real regression in splats-with-mixed-vl.ll due to a different overly aggressive combine, fix in a follow up patch.
* The test/CodeGen/X86/vector-replicaton-i1-mask.ll diff looked concerning at first, but not the mask size at most 4 i1s. I think the type changes on the mask loads are correct, but would welcome a second opinion with someone more familiar with AVX512 codegen.

Differential Revision: https://reviews.llvm.org/D158201

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Revision tags: llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init
# 92b5a340 29-Jun-2023 Philip Reames <preames@rivosinc.com>

[RISCV] Remove legacy TA/TU pseudo distinction for unary instructions

This change continues with the line of work discussed in https://discourse.llvm.org/t/riscv-transition-in-vector-pseudo-structur

[RISCV] Remove legacy TA/TU pseudo distinction for unary instructions

This change continues with the line of work discussed in https://discourse.llvm.org/t/riscv-transition-in-vector-pseudo-structure-policy-variants/71295. In D153155, we started removing the legacy distinction between unsuffixed (TA) and _TU pseudos. This patch continues that effort for the unary instruction families.

The change consists of a few interacting pieces:
* Adding a vector policy operand to VPseudoUnaryNoMaskTU.
* Then using VPseudoUnaryNoMaskTU for all cases where VPseudoUnaryNoMask was previously used and deleting the unsuffixed form.
* Then renaming VPseudoUnaryNoMaskTU to VPseudoUnaryNoMask, and adjusting the RISCVMaskedPseudo table to use the combined pseudo.
* Fixing up two places in C++ code which manually construct VMV_V_* instructions.

Normally, I'd try to factor this into a couple of changes, but in this case, the table structure is tied to naming and thus we can't really separate the otherwise NFC bits.

As before, we see codegen changes (some improvements and some regressions) due to scheduling differences caused by the extra implicit_def instructions.

Differential Revision: https://reviews.llvm.org/D153899

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Revision tags: llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1
# 2b24e7b5 31-Mar-2023 Luke Lau <luke@igalia.com>

[RISCV] Use tail agnostic policy more often when lowering insert_subvector

If we're inserting a fixed length subvector into a fixed length vector,
then we can use a tail agnostic policy as long as w

[RISCV] Use tail agnostic policy more often when lowering insert_subvector

If we're inserting a fixed length subvector into a fixed length vector,
then we can use a tail agnostic policy as long as we're inserting up to
or past the end of the main vector.
I.e., because we're overwriting all of the main vector's tail elements,
and we don't care what the elements after that are.
As noted by Philip in https://reviews.llvm.org/D146711#4220341

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D147347

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Revision tags: llvmorg-16.0.0, llvmorg-16.0.0-rc4
# 365f8403 09-Mar-2023 Piyou Chen <piyou.chen@sifive.com>

[RISCV] Enable subregister liveness by default

This commit enable the subregister liveness by default in RISC-V.

It was previously disabled in https://reviews.llvm.org/D129646 after a previous atte

[RISCV] Enable subregister liveness by default

This commit enable the subregister liveness by default in RISC-V.

It was previously disabled in https://reviews.llvm.org/D129646 after a previous attempt to enabled it https://reviews.llvm.org/D128016.

We believe that https://reviews.llvm.org/D129735 fixes the issue that caused it to be disabled.

Reviewed By: craig.topper, kito-cheng

Differential Revision: https://reviews.llvm.org/D145546

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Revision tags: llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7
# 1456b686 19-Dec-2022 Nikita Popov <npopov@redhat.com>

[RISCV] Convert some tests to opaque pointers (NFC)


Revision tags: llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3
# d89d45ca 06-Oct-2022 Philip Reames <preames@rivosinc.com>

[RISCV][InsertVSETVLI] Default to MA not MU

This changes the default value used for mask policy from mask undisturbed to mask agnostic. In hardware, there may be a minor preference for ta/ma, but si

[RISCV][InsertVSETVLI] Default to MA not MU

This changes the default value used for mask policy from mask undisturbed to mask agnostic. In hardware, there may be a minor preference for ta/ma, but since this is only going to apply to instructions which don't use the mask policy bit, this is functionally mostly a nop. The main value is to make future changes to using MA when legal for masked instructions easier to review by reducing test churn.

The prior code was motivated by a desire to minimize state transitions between masked and unmasked code. This patch achieves the same effect using the demanded field logic (landed in afb45ff), and there are no regressions I spotted in the test diffs. (Given the size, I have only been able to skim.) I do want to call out that regressions are possible here; the demanded analysis only works on a block local scope right now, so e.g. a tight loop mixing masked and unmasked computation might see an extra vsetvli or two.

Differential Revision: https://reviews.llvm.org/D133803

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Revision tags: working, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3
# c9a41fe6 19-Aug-2022 Craig Topper <craig.topper@sifive.com>

[RISCV] Prefer vnsrl.wi v8, v8, 0 over vnsrl.wx v8, v8, x0.

I have a couple data points that some microarchitectures prefer
the immediate 0 over x0. Does anyone know of microarchitectures
where the

[RISCV] Prefer vnsrl.wi v8, v8, 0 over vnsrl.wx v8, v8, x0.

I have a couple data points that some microarchitectures prefer
the immediate 0 over x0. Does anyone know of microarchitectures
where the opposite is true?

Unfortunately, this is different than the vncvt.x.x.w alias
from the spec. Perhaps the alias was poorly chosen if x0 isn't
as optimal as immediate 0 on all microarchitectures.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D132041

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Revision tags: llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init
# d1a5669f 13-Jul-2022 Fraser Cormack <fraser@codeplay.com>

[RISCV] Disable subregister liveness by default

We previously enabled subregister liveness by default when compiling
with RVV. This has been shown to cause miscompilations where RVV
register operand

[RISCV] Disable subregister liveness by default

We previously enabled subregister liveness by default when compiling
with RVV. This has been shown to cause miscompilations where RVV
register operand constraints are not met. A test was added for this in
D129639 which explains the issue in more detail.

Until this issue is fixed in some way, we should not be enabling
subregister liveness unless the user asks for it.

Reviewed By: craig.topper, rogfer01, kito-cheng

Differential Revision: https://reviews.llvm.org/D129646

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Revision tags: llvmorg-14.0.6
# 59cde213 21-Jun-2022 Craig Topper <craig.topper@sifive.com>

Recommit "[RISCV] Enable subregister liveness tracking for RVV."

The failure that caused the previous revert has been fixed
by https://reviews.llvm.org/D126048

Original commit message:

RVV makes h

Recommit "[RISCV] Enable subregister liveness tracking for RVV."

The failure that caused the previous revert has been fixed
by https://reviews.llvm.org/D126048

Original commit message:

RVV makes heavy use of subregisters due to LMUL>1 and segment
load/store tuples. Enabling subregister liveness tracking improves the quality
of the register allocation.

I've added a command line that can be used to turn it off if it causes compile
time or functional issues. I used the command line to keep the old behavior
for one interesting test case that was testing register allocation.

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D128016

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# 4a3e4611 16-Jun-2022 Philip Reames <preames@rivosinc.com>

[RISCV] Extend demanded field transform in InsertVSETVLI to VTYPE subfeilds

The motivating case, and the only one actually enabled by this patch, is a load or store followed by another op with the s

[RISCV] Extend demanded field transform in InsertVSETVLI to VTYPE subfeilds

The motivating case, and the only one actually enabled by this patch, is a load or store followed by another op with the same SEW/LMUL ratio.

As an example, consider:

define void @test1(ptr %in, ptr %out) {
entry:
%0 = load <8 x i16>, ptr %in, align 2
%1 = sext <8 x i16> %0 to <8 x i32>
store <8 x i32> %1, ptr %out, align 4
ret void
}

Without this patch, we get:

vsetivli zero, 8, e16, mf4, ta, mu
vle16.v v8, (a0)
vsetvli zero, zero, e32, mf2, ta, mu
vsext.vf2 v9, v8
vse32.v v9, (a1)
ret

Whereas with the patch we get:

vsetivli zero, 8, e32, mf2, ta, mu
vle16.v v8, (a0)
vsext.vf2 v9, v8
vse32.v v9, (a1)
ret

We have rewritten the first vsetvli and thus removed the second one.

As is strongly hinted by the code structure and todos, I am planning on communing this with all (or most all?) of the cases from isCompatible used in the forward data flow. This will be done in a series of following changes - some NFC reworks, and some reviewed optimization extensions.

Differential Revision: https://reviews.llvm.org/D127780

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Revision tags: llvmorg-14.0.5, llvmorg-14.0.4
# 1878f240 16-May-2022 Zakk Chen <zakk.chen@sifive.com>

[RISCV] Fix incorrect use of tail agnostic vslideup.

We need to use tail undisturbed for vslideup to implement
vector insert operation correctly.

Ideally, we cound use the tail agnostic when insert

[RISCV] Fix incorrect use of tail agnostic vslideup.

We need to use tail undisturbed for vslideup to implement
vector insert operation correctly.

Ideally, we cound use the tail agnostic when insert subvector
or element at the end of the vector. This will be in follow-up
patch.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D125545

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# a2918976 13-May-2022 Craig Topper <craig.topper@sifive.com>

Revert "[RISCV] Enable subregister liveness tracking for RVV."

This reverts most of ed242b54c9c2aa84a47f66af5b8497d93646b68d

I'm seeing failures in our intrinsic testing on qemu that seem
related t

Revert "[RISCV] Enable subregister liveness tracking for RVV."

This reverts most of ed242b54c9c2aa84a47f66af5b8497d93646b68d

I'm seeing failures in our intrinsic testing on qemu that seem
related to this. Reverting while I investigate.

I've left the command line option in place for directed testing.
It defaults to off.

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# ed242b54 11-May-2022 Craig Topper <craig.topper@sifive.com>

[RISCV] Enable subregister liveness tracking for RVV.

RVV makes heavy use of subregisters due to LMUL>1 and segment
load/store tuples. Enabling subregister liveness tracking improves the quality
of

[RISCV] Enable subregister liveness tracking for RVV.

RVV makes heavy use of subregisters due to LMUL>1 and segment
load/store tuples. Enabling subregister liveness tracking improves the quality
of the register allocation.

I've added a command line that can be used to turn it off if it causes compile
time or functional issues. I used the command line to keep the old behavior
for one interesting test case that was testing register allocation.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D125108

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Revision tags: llvmorg-14.0.3, llvmorg-14.0.2
# ffe03ff7 25-Apr-2022 Zakk Chen <zakk.chen@sifive.com>

[RISCV] Fix incorrect policy implement for unmasked vslidedown and vslideup.

vslideup works by leaving elements 0<i<OFFSET undisturbed.
so it need the destination operand as input for correctness
re

[RISCV] Fix incorrect policy implement for unmasked vslidedown and vslideup.

vslideup works by leaving elements 0<i<OFFSET undisturbed.
so it need the destination operand as input for correctness
regardless of policy. Add a operand to indicate policy.

We also add policy operand for unmaksed vslidedown to keep the interface consistent with vslideup
because vslidedown have only undisturbed at 0<i<vstart but user have no way to control of vstart.

Reviewed By: rogfer01, craig.topper

Differential Revision: https://reviews.llvm.org/D124186

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Revision tags: llvmorg-14.0.1
# 9b0f227d 22-Mar-2022 Craig Topper <craig.topper@sifive.com>

[TableGen][RISCV] Add InstAliases with zero_reg to cover unmasked vnot.v, vncvt.x.x.w, vneg.v, etc.

The mask being NoRegister prevented the existing aliases from matching
since NoRegister isn't in t

[TableGen][RISCV] Add InstAliases with zero_reg to cover unmasked vnot.v, vncvt.x.x.w, vneg.v, etc.

The mask being NoRegister prevented the existing aliases from matching
since NoRegister isn't in the VMV0 register class.

To workaround this I've added new aliases that look for zero_reg.
I had to motify tablegen to generate matching code for zero_reg.
And as a consequence, I had to change the EmitPriority for an ARM
alias that used zero_reg that started printing.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D121496

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Revision tags: llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3, llvmorg-14.0.0-rc2, llvmorg-14.0.0-rc1, llvmorg-15-init
# b3bec6e4 27-Jan-2022 Craig Topper <craig.topper@sifive.com>

[RISCV] Use vnsrl.wx with x0 instead of vnsrl.vi for truncate.

This matches what the spec uses for the vncvt.x.x.w assembly
pseudoinstruction.

Reviewed By: kito-cheng

Differential Revision: https:

[RISCV] Use vnsrl.wx with x0 instead of vnsrl.vi for truncate.

This matches what the spec uses for the vncvt.x.x.w assembly
pseudoinstruction.

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D118295

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# 3cf15af2 21-Jan-2022 eopXD <eop.chen@sifive.com>

[RISCV] Remove experimental prefix from rvv-related extensions.

Extensions affected: +v, +zve*, +zvl*

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D117860


Revision tags: llvmorg-13.0.1, llvmorg-13.0.1-rc3
# 9c410838 17-Jan-2022 Craig Topper <craig.topper@sifive.com>

[RISCV] Legalize fixed length (insert_subvector undef, X, 0) to a scalable insert.

We were considering this legal, but later the undef would become an all
zeros vector. This would cause us to need t

[RISCV] Legalize fixed length (insert_subvector undef, X, 0) to a scalable insert.

We were considering this legal, but later the undef would become an all
zeros vector. This would cause us to need to re-legalize the insert later
into a vslideup with zero vector.

This patch catches the case and directly legalizes it to a scalable
insert.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D117377

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Revision tags: llvmorg-13.0.1-rc2, llvmorg-13.0.1-rc1
# af0ecfcc 22-Nov-2021 wangpc <pc.wang@linux.alibaba.com>

[RISCV] Generate pseudo instruction li

Add an alias of `addi [x], zero, imm` to generate pseudo
instruction li, which makes assembly mush more readable.
For existed tests, users can update them by r

[RISCV] Generate pseudo instruction li

Add an alias of `addi [x], zero, imm` to generate pseudo
instruction li, which makes assembly mush more readable.
For existed tests, users can update them by running script
`llvm/utils/update_llc_test_checks.py`.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D112692

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# facff468 07-Oct-2021 Hsiangkai Wang <kai.wang@sifive.com>

[RISCV] Reorder the vector register allocation order.

GPR uses argument registers as the first group of registers to allocate.
This patch uses vector argument registers, v8 to v23, as the first grou

[RISCV] Reorder the vector register allocation order.

GPR uses argument registers as the first group of registers to allocate.
This patch uses vector argument registers, v8 to v23, as the first group
to allocate.

Differential Revision: https://reviews.llvm.org/D111304

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Revision tags: llvmorg-13.0.0, llvmorg-13.0.0-rc4, llvmorg-13.0.0-rc3
# 6c7cadb8 09-Sep-2021 Craig Topper <craig.topper@sifive.com>

[RISCV] Teach vsetvli insertion that stores don't use the policy bits in vtype.

This can avoid a vsetvl after a tail undisturbed operation.

Differential Revision: https://reviews.llvm.org/D109549


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