Register list operands are not allowed to contain only a single register. Alternate encodings are used in that case.

llvm-svn: 143552

Fix disassembly of some VST1 instructions.

llvm-svn: 143507

ARM VST1 w/ writeback assembly parsing and encoding.

llvm-svn: 143369

More not-crashing NEON disassembly updates for the vld refactoring.

llvm-svn: 143351

Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle.

llvm-svn: 143208

Add some NEON stores to the VLD decoding hook that were accidentally omitted previously.

llvm-svn: 143162

ARM assembly parsing and encoding for VLD1 with writeback.

Four entry register lists.

llvm-svn: 142882

ARM assembly parsing and encoding for VLD1 w/ writeback.

Three entry register list variation.

llvm-svn: 142876

ARM refactor am6offset usage for VLD1.

Split am6offset into fixed and register offset variants so the instruction
encodings are explicit rather than relying an a magic reg0 marker.
Needed to being a

ARM refactor am6offset usage for VLD1.

Split am6offset into fixed and register offset variants so the instruction
encodings are explicit rather than relying an a magic reg0 marker.
Needed to being able to parse these.

llvm-svn: 142853

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Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely.

llvm-s

Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely.

llvm-svn: 142817

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Move various generated tables into read-only memory, fixing up const correctness along the way.

llvm-svn: 142726

Assembly parsing for 4-register sequential variant of VLD2.

llvm-svn: 142704

Assembly parsing for 2-register sequential variant of VLD2.

llvm-svn: 142691

Assembly parsing for 4-register variant of VLD1.

llvm-svn: 142682

Assembly parsing for 3-register variant of VLD1.

llvm-svn: 142675

ARM VLD parsing and encoding.

Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.

Adjust the instruction definitions

ARM VLD parsing and encoding.

Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.

Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.

llvm-svn: 142670

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Tidy up. Trailing whitespace.

llvm-svn: 142591

Removed set, but unused variables.

Patch by Joe Abbey <jabbey@arxan.com>.

llvm-svn: 142223

Fix a non-firing assert. Change:
assert("bad SymbolicOp.VariantKind");
To:
assert(0 && "bad SymbolicOp.VariantKind");

llvm-svn: 142000

Fix undefined shift. Patch by Ahmed Charles.

llvm-svn: 141914

SETEND is not allowed in an IT block.

llvm-svn: 141874

ARM addrmode5 represents the 'U' bit of the encoding backwards.

The disassembler needs to use the AM5 factory methods instead of just
building up the immediate directly.

llvm-svn: 141819

Thumb2 assembly parsing and encoding for LDC/STC.

llvm-svn: 141811

addrmode2 is gone from these, so no need for the reg0 operand.

llvm-svn: 141794

Fix the check for nested IT instructions in the disassembler. We need to perform the check before adding the Thumb predicate, which pops on entry off the ITBlock queue.

llvm-svn: 141339