1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARM.h" 13 #include "ARMRegisterInfo.h" 14 #include "ARMSubtarget.h" 15 #include "MCTargetDesc/ARMAddressingModes.h" 16 #include "MCTargetDesc/ARMMCExpr.h" 17 #include "MCTargetDesc/ARMBaseInfo.h" 18 #include "llvm/MC/EDInstInfo.h" 19 #include "llvm/MC/MCInst.h" 20 #include "llvm/MC/MCExpr.h" 21 #include "llvm/MC/MCContext.h" 22 #include "llvm/MC/MCDisassembler.h" 23 #include "llvm/Support/Debug.h" 24 #include "llvm/Support/MemoryObject.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include "llvm/Support/raw_ostream.h" 28 29 using namespace llvm; 30 31 typedef MCDisassembler::DecodeStatus DecodeStatus; 32 33 namespace { 34 /// ARMDisassembler - ARM disassembler for all ARM platforms. 35 class ARMDisassembler : public MCDisassembler { 36 public: 37 /// Constructor - Initializes the disassembler. 38 /// 39 ARMDisassembler(const MCSubtargetInfo &STI) : 40 MCDisassembler(STI) { 41 } 42 43 ~ARMDisassembler() { 44 } 45 46 /// getInstruction - See MCDisassembler. 47 DecodeStatus getInstruction(MCInst &instr, 48 uint64_t &size, 49 const MemoryObject ®ion, 50 uint64_t address, 51 raw_ostream &vStream, 52 raw_ostream &cStream) const; 53 54 /// getEDInfo - See MCDisassembler. 55 EDInstInfo *getEDInfo() const; 56 private: 57 }; 58 59 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 60 class ThumbDisassembler : public MCDisassembler { 61 public: 62 /// Constructor - Initializes the disassembler. 63 /// 64 ThumbDisassembler(const MCSubtargetInfo &STI) : 65 MCDisassembler(STI) { 66 } 67 68 ~ThumbDisassembler() { 69 } 70 71 /// getInstruction - See MCDisassembler. 72 DecodeStatus getInstruction(MCInst &instr, 73 uint64_t &size, 74 const MemoryObject ®ion, 75 uint64_t address, 76 raw_ostream &vStream, 77 raw_ostream &cStream) const; 78 79 /// getEDInfo - See MCDisassembler. 80 EDInstInfo *getEDInfo() const; 81 private: 82 mutable std::vector<unsigned> ITBlock; 83 DecodeStatus AddThumbPredicate(MCInst&) const; 84 void UpdateThumbVFPPredicate(MCInst&) const; 85 }; 86 } 87 88 static bool Check(DecodeStatus &Out, DecodeStatus In) { 89 switch (In) { 90 case MCDisassembler::Success: 91 // Out stays the same. 92 return true; 93 case MCDisassembler::SoftFail: 94 Out = In; 95 return true; 96 case MCDisassembler::Fail: 97 Out = In; 98 return false; 99 } 100 return false; 101 } 102 103 104 // Forward declare these because the autogenerated code will reference them. 105 // Definitions are further down. 106 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 107 uint64_t Address, const void *Decoder); 108 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, 109 unsigned RegNo, uint64_t Address, 110 const void *Decoder); 111 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 112 uint64_t Address, const void *Decoder); 113 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 114 uint64_t Address, const void *Decoder); 115 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 116 uint64_t Address, const void *Decoder); 117 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 118 uint64_t Address, const void *Decoder); 119 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 120 uint64_t Address, const void *Decoder); 121 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 122 uint64_t Address, const void *Decoder); 123 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, 124 unsigned RegNo, 125 uint64_t Address, 126 const void *Decoder); 127 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 128 uint64_t Address, const void *Decoder); 129 130 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 131 uint64_t Address, const void *Decoder); 132 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 133 uint64_t Address, const void *Decoder); 134 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 135 uint64_t Address, const void *Decoder); 136 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 137 uint64_t Address, const void *Decoder); 138 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 139 uint64_t Address, const void *Decoder); 140 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 141 uint64_t Address, const void *Decoder); 142 143 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 144 uint64_t Address, const void *Decoder); 145 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 146 uint64_t Address, const void *Decoder); 147 static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, 148 unsigned Insn, 149 uint64_t Address, 150 const void *Decoder); 151 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 152 uint64_t Address, const void *Decoder); 153 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn, 154 uint64_t Address, const void *Decoder); 155 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 156 uint64_t Address, const void *Decoder); 157 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 158 uint64_t Address, const void *Decoder); 159 160 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 161 unsigned Insn, 162 uint64_t Adddress, 163 const void *Decoder); 164 static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 165 uint64_t Address, const void *Decoder); 166 static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 167 uint64_t Address, const void *Decoder); 168 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 171 uint64_t Address, const void *Decoder); 172 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 173 uint64_t Address, const void *Decoder); 174 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 175 uint64_t Address, const void *Decoder); 176 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 177 uint64_t Address, const void *Decoder); 178 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 179 uint64_t Address, const void *Decoder); 180 static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 185 uint64_t Address, const void *Decoder); 186 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 197 uint64_t Address, const void *Decoder); 198 static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val, 199 uint64_t Address, const void *Decoder); 200 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 201 uint64_t Address, const void *Decoder); 202 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 203 uint64_t Address, const void *Decoder); 204 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 205 uint64_t Address, const void *Decoder); 206 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 207 uint64_t Address, const void *Decoder); 208 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 209 uint64_t Address, const void *Decoder); 210 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 211 uint64_t Address, const void *Decoder); 212 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 213 uint64_t Address, const void *Decoder); 214 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 215 uint64_t Address, const void *Decoder); 216 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 217 uint64_t Address, const void *Decoder); 218 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 219 uint64_t Address, const void *Decoder); 220 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 221 uint64_t Address, const void *Decoder); 222 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 223 uint64_t Address, const void *Decoder); 224 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 225 uint64_t Address, const void *Decoder); 226 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 231 uint64_t Address, const void *Decoder); 232 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 233 uint64_t Address, const void *Decoder); 234 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 237 uint64_t Address, const void *Decoder); 238 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 239 uint64_t Address, const void *Decoder); 240 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 251 uint64_t Address, const void *Decoder); 252 253 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 254 uint64_t Address, const void *Decoder); 255 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 256 uint64_t Address, const void *Decoder); 257 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 258 uint64_t Address, const void *Decoder); 259 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 260 uint64_t Address, const void *Decoder); 261 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 262 uint64_t Address, const void *Decoder); 263 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 264 uint64_t Address, const void *Decoder); 265 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 266 uint64_t Address, const void *Decoder); 267 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 268 uint64_t Address, const void *Decoder); 269 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 270 uint64_t Address, const void *Decoder); 271 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 272 uint64_t Address, const void *Decoder); 273 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 274 uint64_t Address, const void *Decoder); 275 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 276 uint64_t Address, const void *Decoder); 277 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, 278 uint64_t Address, const void *Decoder); 279 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 280 uint64_t Address, const void *Decoder); 281 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 282 uint64_t Address, const void *Decoder); 283 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 284 uint64_t Address, const void *Decoder); 285 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 286 uint64_t Address, const void *Decoder); 287 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 288 uint64_t Address, const void *Decoder); 289 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 290 uint64_t Address, const void *Decoder); 291 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 292 uint64_t Address, const void *Decoder); 293 static DecodeStatus DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Val, 294 uint64_t Address, const void *Decoder); 295 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 296 uint64_t Address, const void *Decoder); 297 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 298 uint64_t Address, const void *Decoder); 299 static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val, 300 uint64_t Address, const void *Decoder); 301 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 302 uint64_t Address, const void *Decoder); 303 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val, 304 uint64_t Address, const void *Decoder); 305 static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 306 uint64_t Address, const void *Decoder); 307 static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 308 uint64_t Address, const void *Decoder); 309 static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val, 310 uint64_t Address, const void *Decoder); 311 static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val, 312 uint64_t Address, const void *Decoder); 313 static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, unsigned Val, 314 uint64_t Address, const void *Decoder); 315 316 317 318 #include "ARMGenDisassemblerTables.inc" 319 #include "ARMGenInstrInfo.inc" 320 #include "ARMGenEDInfo.inc" 321 322 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 323 return new ARMDisassembler(STI); 324 } 325 326 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 327 return new ThumbDisassembler(STI); 328 } 329 330 EDInstInfo *ARMDisassembler::getEDInfo() const { 331 return instInfoARM; 332 } 333 334 EDInstInfo *ThumbDisassembler::getEDInfo() const { 335 return instInfoARM; 336 } 337 338 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 339 const MemoryObject &Region, 340 uint64_t Address, 341 raw_ostream &os, 342 raw_ostream &cs) const { 343 CommentStream = &cs; 344 345 uint8_t bytes[4]; 346 347 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 348 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 349 350 // We want to read exactly 4 bytes of data. 351 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 352 Size = 0; 353 return MCDisassembler::Fail; 354 } 355 356 // Encoded as a small-endian 32-bit word in the stream. 357 uint32_t insn = (bytes[3] << 24) | 358 (bytes[2] << 16) | 359 (bytes[1] << 8) | 360 (bytes[0] << 0); 361 362 // Calling the auto-generated decoder function. 363 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI); 364 if (result != MCDisassembler::Fail) { 365 Size = 4; 366 return result; 367 } 368 369 // VFP and NEON instructions, similarly, are shared between ARM 370 // and Thumb modes. 371 MI.clear(); 372 result = decodeVFPInstruction32(MI, insn, Address, this, STI); 373 if (result != MCDisassembler::Fail) { 374 Size = 4; 375 return result; 376 } 377 378 MI.clear(); 379 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI); 380 if (result != MCDisassembler::Fail) { 381 Size = 4; 382 // Add a fake predicate operand, because we share these instruction 383 // definitions with Thumb2 where these instructions are predicable. 384 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 385 return MCDisassembler::Fail; 386 return result; 387 } 388 389 MI.clear(); 390 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI); 391 if (result != MCDisassembler::Fail) { 392 Size = 4; 393 // Add a fake predicate operand, because we share these instruction 394 // definitions with Thumb2 where these instructions are predicable. 395 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 396 return MCDisassembler::Fail; 397 return result; 398 } 399 400 MI.clear(); 401 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI); 402 if (result != MCDisassembler::Fail) { 403 Size = 4; 404 // Add a fake predicate operand, because we share these instruction 405 // definitions with Thumb2 where these instructions are predicable. 406 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 407 return MCDisassembler::Fail; 408 return result; 409 } 410 411 MI.clear(); 412 413 Size = 0; 414 return MCDisassembler::Fail; 415 } 416 417 namespace llvm { 418 extern const MCInstrDesc ARMInsts[]; 419 } 420 421 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 422 /// immediate Value in the MCInst. The immediate Value has had any PC 423 /// adjustment made by the caller. If the instruction is a branch instruction 424 /// then isBranch is true, else false. If the getOpInfo() function was set as 425 /// part of the setupForSymbolicDisassembly() call then that function is called 426 /// to get any symbolic information at the Address for this instruction. If 427 /// that returns non-zero then the symbolic information it returns is used to 428 /// create an MCExpr and that is added as an operand to the MCInst. If 429 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 430 /// Value is done and if a symbol is found an MCExpr is created with that, else 431 /// an MCExpr with Value is created. This function returns true if it adds an 432 /// operand to the MCInst and false otherwise. 433 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 434 bool isBranch, uint64_t InstSize, 435 MCInst &MI, const void *Decoder) { 436 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 437 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback(); 438 if (!getOpInfo) 439 return false; 440 441 struct LLVMOpInfo1 SymbolicOp; 442 SymbolicOp.Value = Value; 443 void *DisInfo = Dis->getDisInfoBlock(); 444 if (!getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) { 445 if (isBranch) { 446 LLVMSymbolLookupCallback SymbolLookUp = 447 Dis->getLLVMSymbolLookupCallback(); 448 if (SymbolLookUp) { 449 uint64_t ReferenceType; 450 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch; 451 const char *ReferenceName; 452 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address, 453 &ReferenceName); 454 if (Name) { 455 SymbolicOp.AddSymbol.Name = Name; 456 SymbolicOp.AddSymbol.Present = true; 457 SymbolicOp.Value = 0; 458 } 459 else { 460 SymbolicOp.Value = Value; 461 } 462 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub) 463 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName; 464 } 465 else { 466 return false; 467 } 468 } 469 else { 470 return false; 471 } 472 } 473 474 MCContext *Ctx = Dis->getMCContext(); 475 const MCExpr *Add = NULL; 476 if (SymbolicOp.AddSymbol.Present) { 477 if (SymbolicOp.AddSymbol.Name) { 478 StringRef Name(SymbolicOp.AddSymbol.Name); 479 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 480 Add = MCSymbolRefExpr::Create(Sym, *Ctx); 481 } else { 482 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx); 483 } 484 } 485 486 const MCExpr *Sub = NULL; 487 if (SymbolicOp.SubtractSymbol.Present) { 488 if (SymbolicOp.SubtractSymbol.Name) { 489 StringRef Name(SymbolicOp.SubtractSymbol.Name); 490 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 491 Sub = MCSymbolRefExpr::Create(Sym, *Ctx); 492 } else { 493 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx); 494 } 495 } 496 497 const MCExpr *Off = NULL; 498 if (SymbolicOp.Value != 0) 499 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx); 500 501 const MCExpr *Expr; 502 if (Sub) { 503 const MCExpr *LHS; 504 if (Add) 505 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx); 506 else 507 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx); 508 if (Off != 0) 509 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx); 510 else 511 Expr = LHS; 512 } else if (Add) { 513 if (Off != 0) 514 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx); 515 else 516 Expr = Add; 517 } else { 518 if (Off != 0) 519 Expr = Off; 520 else 521 Expr = MCConstantExpr::Create(0, *Ctx); 522 } 523 524 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16) 525 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx))); 526 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16) 527 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx))); 528 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None) 529 MI.addOperand(MCOperand::CreateExpr(Expr)); 530 else 531 assert(0 && "bad SymbolicOp.VariantKind"); 532 533 return true; 534 } 535 536 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 537 /// referenced by a load instruction with the base register that is the Pc. 538 /// These can often be values in a literal pool near the Address of the 539 /// instruction. The Address of the instruction and its immediate Value are 540 /// used as a possible literal pool entry. The SymbolLookUp call back will 541 /// return the name of a symbol referenced by the the literal pool's entry if 542 /// the referenced address is that of a symbol. Or it will return a pointer to 543 /// a literal 'C' string if the referenced address of the literal pool's entry 544 /// is an address into a section with 'C' string literals. 545 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 546 const void *Decoder) { 547 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 548 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 549 if (SymbolLookUp) { 550 void *DisInfo = Dis->getDisInfoBlock(); 551 uint64_t ReferenceType; 552 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load; 553 const char *ReferenceName; 554 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName); 555 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr || 556 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr) 557 (*Dis->CommentStream) << "literal pool for: " << ReferenceName; 558 } 559 } 560 561 // Thumb1 instructions don't have explicit S bits. Rather, they 562 // implicitly set CPSR. Since it's not represented in the encoding, the 563 // auto-generated decoder won't inject the CPSR operand. We need to fix 564 // that as a post-pass. 565 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 566 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 567 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 568 MCInst::iterator I = MI.begin(); 569 for (unsigned i = 0; i < NumOps; ++i, ++I) { 570 if (I == MI.end()) break; 571 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 572 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 573 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 574 return; 575 } 576 } 577 578 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 579 } 580 581 // Most Thumb instructions don't have explicit predicates in the 582 // encoding, but rather get their predicates from IT context. We need 583 // to fix up the predicate operands using this context information as a 584 // post-pass. 585 MCDisassembler::DecodeStatus 586 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 587 MCDisassembler::DecodeStatus S = Success; 588 589 // A few instructions actually have predicates encoded in them. Don't 590 // try to overwrite it if we're seeing one of those. 591 switch (MI.getOpcode()) { 592 case ARM::tBcc: 593 case ARM::t2Bcc: 594 case ARM::tCBZ: 595 case ARM::tCBNZ: 596 case ARM::tCPS: 597 case ARM::t2CPS3p: 598 case ARM::t2CPS2p: 599 case ARM::t2CPS1p: 600 case ARM::tMOVSr: 601 case ARM::tSETEND: 602 // Some instructions (mostly conditional branches) are not 603 // allowed in IT blocks. 604 if (!ITBlock.empty()) 605 S = SoftFail; 606 else 607 return Success; 608 break; 609 case ARM::tB: 610 case ARM::t2B: 611 case ARM::t2TBB: 612 case ARM::t2TBH: 613 // Some instructions (mostly unconditional branches) can 614 // only appears at the end of, or outside of, an IT. 615 if (ITBlock.size() > 1) 616 S = SoftFail; 617 break; 618 default: 619 break; 620 } 621 622 // If we're in an IT block, base the predicate on that. Otherwise, 623 // assume a predicate of AL. 624 unsigned CC; 625 if (!ITBlock.empty()) { 626 CC = ITBlock.back(); 627 if (CC == 0xF) 628 CC = ARMCC::AL; 629 ITBlock.pop_back(); 630 } else 631 CC = ARMCC::AL; 632 633 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 634 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 635 MCInst::iterator I = MI.begin(); 636 for (unsigned i = 0; i < NumOps; ++i, ++I) { 637 if (I == MI.end()) break; 638 if (OpInfo[i].isPredicate()) { 639 I = MI.insert(I, MCOperand::CreateImm(CC)); 640 ++I; 641 if (CC == ARMCC::AL) 642 MI.insert(I, MCOperand::CreateReg(0)); 643 else 644 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 645 return S; 646 } 647 } 648 649 I = MI.insert(I, MCOperand::CreateImm(CC)); 650 ++I; 651 if (CC == ARMCC::AL) 652 MI.insert(I, MCOperand::CreateReg(0)); 653 else 654 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 655 656 return S; 657 } 658 659 // Thumb VFP instructions are a special case. Because we share their 660 // encodings between ARM and Thumb modes, and they are predicable in ARM 661 // mode, the auto-generated decoder will give them an (incorrect) 662 // predicate operand. We need to rewrite these operands based on the IT 663 // context as a post-pass. 664 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 665 unsigned CC; 666 if (!ITBlock.empty()) { 667 CC = ITBlock.back(); 668 ITBlock.pop_back(); 669 } else 670 CC = ARMCC::AL; 671 672 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 673 MCInst::iterator I = MI.begin(); 674 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 675 for (unsigned i = 0; i < NumOps; ++i, ++I) { 676 if (OpInfo[i].isPredicate() ) { 677 I->setImm(CC); 678 ++I; 679 if (CC == ARMCC::AL) 680 I->setReg(0); 681 else 682 I->setReg(ARM::CPSR); 683 return; 684 } 685 } 686 } 687 688 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 689 const MemoryObject &Region, 690 uint64_t Address, 691 raw_ostream &os, 692 raw_ostream &cs) const { 693 CommentStream = &cs; 694 695 uint8_t bytes[4]; 696 697 assert((STI.getFeatureBits() & ARM::ModeThumb) && 698 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 699 700 // We want to read exactly 2 bytes of data. 701 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 702 Size = 0; 703 return MCDisassembler::Fail; 704 } 705 706 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 707 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI); 708 if (result != MCDisassembler::Fail) { 709 Size = 2; 710 Check(result, AddThumbPredicate(MI)); 711 return result; 712 } 713 714 MI.clear(); 715 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI); 716 if (result) { 717 Size = 2; 718 bool InITBlock = !ITBlock.empty(); 719 Check(result, AddThumbPredicate(MI)); 720 AddThumb1SBit(MI, InITBlock); 721 return result; 722 } 723 724 MI.clear(); 725 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI); 726 if (result != MCDisassembler::Fail) { 727 Size = 2; 728 729 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 730 // the Thumb predicate. 731 if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty()) 732 result = MCDisassembler::SoftFail; 733 734 Check(result, AddThumbPredicate(MI)); 735 736 // If we find an IT instruction, we need to parse its condition 737 // code and mask operands so that we can apply them correctly 738 // to the subsequent instructions. 739 if (MI.getOpcode() == ARM::t2IT) { 740 741 // (3 - the number of trailing zeros) is the number of then / else. 742 unsigned firstcond = MI.getOperand(0).getImm(); 743 unsigned Mask = MI.getOperand(1).getImm(); 744 unsigned CondBit0 = Mask >> 4 & 1; 745 unsigned NumTZ = CountTrailingZeros_32(Mask); 746 assert(NumTZ <= 3 && "Invalid IT mask!"); 747 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { 748 bool T = ((Mask >> Pos) & 1) == CondBit0; 749 if (T) 750 ITBlock.insert(ITBlock.begin(), firstcond); 751 else 752 ITBlock.insert(ITBlock.begin(), firstcond ^ 1); 753 } 754 755 ITBlock.push_back(firstcond); 756 } 757 758 return result; 759 } 760 761 // We want to read exactly 4 bytes of data. 762 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 763 Size = 0; 764 return MCDisassembler::Fail; 765 } 766 767 uint32_t insn32 = (bytes[3] << 8) | 768 (bytes[2] << 0) | 769 (bytes[1] << 24) | 770 (bytes[0] << 16); 771 MI.clear(); 772 result = decodeThumbInstruction32(MI, insn32, Address, this, STI); 773 if (result != MCDisassembler::Fail) { 774 Size = 4; 775 bool InITBlock = ITBlock.size(); 776 Check(result, AddThumbPredicate(MI)); 777 AddThumb1SBit(MI, InITBlock); 778 return result; 779 } 780 781 MI.clear(); 782 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI); 783 if (result != MCDisassembler::Fail) { 784 Size = 4; 785 Check(result, AddThumbPredicate(MI)); 786 return result; 787 } 788 789 MI.clear(); 790 result = decodeVFPInstruction32(MI, insn32, Address, this, STI); 791 if (result != MCDisassembler::Fail) { 792 Size = 4; 793 UpdateThumbVFPPredicate(MI); 794 return result; 795 } 796 797 MI.clear(); 798 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI); 799 if (result != MCDisassembler::Fail) { 800 Size = 4; 801 Check(result, AddThumbPredicate(MI)); 802 return result; 803 } 804 805 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 806 MI.clear(); 807 uint32_t NEONLdStInsn = insn32; 808 NEONLdStInsn &= 0xF0FFFFFF; 809 NEONLdStInsn |= 0x04000000; 810 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI); 811 if (result != MCDisassembler::Fail) { 812 Size = 4; 813 Check(result, AddThumbPredicate(MI)); 814 return result; 815 } 816 } 817 818 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 819 MI.clear(); 820 uint32_t NEONDataInsn = insn32; 821 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 822 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 823 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 824 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI); 825 if (result != MCDisassembler::Fail) { 826 Size = 4; 827 Check(result, AddThumbPredicate(MI)); 828 return result; 829 } 830 } 831 832 Size = 0; 833 return MCDisassembler::Fail; 834 } 835 836 837 extern "C" void LLVMInitializeARMDisassembler() { 838 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 839 createARMDisassembler); 840 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 841 createThumbDisassembler); 842 } 843 844 static const unsigned GPRDecoderTable[] = { 845 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 846 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 847 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 848 ARM::R12, ARM::SP, ARM::LR, ARM::PC 849 }; 850 851 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 852 uint64_t Address, const void *Decoder) { 853 if (RegNo > 15) 854 return MCDisassembler::Fail; 855 856 unsigned Register = GPRDecoderTable[RegNo]; 857 Inst.addOperand(MCOperand::CreateReg(Register)); 858 return MCDisassembler::Success; 859 } 860 861 static DecodeStatus 862 DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 863 uint64_t Address, const void *Decoder) { 864 if (RegNo == 15) return MCDisassembler::Fail; 865 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 866 } 867 868 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 869 uint64_t Address, const void *Decoder) { 870 if (RegNo > 7) 871 return MCDisassembler::Fail; 872 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 873 } 874 875 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 876 uint64_t Address, const void *Decoder) { 877 unsigned Register = 0; 878 switch (RegNo) { 879 case 0: 880 Register = ARM::R0; 881 break; 882 case 1: 883 Register = ARM::R1; 884 break; 885 case 2: 886 Register = ARM::R2; 887 break; 888 case 3: 889 Register = ARM::R3; 890 break; 891 case 9: 892 Register = ARM::R9; 893 break; 894 case 12: 895 Register = ARM::R12; 896 break; 897 default: 898 return MCDisassembler::Fail; 899 } 900 901 Inst.addOperand(MCOperand::CreateReg(Register)); 902 return MCDisassembler::Success; 903 } 904 905 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 906 uint64_t Address, const void *Decoder) { 907 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 908 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 909 } 910 911 static const unsigned SPRDecoderTable[] = { 912 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 913 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 914 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 915 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 916 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 917 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 918 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 919 ARM::S28, ARM::S29, ARM::S30, ARM::S31 920 }; 921 922 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 923 uint64_t Address, const void *Decoder) { 924 if (RegNo > 31) 925 return MCDisassembler::Fail; 926 927 unsigned Register = SPRDecoderTable[RegNo]; 928 Inst.addOperand(MCOperand::CreateReg(Register)); 929 return MCDisassembler::Success; 930 } 931 932 static const unsigned DPRDecoderTable[] = { 933 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 934 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 935 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 936 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 937 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 938 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 939 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 940 ARM::D28, ARM::D29, ARM::D30, ARM::D31 941 }; 942 943 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 944 uint64_t Address, const void *Decoder) { 945 if (RegNo > 31) 946 return MCDisassembler::Fail; 947 948 unsigned Register = DPRDecoderTable[RegNo]; 949 Inst.addOperand(MCOperand::CreateReg(Register)); 950 return MCDisassembler::Success; 951 } 952 953 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 954 uint64_t Address, const void *Decoder) { 955 if (RegNo > 7) 956 return MCDisassembler::Fail; 957 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 958 } 959 960 static DecodeStatus 961 DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 962 uint64_t Address, const void *Decoder) { 963 if (RegNo > 15) 964 return MCDisassembler::Fail; 965 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 966 } 967 968 static const unsigned QPRDecoderTable[] = { 969 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 970 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 971 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 972 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 973 }; 974 975 976 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 977 uint64_t Address, const void *Decoder) { 978 if (RegNo > 31) 979 return MCDisassembler::Fail; 980 RegNo >>= 1; 981 982 unsigned Register = QPRDecoderTable[RegNo]; 983 Inst.addOperand(MCOperand::CreateReg(Register)); 984 return MCDisassembler::Success; 985 } 986 987 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 988 uint64_t Address, const void *Decoder) { 989 if (Val == 0xF) return MCDisassembler::Fail; 990 // AL predicate is not allowed on Thumb1 branches. 991 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 992 return MCDisassembler::Fail; 993 Inst.addOperand(MCOperand::CreateImm(Val)); 994 if (Val == ARMCC::AL) { 995 Inst.addOperand(MCOperand::CreateReg(0)); 996 } else 997 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 998 return MCDisassembler::Success; 999 } 1000 1001 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 1002 uint64_t Address, const void *Decoder) { 1003 if (Val) 1004 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1005 else 1006 Inst.addOperand(MCOperand::CreateReg(0)); 1007 return MCDisassembler::Success; 1008 } 1009 1010 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 1011 uint64_t Address, const void *Decoder) { 1012 uint32_t imm = Val & 0xFF; 1013 uint32_t rot = (Val & 0xF00) >> 7; 1014 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1015 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1016 return MCDisassembler::Success; 1017 } 1018 1019 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 1020 uint64_t Address, const void *Decoder) { 1021 DecodeStatus S = MCDisassembler::Success; 1022 1023 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1024 unsigned type = fieldFromInstruction32(Val, 5, 2); 1025 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1026 1027 // Register-immediate 1028 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1029 return MCDisassembler::Fail; 1030 1031 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1032 switch (type) { 1033 case 0: 1034 Shift = ARM_AM::lsl; 1035 break; 1036 case 1: 1037 Shift = ARM_AM::lsr; 1038 break; 1039 case 2: 1040 Shift = ARM_AM::asr; 1041 break; 1042 case 3: 1043 Shift = ARM_AM::ror; 1044 break; 1045 } 1046 1047 if (Shift == ARM_AM::ror && imm == 0) 1048 Shift = ARM_AM::rrx; 1049 1050 unsigned Op = Shift | (imm << 3); 1051 Inst.addOperand(MCOperand::CreateImm(Op)); 1052 1053 return S; 1054 } 1055 1056 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 1057 uint64_t Address, const void *Decoder) { 1058 DecodeStatus S = MCDisassembler::Success; 1059 1060 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1061 unsigned type = fieldFromInstruction32(Val, 5, 2); 1062 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 1063 1064 // Register-register 1065 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1066 return MCDisassembler::Fail; 1067 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1068 return MCDisassembler::Fail; 1069 1070 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1071 switch (type) { 1072 case 0: 1073 Shift = ARM_AM::lsl; 1074 break; 1075 case 1: 1076 Shift = ARM_AM::lsr; 1077 break; 1078 case 2: 1079 Shift = ARM_AM::asr; 1080 break; 1081 case 3: 1082 Shift = ARM_AM::ror; 1083 break; 1084 } 1085 1086 Inst.addOperand(MCOperand::CreateImm(Shift)); 1087 1088 return S; 1089 } 1090 1091 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 1092 uint64_t Address, const void *Decoder) { 1093 DecodeStatus S = MCDisassembler::Success; 1094 1095 bool writebackLoad = false; 1096 unsigned writebackReg = 0; 1097 switch (Inst.getOpcode()) { 1098 default: 1099 break; 1100 case ARM::LDMIA_UPD: 1101 case ARM::LDMDB_UPD: 1102 case ARM::LDMIB_UPD: 1103 case ARM::LDMDA_UPD: 1104 case ARM::t2LDMIA_UPD: 1105 case ARM::t2LDMDB_UPD: 1106 writebackLoad = true; 1107 writebackReg = Inst.getOperand(0).getReg(); 1108 break; 1109 } 1110 1111 // Empty register lists are not allowed. 1112 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; 1113 for (unsigned i = 0; i < 16; ++i) { 1114 if (Val & (1 << i)) { 1115 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1116 return MCDisassembler::Fail; 1117 // Writeback not allowed if Rn is in the target list. 1118 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 1119 Check(S, MCDisassembler::SoftFail); 1120 } 1121 } 1122 1123 return S; 1124 } 1125 1126 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 1127 uint64_t Address, const void *Decoder) { 1128 DecodeStatus S = MCDisassembler::Success; 1129 1130 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 1131 unsigned regs = Val & 0xFF; 1132 1133 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1134 return MCDisassembler::Fail; 1135 for (unsigned i = 0; i < (regs - 1); ++i) { 1136 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1137 return MCDisassembler::Fail; 1138 } 1139 1140 return S; 1141 } 1142 1143 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 1144 uint64_t Address, const void *Decoder) { 1145 DecodeStatus S = MCDisassembler::Success; 1146 1147 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 1148 unsigned regs = (Val & 0xFF) / 2; 1149 1150 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1151 return MCDisassembler::Fail; 1152 for (unsigned i = 0; i < (regs - 1); ++i) { 1153 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1154 return MCDisassembler::Fail; 1155 } 1156 1157 return S; 1158 } 1159 1160 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 1161 uint64_t Address, const void *Decoder) { 1162 // This operand encodes a mask of contiguous zeros between a specified MSB 1163 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1164 // the mask of all bits LSB-and-lower, and then xor them to create 1165 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1166 // create the final mask. 1167 unsigned msb = fieldFromInstruction32(Val, 5, 5); 1168 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 1169 1170 DecodeStatus S = MCDisassembler::Success; 1171 if (lsb > msb) Check(S, MCDisassembler::SoftFail); 1172 1173 uint32_t msb_mask = 0xFFFFFFFF; 1174 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1175 uint32_t lsb_mask = (1U << lsb) - 1; 1176 1177 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1178 return S; 1179 } 1180 1181 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 1182 uint64_t Address, const void *Decoder) { 1183 DecodeStatus S = MCDisassembler::Success; 1184 1185 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1186 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 1187 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 1188 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 1189 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1190 unsigned U = fieldFromInstruction32(Insn, 23, 1); 1191 1192 switch (Inst.getOpcode()) { 1193 case ARM::LDC_OFFSET: 1194 case ARM::LDC_PRE: 1195 case ARM::LDC_POST: 1196 case ARM::LDC_OPTION: 1197 case ARM::LDCL_OFFSET: 1198 case ARM::LDCL_PRE: 1199 case ARM::LDCL_POST: 1200 case ARM::LDCL_OPTION: 1201 case ARM::STC_OFFSET: 1202 case ARM::STC_PRE: 1203 case ARM::STC_POST: 1204 case ARM::STC_OPTION: 1205 case ARM::STCL_OFFSET: 1206 case ARM::STCL_PRE: 1207 case ARM::STCL_POST: 1208 case ARM::STCL_OPTION: 1209 case ARM::t2LDC_OFFSET: 1210 case ARM::t2LDC_PRE: 1211 case ARM::t2LDC_POST: 1212 case ARM::t2LDC_OPTION: 1213 case ARM::t2LDCL_OFFSET: 1214 case ARM::t2LDCL_PRE: 1215 case ARM::t2LDCL_POST: 1216 case ARM::t2LDCL_OPTION: 1217 case ARM::t2STC_OFFSET: 1218 case ARM::t2STC_PRE: 1219 case ARM::t2STC_POST: 1220 case ARM::t2STC_OPTION: 1221 case ARM::t2STCL_OFFSET: 1222 case ARM::t2STCL_PRE: 1223 case ARM::t2STCL_POST: 1224 case ARM::t2STCL_OPTION: 1225 if (coproc == 0xA || coproc == 0xB) 1226 return MCDisassembler::Fail; 1227 break; 1228 default: 1229 break; 1230 } 1231 1232 Inst.addOperand(MCOperand::CreateImm(coproc)); 1233 Inst.addOperand(MCOperand::CreateImm(CRd)); 1234 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1235 return MCDisassembler::Fail; 1236 1237 switch (Inst.getOpcode()) { 1238 case ARM::t2LDC2_OFFSET: 1239 case ARM::t2LDC2L_OFFSET: 1240 case ARM::t2LDC2_PRE: 1241 case ARM::t2LDC2L_PRE: 1242 case ARM::t2STC2_OFFSET: 1243 case ARM::t2STC2L_OFFSET: 1244 case ARM::t2STC2_PRE: 1245 case ARM::t2STC2L_PRE: 1246 case ARM::LDC2_OFFSET: 1247 case ARM::LDC2L_OFFSET: 1248 case ARM::LDC2_PRE: 1249 case ARM::LDC2L_PRE: 1250 case ARM::STC2_OFFSET: 1251 case ARM::STC2L_OFFSET: 1252 case ARM::STC2_PRE: 1253 case ARM::STC2L_PRE: 1254 case ARM::t2LDC_OFFSET: 1255 case ARM::t2LDCL_OFFSET: 1256 case ARM::t2LDC_PRE: 1257 case ARM::t2LDCL_PRE: 1258 case ARM::t2STC_OFFSET: 1259 case ARM::t2STCL_OFFSET: 1260 case ARM::t2STC_PRE: 1261 case ARM::t2STCL_PRE: 1262 case ARM::LDC_OFFSET: 1263 case ARM::LDCL_OFFSET: 1264 case ARM::LDC_PRE: 1265 case ARM::LDCL_PRE: 1266 case ARM::STC_OFFSET: 1267 case ARM::STCL_OFFSET: 1268 case ARM::STC_PRE: 1269 case ARM::STCL_PRE: 1270 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1271 Inst.addOperand(MCOperand::CreateImm(imm)); 1272 break; 1273 case ARM::t2LDC2_POST: 1274 case ARM::t2LDC2L_POST: 1275 case ARM::t2STC2_POST: 1276 case ARM::t2STC2L_POST: 1277 case ARM::LDC2_POST: 1278 case ARM::LDC2L_POST: 1279 case ARM::STC2_POST: 1280 case ARM::STC2L_POST: 1281 case ARM::t2LDC_POST: 1282 case ARM::t2LDCL_POST: 1283 case ARM::t2STC_POST: 1284 case ARM::t2STCL_POST: 1285 case ARM::LDC_POST: 1286 case ARM::LDCL_POST: 1287 case ARM::STC_POST: 1288 case ARM::STCL_POST: 1289 imm |= U << 8; 1290 // fall through. 1291 default: 1292 // The 'option' variant doesn't encode 'U' in the immediate since 1293 // the immediate is unsigned [0,255]. 1294 Inst.addOperand(MCOperand::CreateImm(imm)); 1295 break; 1296 } 1297 1298 switch (Inst.getOpcode()) { 1299 case ARM::LDC_OFFSET: 1300 case ARM::LDC_PRE: 1301 case ARM::LDC_POST: 1302 case ARM::LDC_OPTION: 1303 case ARM::LDCL_OFFSET: 1304 case ARM::LDCL_PRE: 1305 case ARM::LDCL_POST: 1306 case ARM::LDCL_OPTION: 1307 case ARM::STC_OFFSET: 1308 case ARM::STC_PRE: 1309 case ARM::STC_POST: 1310 case ARM::STC_OPTION: 1311 case ARM::STCL_OFFSET: 1312 case ARM::STCL_PRE: 1313 case ARM::STCL_POST: 1314 case ARM::STCL_OPTION: 1315 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1316 return MCDisassembler::Fail; 1317 break; 1318 default: 1319 break; 1320 } 1321 1322 return S; 1323 } 1324 1325 static DecodeStatus 1326 DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 1327 uint64_t Address, const void *Decoder) { 1328 DecodeStatus S = MCDisassembler::Success; 1329 1330 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1331 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1332 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1333 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 1334 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1335 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 1336 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1337 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1338 1339 // On stores, the writeback operand precedes Rt. 1340 switch (Inst.getOpcode()) { 1341 case ARM::STR_POST_IMM: 1342 case ARM::STR_POST_REG: 1343 case ARM::STRB_POST_IMM: 1344 case ARM::STRB_POST_REG: 1345 case ARM::STRT_POST_REG: 1346 case ARM::STRT_POST_IMM: 1347 case ARM::STRBT_POST_REG: 1348 case ARM::STRBT_POST_IMM: 1349 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1350 return MCDisassembler::Fail; 1351 break; 1352 default: 1353 break; 1354 } 1355 1356 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1357 return MCDisassembler::Fail; 1358 1359 // On loads, the writeback operand comes after Rt. 1360 switch (Inst.getOpcode()) { 1361 case ARM::LDR_POST_IMM: 1362 case ARM::LDR_POST_REG: 1363 case ARM::LDRB_POST_IMM: 1364 case ARM::LDRB_POST_REG: 1365 case ARM::LDRBT_POST_REG: 1366 case ARM::LDRBT_POST_IMM: 1367 case ARM::LDRT_POST_REG: 1368 case ARM::LDRT_POST_IMM: 1369 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1370 return MCDisassembler::Fail; 1371 break; 1372 default: 1373 break; 1374 } 1375 1376 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1377 return MCDisassembler::Fail; 1378 1379 ARM_AM::AddrOpc Op = ARM_AM::add; 1380 if (!fieldFromInstruction32(Insn, 23, 1)) 1381 Op = ARM_AM::sub; 1382 1383 bool writeback = (P == 0) || (W == 1); 1384 unsigned idx_mode = 0; 1385 if (P && writeback) 1386 idx_mode = ARMII::IndexModePre; 1387 else if (!P && writeback) 1388 idx_mode = ARMII::IndexModePost; 1389 1390 if (writeback && (Rn == 15 || Rn == Rt)) 1391 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1392 1393 if (reg) { 1394 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1395 return MCDisassembler::Fail; 1396 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1397 switch( fieldFromInstruction32(Insn, 5, 2)) { 1398 case 0: 1399 Opc = ARM_AM::lsl; 1400 break; 1401 case 1: 1402 Opc = ARM_AM::lsr; 1403 break; 1404 case 2: 1405 Opc = ARM_AM::asr; 1406 break; 1407 case 3: 1408 Opc = ARM_AM::ror; 1409 break; 1410 default: 1411 return MCDisassembler::Fail; 1412 } 1413 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1414 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1415 1416 Inst.addOperand(MCOperand::CreateImm(imm)); 1417 } else { 1418 Inst.addOperand(MCOperand::CreateReg(0)); 1419 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1420 Inst.addOperand(MCOperand::CreateImm(tmp)); 1421 } 1422 1423 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1424 return MCDisassembler::Fail; 1425 1426 return S; 1427 } 1428 1429 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1430 uint64_t Address, const void *Decoder) { 1431 DecodeStatus S = MCDisassembler::Success; 1432 1433 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1434 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1435 unsigned type = fieldFromInstruction32(Val, 5, 2); 1436 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1437 unsigned U = fieldFromInstruction32(Val, 12, 1); 1438 1439 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1440 switch (type) { 1441 case 0: 1442 ShOp = ARM_AM::lsl; 1443 break; 1444 case 1: 1445 ShOp = ARM_AM::lsr; 1446 break; 1447 case 2: 1448 ShOp = ARM_AM::asr; 1449 break; 1450 case 3: 1451 ShOp = ARM_AM::ror; 1452 break; 1453 } 1454 1455 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1456 return MCDisassembler::Fail; 1457 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1458 return MCDisassembler::Fail; 1459 unsigned shift; 1460 if (U) 1461 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1462 else 1463 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1464 Inst.addOperand(MCOperand::CreateImm(shift)); 1465 1466 return S; 1467 } 1468 1469 static DecodeStatus 1470 DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1471 uint64_t Address, const void *Decoder) { 1472 DecodeStatus S = MCDisassembler::Success; 1473 1474 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1475 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1476 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1477 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1478 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1479 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1480 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1481 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1482 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1483 1484 bool writeback = (W == 1) | (P == 0); 1485 1486 // For {LD,ST}RD, Rt must be even, else undefined. 1487 switch (Inst.getOpcode()) { 1488 case ARM::STRD: 1489 case ARM::STRD_PRE: 1490 case ARM::STRD_POST: 1491 case ARM::LDRD: 1492 case ARM::LDRD_PRE: 1493 case ARM::LDRD_POST: 1494 if (Rt & 0x1) return MCDisassembler::Fail; 1495 break; 1496 default: 1497 break; 1498 } 1499 1500 if (writeback) { // Writeback 1501 if (P) 1502 U |= ARMII::IndexModePre << 9; 1503 else 1504 U |= ARMII::IndexModePost << 9; 1505 1506 // On stores, the writeback operand precedes Rt. 1507 switch (Inst.getOpcode()) { 1508 case ARM::STRD: 1509 case ARM::STRD_PRE: 1510 case ARM::STRD_POST: 1511 case ARM::STRH: 1512 case ARM::STRH_PRE: 1513 case ARM::STRH_POST: 1514 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1515 return MCDisassembler::Fail; 1516 break; 1517 default: 1518 break; 1519 } 1520 } 1521 1522 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1523 return MCDisassembler::Fail; 1524 switch (Inst.getOpcode()) { 1525 case ARM::STRD: 1526 case ARM::STRD_PRE: 1527 case ARM::STRD_POST: 1528 case ARM::LDRD: 1529 case ARM::LDRD_PRE: 1530 case ARM::LDRD_POST: 1531 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1532 return MCDisassembler::Fail; 1533 break; 1534 default: 1535 break; 1536 } 1537 1538 if (writeback) { 1539 // On loads, the writeback operand comes after Rt. 1540 switch (Inst.getOpcode()) { 1541 case ARM::LDRD: 1542 case ARM::LDRD_PRE: 1543 case ARM::LDRD_POST: 1544 case ARM::LDRH: 1545 case ARM::LDRH_PRE: 1546 case ARM::LDRH_POST: 1547 case ARM::LDRSH: 1548 case ARM::LDRSH_PRE: 1549 case ARM::LDRSH_POST: 1550 case ARM::LDRSB: 1551 case ARM::LDRSB_PRE: 1552 case ARM::LDRSB_POST: 1553 case ARM::LDRHTr: 1554 case ARM::LDRSBTr: 1555 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1556 return MCDisassembler::Fail; 1557 break; 1558 default: 1559 break; 1560 } 1561 } 1562 1563 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1564 return MCDisassembler::Fail; 1565 1566 if (type) { 1567 Inst.addOperand(MCOperand::CreateReg(0)); 1568 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1569 } else { 1570 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1571 return MCDisassembler::Fail; 1572 Inst.addOperand(MCOperand::CreateImm(U)); 1573 } 1574 1575 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1576 return MCDisassembler::Fail; 1577 1578 return S; 1579 } 1580 1581 static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1582 uint64_t Address, const void *Decoder) { 1583 DecodeStatus S = MCDisassembler::Success; 1584 1585 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1586 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1587 1588 switch (mode) { 1589 case 0: 1590 mode = ARM_AM::da; 1591 break; 1592 case 1: 1593 mode = ARM_AM::ia; 1594 break; 1595 case 2: 1596 mode = ARM_AM::db; 1597 break; 1598 case 3: 1599 mode = ARM_AM::ib; 1600 break; 1601 } 1602 1603 Inst.addOperand(MCOperand::CreateImm(mode)); 1604 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1605 return MCDisassembler::Fail; 1606 1607 return S; 1608 } 1609 1610 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1611 unsigned Insn, 1612 uint64_t Address, const void *Decoder) { 1613 DecodeStatus S = MCDisassembler::Success; 1614 1615 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1616 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1617 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1618 1619 if (pred == 0xF) { 1620 switch (Inst.getOpcode()) { 1621 case ARM::LDMDA: 1622 Inst.setOpcode(ARM::RFEDA); 1623 break; 1624 case ARM::LDMDA_UPD: 1625 Inst.setOpcode(ARM::RFEDA_UPD); 1626 break; 1627 case ARM::LDMDB: 1628 Inst.setOpcode(ARM::RFEDB); 1629 break; 1630 case ARM::LDMDB_UPD: 1631 Inst.setOpcode(ARM::RFEDB_UPD); 1632 break; 1633 case ARM::LDMIA: 1634 Inst.setOpcode(ARM::RFEIA); 1635 break; 1636 case ARM::LDMIA_UPD: 1637 Inst.setOpcode(ARM::RFEIA_UPD); 1638 break; 1639 case ARM::LDMIB: 1640 Inst.setOpcode(ARM::RFEIB); 1641 break; 1642 case ARM::LDMIB_UPD: 1643 Inst.setOpcode(ARM::RFEIB_UPD); 1644 break; 1645 case ARM::STMDA: 1646 Inst.setOpcode(ARM::SRSDA); 1647 break; 1648 case ARM::STMDA_UPD: 1649 Inst.setOpcode(ARM::SRSDA_UPD); 1650 break; 1651 case ARM::STMDB: 1652 Inst.setOpcode(ARM::SRSDB); 1653 break; 1654 case ARM::STMDB_UPD: 1655 Inst.setOpcode(ARM::SRSDB_UPD); 1656 break; 1657 case ARM::STMIA: 1658 Inst.setOpcode(ARM::SRSIA); 1659 break; 1660 case ARM::STMIA_UPD: 1661 Inst.setOpcode(ARM::SRSIA_UPD); 1662 break; 1663 case ARM::STMIB: 1664 Inst.setOpcode(ARM::SRSIB); 1665 break; 1666 case ARM::STMIB_UPD: 1667 Inst.setOpcode(ARM::SRSIB_UPD); 1668 break; 1669 default: 1670 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1671 } 1672 1673 // For stores (which become SRS's, the only operand is the mode. 1674 if (fieldFromInstruction32(Insn, 20, 1) == 0) { 1675 Inst.addOperand( 1676 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4))); 1677 return S; 1678 } 1679 1680 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1681 } 1682 1683 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1684 return MCDisassembler::Fail; 1685 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1686 return MCDisassembler::Fail; // Tied 1687 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1688 return MCDisassembler::Fail; 1689 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1690 return MCDisassembler::Fail; 1691 1692 return S; 1693 } 1694 1695 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1696 uint64_t Address, const void *Decoder) { 1697 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1698 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1699 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1700 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1701 1702 DecodeStatus S = MCDisassembler::Success; 1703 1704 // imod == '01' --> UNPREDICTABLE 1705 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1706 // return failure here. The '01' imod value is unprintable, so there's 1707 // nothing useful we could do even if we returned UNPREDICTABLE. 1708 1709 if (imod == 1) return MCDisassembler::Fail; 1710 1711 if (imod && M) { 1712 Inst.setOpcode(ARM::CPS3p); 1713 Inst.addOperand(MCOperand::CreateImm(imod)); 1714 Inst.addOperand(MCOperand::CreateImm(iflags)); 1715 Inst.addOperand(MCOperand::CreateImm(mode)); 1716 } else if (imod && !M) { 1717 Inst.setOpcode(ARM::CPS2p); 1718 Inst.addOperand(MCOperand::CreateImm(imod)); 1719 Inst.addOperand(MCOperand::CreateImm(iflags)); 1720 if (mode) S = MCDisassembler::SoftFail; 1721 } else if (!imod && M) { 1722 Inst.setOpcode(ARM::CPS1p); 1723 Inst.addOperand(MCOperand::CreateImm(mode)); 1724 if (iflags) S = MCDisassembler::SoftFail; 1725 } else { 1726 // imod == '00' && M == '0' --> UNPREDICTABLE 1727 Inst.setOpcode(ARM::CPS1p); 1728 Inst.addOperand(MCOperand::CreateImm(mode)); 1729 S = MCDisassembler::SoftFail; 1730 } 1731 1732 return S; 1733 } 1734 1735 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1736 uint64_t Address, const void *Decoder) { 1737 unsigned imod = fieldFromInstruction32(Insn, 9, 2); 1738 unsigned M = fieldFromInstruction32(Insn, 8, 1); 1739 unsigned iflags = fieldFromInstruction32(Insn, 5, 3); 1740 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1741 1742 DecodeStatus S = MCDisassembler::Success; 1743 1744 // imod == '01' --> UNPREDICTABLE 1745 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1746 // return failure here. The '01' imod value is unprintable, so there's 1747 // nothing useful we could do even if we returned UNPREDICTABLE. 1748 1749 if (imod == 1) return MCDisassembler::Fail; 1750 1751 if (imod && M) { 1752 Inst.setOpcode(ARM::t2CPS3p); 1753 Inst.addOperand(MCOperand::CreateImm(imod)); 1754 Inst.addOperand(MCOperand::CreateImm(iflags)); 1755 Inst.addOperand(MCOperand::CreateImm(mode)); 1756 } else if (imod && !M) { 1757 Inst.setOpcode(ARM::t2CPS2p); 1758 Inst.addOperand(MCOperand::CreateImm(imod)); 1759 Inst.addOperand(MCOperand::CreateImm(iflags)); 1760 if (mode) S = MCDisassembler::SoftFail; 1761 } else if (!imod && M) { 1762 Inst.setOpcode(ARM::t2CPS1p); 1763 Inst.addOperand(MCOperand::CreateImm(mode)); 1764 if (iflags) S = MCDisassembler::SoftFail; 1765 } else { 1766 // imod == '00' && M == '0' --> UNPREDICTABLE 1767 Inst.setOpcode(ARM::t2CPS1p); 1768 Inst.addOperand(MCOperand::CreateImm(mode)); 1769 S = MCDisassembler::SoftFail; 1770 } 1771 1772 return S; 1773 } 1774 1775 static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 1776 uint64_t Address, const void *Decoder) { 1777 DecodeStatus S = MCDisassembler::Success; 1778 1779 unsigned Rd = fieldFromInstruction32(Insn, 8, 4); 1780 unsigned imm = 0; 1781 1782 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0); 1783 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8); 1784 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12); 1785 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11); 1786 1787 if (Inst.getOpcode() == ARM::t2MOVTi16) 1788 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1789 return MCDisassembler::Fail; 1790 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1791 return MCDisassembler::Fail; 1792 1793 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1794 Inst.addOperand(MCOperand::CreateImm(imm)); 1795 1796 return S; 1797 } 1798 1799 static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 1800 uint64_t Address, const void *Decoder) { 1801 DecodeStatus S = MCDisassembler::Success; 1802 1803 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1804 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1805 unsigned imm = 0; 1806 1807 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0); 1808 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12); 1809 1810 if (Inst.getOpcode() == ARM::MOVTi16) 1811 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1812 return MCDisassembler::Fail; 1813 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1814 return MCDisassembler::Fail; 1815 1816 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1817 Inst.addOperand(MCOperand::CreateImm(imm)); 1818 1819 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1820 return MCDisassembler::Fail; 1821 1822 return S; 1823 } 1824 1825 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1826 uint64_t Address, const void *Decoder) { 1827 DecodeStatus S = MCDisassembler::Success; 1828 1829 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1830 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1831 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1832 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1833 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1834 1835 if (pred == 0xF) 1836 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1837 1838 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1839 return MCDisassembler::Fail; 1840 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1841 return MCDisassembler::Fail; 1842 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1843 return MCDisassembler::Fail; 1844 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 1845 return MCDisassembler::Fail; 1846 1847 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1848 return MCDisassembler::Fail; 1849 1850 return S; 1851 } 1852 1853 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1854 uint64_t Address, const void *Decoder) { 1855 DecodeStatus S = MCDisassembler::Success; 1856 1857 unsigned add = fieldFromInstruction32(Val, 12, 1); 1858 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1859 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1860 1861 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1862 return MCDisassembler::Fail; 1863 1864 if (!add) imm *= -1; 1865 if (imm == 0 && !add) imm = INT32_MIN; 1866 Inst.addOperand(MCOperand::CreateImm(imm)); 1867 if (Rn == 15) 1868 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 1869 1870 return S; 1871 } 1872 1873 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1874 uint64_t Address, const void *Decoder) { 1875 DecodeStatus S = MCDisassembler::Success; 1876 1877 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1878 unsigned U = fieldFromInstruction32(Val, 8, 1); 1879 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1880 1881 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1882 return MCDisassembler::Fail; 1883 1884 if (U) 1885 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1886 else 1887 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1888 1889 return S; 1890 } 1891 1892 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1893 uint64_t Address, const void *Decoder) { 1894 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1895 } 1896 1897 static DecodeStatus 1898 DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1899 uint64_t Address, const void *Decoder) { 1900 DecodeStatus S = MCDisassembler::Success; 1901 1902 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1903 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1904 1905 if (pred == 0xF) { 1906 Inst.setOpcode(ARM::BLXi); 1907 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1908 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1909 return S; 1910 } 1911 1912 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, true, 1913 4, Inst, Decoder)) 1914 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1915 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1916 return MCDisassembler::Fail; 1917 1918 return S; 1919 } 1920 1921 1922 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1923 uint64_t Address, const void *Decoder) { 1924 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1925 return MCDisassembler::Success; 1926 } 1927 1928 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1929 uint64_t Address, const void *Decoder) { 1930 DecodeStatus S = MCDisassembler::Success; 1931 1932 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1933 unsigned align = fieldFromInstruction32(Val, 4, 2); 1934 1935 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1936 return MCDisassembler::Fail; 1937 if (!align) 1938 Inst.addOperand(MCOperand::CreateImm(0)); 1939 else 1940 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1941 1942 return S; 1943 } 1944 1945 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1946 uint64_t Address, const void *Decoder) { 1947 DecodeStatus S = MCDisassembler::Success; 1948 1949 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1950 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1951 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1952 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1953 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1954 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1955 1956 // First output register 1957 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 1958 return MCDisassembler::Fail; 1959 1960 // Second output register 1961 switch (Inst.getOpcode()) { 1962 case ARM::VLD3d8: 1963 case ARM::VLD3d16: 1964 case ARM::VLD3d32: 1965 case ARM::VLD3d8_UPD: 1966 case ARM::VLD3d16_UPD: 1967 case ARM::VLD3d32_UPD: 1968 case ARM::VLD4d8: 1969 case ARM::VLD4d16: 1970 case ARM::VLD4d32: 1971 case ARM::VLD4d8_UPD: 1972 case ARM::VLD4d16_UPD: 1973 case ARM::VLD4d32_UPD: 1974 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 1975 return MCDisassembler::Fail; 1976 break; 1977 case ARM::VLD3q8: 1978 case ARM::VLD3q16: 1979 case ARM::VLD3q32: 1980 case ARM::VLD3q8_UPD: 1981 case ARM::VLD3q16_UPD: 1982 case ARM::VLD3q32_UPD: 1983 case ARM::VLD4q8: 1984 case ARM::VLD4q16: 1985 case ARM::VLD4q32: 1986 case ARM::VLD4q8_UPD: 1987 case ARM::VLD4q16_UPD: 1988 case ARM::VLD4q32_UPD: 1989 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 1990 return MCDisassembler::Fail; 1991 default: 1992 break; 1993 } 1994 1995 // Third output register 1996 switch(Inst.getOpcode()) { 1997 case ARM::VLD3d8: 1998 case ARM::VLD3d16: 1999 case ARM::VLD3d32: 2000 case ARM::VLD3d8_UPD: 2001 case ARM::VLD3d16_UPD: 2002 case ARM::VLD3d32_UPD: 2003 case ARM::VLD4d8: 2004 case ARM::VLD4d16: 2005 case ARM::VLD4d32: 2006 case ARM::VLD4d8_UPD: 2007 case ARM::VLD4d16_UPD: 2008 case ARM::VLD4d32_UPD: 2009 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2010 return MCDisassembler::Fail; 2011 break; 2012 case ARM::VLD3q8: 2013 case ARM::VLD3q16: 2014 case ARM::VLD3q32: 2015 case ARM::VLD3q8_UPD: 2016 case ARM::VLD3q16_UPD: 2017 case ARM::VLD3q32_UPD: 2018 case ARM::VLD4q8: 2019 case ARM::VLD4q16: 2020 case ARM::VLD4q32: 2021 case ARM::VLD4q8_UPD: 2022 case ARM::VLD4q16_UPD: 2023 case ARM::VLD4q32_UPD: 2024 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2025 return MCDisassembler::Fail; 2026 break; 2027 default: 2028 break; 2029 } 2030 2031 // Fourth output register 2032 switch (Inst.getOpcode()) { 2033 case ARM::VLD4d8: 2034 case ARM::VLD4d16: 2035 case ARM::VLD4d32: 2036 case ARM::VLD4d8_UPD: 2037 case ARM::VLD4d16_UPD: 2038 case ARM::VLD4d32_UPD: 2039 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2040 return MCDisassembler::Fail; 2041 break; 2042 case ARM::VLD4q8: 2043 case ARM::VLD4q16: 2044 case ARM::VLD4q32: 2045 case ARM::VLD4q8_UPD: 2046 case ARM::VLD4q16_UPD: 2047 case ARM::VLD4q32_UPD: 2048 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2049 return MCDisassembler::Fail; 2050 break; 2051 default: 2052 break; 2053 } 2054 2055 // Writeback operand 2056 switch (Inst.getOpcode()) { 2057 case ARM::VLD1d8wb_fixed: 2058 case ARM::VLD1d16wb_fixed: 2059 case ARM::VLD1d32wb_fixed: 2060 case ARM::VLD1d64wb_fixed: 2061 case ARM::VLD1d8wb_register: 2062 case ARM::VLD1d16wb_register: 2063 case ARM::VLD1d32wb_register: 2064 case ARM::VLD1d64wb_register: 2065 case ARM::VLD1q8wb_fixed: 2066 case ARM::VLD1q16wb_fixed: 2067 case ARM::VLD1q32wb_fixed: 2068 case ARM::VLD1q64wb_fixed: 2069 case ARM::VLD1q8wb_register: 2070 case ARM::VLD1q16wb_register: 2071 case ARM::VLD1q32wb_register: 2072 case ARM::VLD1q64wb_register: 2073 case ARM::VLD1d8Twb_fixed: 2074 case ARM::VLD1d8Twb_register: 2075 case ARM::VLD1d16Twb_fixed: 2076 case ARM::VLD1d16Twb_register: 2077 case ARM::VLD1d32Twb_fixed: 2078 case ARM::VLD1d32Twb_register: 2079 case ARM::VLD1d64Twb_fixed: 2080 case ARM::VLD1d64Twb_register: 2081 case ARM::VLD1d8Qwb_fixed: 2082 case ARM::VLD1d8Qwb_register: 2083 case ARM::VLD1d16Qwb_fixed: 2084 case ARM::VLD1d16Qwb_register: 2085 case ARM::VLD1d32Qwb_fixed: 2086 case ARM::VLD1d32Qwb_register: 2087 case ARM::VLD1d64Qwb_fixed: 2088 case ARM::VLD1d64Qwb_register: 2089 case ARM::VLD2d8_UPD: 2090 case ARM::VLD2d16_UPD: 2091 case ARM::VLD2d32_UPD: 2092 case ARM::VLD2q8_UPD: 2093 case ARM::VLD2q16_UPD: 2094 case ARM::VLD2q32_UPD: 2095 case ARM::VLD2b8_UPD: 2096 case ARM::VLD2b16_UPD: 2097 case ARM::VLD2b32_UPD: 2098 case ARM::VLD3d8_UPD: 2099 case ARM::VLD3d16_UPD: 2100 case ARM::VLD3d32_UPD: 2101 case ARM::VLD3q8_UPD: 2102 case ARM::VLD3q16_UPD: 2103 case ARM::VLD3q32_UPD: 2104 case ARM::VLD4d8_UPD: 2105 case ARM::VLD4d16_UPD: 2106 case ARM::VLD4d32_UPD: 2107 case ARM::VLD4q8_UPD: 2108 case ARM::VLD4q16_UPD: 2109 case ARM::VLD4q32_UPD: 2110 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2111 return MCDisassembler::Fail; 2112 break; 2113 default: 2114 break; 2115 } 2116 2117 // AddrMode6 Base (register+alignment) 2118 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2119 return MCDisassembler::Fail; 2120 2121 // AddrMode6 Offset (register) 2122 switch (Inst.getOpcode()) { 2123 default: 2124 // The below have been updated to have explicit am6offset split 2125 // between fixed and register offset. For those instructions not 2126 // yet updated, we need to add an additional reg0 operand for the 2127 // fixed variant. 2128 // 2129 // The fixed offset encodes as Rm == 0xd, so we check for that. 2130 if (Rm == 0xd) { 2131 Inst.addOperand(MCOperand::CreateReg(0)); 2132 break; 2133 } 2134 // Fall through to handle the register offset variant. 2135 case ARM::VLD1d8wb_fixed: 2136 case ARM::VLD1d16wb_fixed: 2137 case ARM::VLD1d32wb_fixed: 2138 case ARM::VLD1d64wb_fixed: 2139 case ARM::VLD1d8Twb_fixed: 2140 case ARM::VLD1d16Twb_fixed: 2141 case ARM::VLD1d32Twb_fixed: 2142 case ARM::VLD1d64Twb_fixed: 2143 case ARM::VLD1d8wb_register: 2144 case ARM::VLD1d16wb_register: 2145 case ARM::VLD1d32wb_register: 2146 case ARM::VLD1d64wb_register: 2147 case ARM::VLD1q8wb_fixed: 2148 case ARM::VLD1q16wb_fixed: 2149 case ARM::VLD1q32wb_fixed: 2150 case ARM::VLD1q64wb_fixed: 2151 case ARM::VLD1q8wb_register: 2152 case ARM::VLD1q16wb_register: 2153 case ARM::VLD1q32wb_register: 2154 case ARM::VLD1q64wb_register: 2155 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2156 // variant encodes Rm == 0xf. Anything else is a register offset post- 2157 // increment and we need to add the register operand to the instruction. 2158 if (Rm != 0xD && Rm != 0xF && 2159 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2160 return MCDisassembler::Fail; 2161 break; 2162 } 2163 2164 return S; 2165 } 2166 2167 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 2168 uint64_t Address, const void *Decoder) { 2169 DecodeStatus S = MCDisassembler::Success; 2170 2171 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2172 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2173 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 2174 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2175 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 2176 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2177 2178 // Writeback Operand 2179 switch (Inst.getOpcode()) { 2180 case ARM::VST1d8_UPD: 2181 case ARM::VST1d16_UPD: 2182 case ARM::VST1d32_UPD: 2183 case ARM::VST1d64_UPD: 2184 case ARM::VST1q8_UPD: 2185 case ARM::VST1q16_UPD: 2186 case ARM::VST1q32_UPD: 2187 case ARM::VST1q64_UPD: 2188 case ARM::VST1d8T_UPD: 2189 case ARM::VST1d16T_UPD: 2190 case ARM::VST1d32T_UPD: 2191 case ARM::VST1d64T_UPD: 2192 case ARM::VST1d8Q_UPD: 2193 case ARM::VST1d16Q_UPD: 2194 case ARM::VST1d32Q_UPD: 2195 case ARM::VST1d64Q_UPD: 2196 case ARM::VST2d8_UPD: 2197 case ARM::VST2d16_UPD: 2198 case ARM::VST2d32_UPD: 2199 case ARM::VST2q8_UPD: 2200 case ARM::VST2q16_UPD: 2201 case ARM::VST2q32_UPD: 2202 case ARM::VST2b8_UPD: 2203 case ARM::VST2b16_UPD: 2204 case ARM::VST2b32_UPD: 2205 case ARM::VST3d8_UPD: 2206 case ARM::VST3d16_UPD: 2207 case ARM::VST3d32_UPD: 2208 case ARM::VST3q8_UPD: 2209 case ARM::VST3q16_UPD: 2210 case ARM::VST3q32_UPD: 2211 case ARM::VST4d8_UPD: 2212 case ARM::VST4d16_UPD: 2213 case ARM::VST4d32_UPD: 2214 case ARM::VST4q8_UPD: 2215 case ARM::VST4q16_UPD: 2216 case ARM::VST4q32_UPD: 2217 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2218 return MCDisassembler::Fail; 2219 break; 2220 default: 2221 break; 2222 } 2223 2224 // AddrMode6 Base (register+alignment) 2225 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2226 return MCDisassembler::Fail; 2227 2228 // AddrMode6 Offset (register) 2229 if (Rm == 0xD) 2230 Inst.addOperand(MCOperand::CreateReg(0)); 2231 else if (Rm != 0xF) { 2232 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2233 return MCDisassembler::Fail; 2234 } 2235 2236 // First input register 2237 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2238 return MCDisassembler::Fail; 2239 2240 // Second input register 2241 switch (Inst.getOpcode()) { 2242 case ARM::VST1q8: 2243 case ARM::VST1q16: 2244 case ARM::VST1q32: 2245 case ARM::VST1q64: 2246 case ARM::VST1q8_UPD: 2247 case ARM::VST1q16_UPD: 2248 case ARM::VST1q32_UPD: 2249 case ARM::VST1q64_UPD: 2250 case ARM::VST1d8T: 2251 case ARM::VST1d16T: 2252 case ARM::VST1d32T: 2253 case ARM::VST1d64T: 2254 case ARM::VST1d8T_UPD: 2255 case ARM::VST1d16T_UPD: 2256 case ARM::VST1d32T_UPD: 2257 case ARM::VST1d64T_UPD: 2258 case ARM::VST1d8Q: 2259 case ARM::VST1d16Q: 2260 case ARM::VST1d32Q: 2261 case ARM::VST1d64Q: 2262 case ARM::VST1d8Q_UPD: 2263 case ARM::VST1d16Q_UPD: 2264 case ARM::VST1d32Q_UPD: 2265 case ARM::VST1d64Q_UPD: 2266 case ARM::VST2d8: 2267 case ARM::VST2d16: 2268 case ARM::VST2d32: 2269 case ARM::VST2d8_UPD: 2270 case ARM::VST2d16_UPD: 2271 case ARM::VST2d32_UPD: 2272 case ARM::VST2q8: 2273 case ARM::VST2q16: 2274 case ARM::VST2q32: 2275 case ARM::VST2q8_UPD: 2276 case ARM::VST2q16_UPD: 2277 case ARM::VST2q32_UPD: 2278 case ARM::VST3d8: 2279 case ARM::VST3d16: 2280 case ARM::VST3d32: 2281 case ARM::VST3d8_UPD: 2282 case ARM::VST3d16_UPD: 2283 case ARM::VST3d32_UPD: 2284 case ARM::VST4d8: 2285 case ARM::VST4d16: 2286 case ARM::VST4d32: 2287 case ARM::VST4d8_UPD: 2288 case ARM::VST4d16_UPD: 2289 case ARM::VST4d32_UPD: 2290 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2291 return MCDisassembler::Fail; 2292 break; 2293 case ARM::VST2b8: 2294 case ARM::VST2b16: 2295 case ARM::VST2b32: 2296 case ARM::VST2b8_UPD: 2297 case ARM::VST2b16_UPD: 2298 case ARM::VST2b32_UPD: 2299 case ARM::VST3q8: 2300 case ARM::VST3q16: 2301 case ARM::VST3q32: 2302 case ARM::VST3q8_UPD: 2303 case ARM::VST3q16_UPD: 2304 case ARM::VST3q32_UPD: 2305 case ARM::VST4q8: 2306 case ARM::VST4q16: 2307 case ARM::VST4q32: 2308 case ARM::VST4q8_UPD: 2309 case ARM::VST4q16_UPD: 2310 case ARM::VST4q32_UPD: 2311 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2312 return MCDisassembler::Fail; 2313 break; 2314 default: 2315 break; 2316 } 2317 2318 // Third input register 2319 switch (Inst.getOpcode()) { 2320 case ARM::VST1d8T: 2321 case ARM::VST1d16T: 2322 case ARM::VST1d32T: 2323 case ARM::VST1d64T: 2324 case ARM::VST1d8T_UPD: 2325 case ARM::VST1d16T_UPD: 2326 case ARM::VST1d32T_UPD: 2327 case ARM::VST1d64T_UPD: 2328 case ARM::VST1d8Q: 2329 case ARM::VST1d16Q: 2330 case ARM::VST1d32Q: 2331 case ARM::VST1d64Q: 2332 case ARM::VST1d8Q_UPD: 2333 case ARM::VST1d16Q_UPD: 2334 case ARM::VST1d32Q_UPD: 2335 case ARM::VST1d64Q_UPD: 2336 case ARM::VST2q8: 2337 case ARM::VST2q16: 2338 case ARM::VST2q32: 2339 case ARM::VST2q8_UPD: 2340 case ARM::VST2q16_UPD: 2341 case ARM::VST2q32_UPD: 2342 case ARM::VST3d8: 2343 case ARM::VST3d16: 2344 case ARM::VST3d32: 2345 case ARM::VST3d8_UPD: 2346 case ARM::VST3d16_UPD: 2347 case ARM::VST3d32_UPD: 2348 case ARM::VST4d8: 2349 case ARM::VST4d16: 2350 case ARM::VST4d32: 2351 case ARM::VST4d8_UPD: 2352 case ARM::VST4d16_UPD: 2353 case ARM::VST4d32_UPD: 2354 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2355 return MCDisassembler::Fail; 2356 break; 2357 case ARM::VST3q8: 2358 case ARM::VST3q16: 2359 case ARM::VST3q32: 2360 case ARM::VST3q8_UPD: 2361 case ARM::VST3q16_UPD: 2362 case ARM::VST3q32_UPD: 2363 case ARM::VST4q8: 2364 case ARM::VST4q16: 2365 case ARM::VST4q32: 2366 case ARM::VST4q8_UPD: 2367 case ARM::VST4q16_UPD: 2368 case ARM::VST4q32_UPD: 2369 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2370 return MCDisassembler::Fail; 2371 break; 2372 default: 2373 break; 2374 } 2375 2376 // Fourth input register 2377 switch (Inst.getOpcode()) { 2378 case ARM::VST1d8Q: 2379 case ARM::VST1d16Q: 2380 case ARM::VST1d32Q: 2381 case ARM::VST1d64Q: 2382 case ARM::VST1d8Q_UPD: 2383 case ARM::VST1d16Q_UPD: 2384 case ARM::VST1d32Q_UPD: 2385 case ARM::VST1d64Q_UPD: 2386 case ARM::VST2q8: 2387 case ARM::VST2q16: 2388 case ARM::VST2q32: 2389 case ARM::VST2q8_UPD: 2390 case ARM::VST2q16_UPD: 2391 case ARM::VST2q32_UPD: 2392 case ARM::VST4d8: 2393 case ARM::VST4d16: 2394 case ARM::VST4d32: 2395 case ARM::VST4d8_UPD: 2396 case ARM::VST4d16_UPD: 2397 case ARM::VST4d32_UPD: 2398 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2399 return MCDisassembler::Fail; 2400 break; 2401 case ARM::VST4q8: 2402 case ARM::VST4q16: 2403 case ARM::VST4q32: 2404 case ARM::VST4q8_UPD: 2405 case ARM::VST4q16_UPD: 2406 case ARM::VST4q32_UPD: 2407 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2408 return MCDisassembler::Fail; 2409 break; 2410 default: 2411 break; 2412 } 2413 2414 return S; 2415 } 2416 2417 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2418 uint64_t Address, const void *Decoder) { 2419 DecodeStatus S = MCDisassembler::Success; 2420 2421 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2422 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2423 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2424 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2425 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2426 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2427 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 2428 2429 align *= (1 << size); 2430 2431 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2432 return MCDisassembler::Fail; 2433 if (regs == 2) { 2434 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2435 return MCDisassembler::Fail; 2436 } 2437 if (Rm != 0xF) { 2438 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2439 return MCDisassembler::Fail; 2440 } 2441 2442 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2443 return MCDisassembler::Fail; 2444 Inst.addOperand(MCOperand::CreateImm(align)); 2445 2446 if (Rm == 0xD) 2447 Inst.addOperand(MCOperand::CreateReg(0)); 2448 else if (Rm != 0xF) { 2449 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2450 return MCDisassembler::Fail; 2451 } 2452 2453 return S; 2454 } 2455 2456 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2457 uint64_t Address, const void *Decoder) { 2458 DecodeStatus S = MCDisassembler::Success; 2459 2460 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2461 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2462 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2463 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2464 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2465 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 2466 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2467 align *= 2*size; 2468 2469 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2470 return MCDisassembler::Fail; 2471 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2472 return MCDisassembler::Fail; 2473 if (Rm != 0xF) { 2474 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2475 return MCDisassembler::Fail; 2476 } 2477 2478 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2479 return MCDisassembler::Fail; 2480 Inst.addOperand(MCOperand::CreateImm(align)); 2481 2482 if (Rm == 0xD) 2483 Inst.addOperand(MCOperand::CreateReg(0)); 2484 else if (Rm != 0xF) { 2485 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2486 return MCDisassembler::Fail; 2487 } 2488 2489 return S; 2490 } 2491 2492 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2493 uint64_t Address, const void *Decoder) { 2494 DecodeStatus S = MCDisassembler::Success; 2495 2496 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2497 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2498 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2499 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2500 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2501 2502 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2503 return MCDisassembler::Fail; 2504 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2505 return MCDisassembler::Fail; 2506 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2507 return MCDisassembler::Fail; 2508 if (Rm != 0xF) { 2509 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2510 return MCDisassembler::Fail; 2511 } 2512 2513 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2514 return MCDisassembler::Fail; 2515 Inst.addOperand(MCOperand::CreateImm(0)); 2516 2517 if (Rm == 0xD) 2518 Inst.addOperand(MCOperand::CreateReg(0)); 2519 else if (Rm != 0xF) { 2520 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2521 return MCDisassembler::Fail; 2522 } 2523 2524 return S; 2525 } 2526 2527 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2528 uint64_t Address, const void *Decoder) { 2529 DecodeStatus S = MCDisassembler::Success; 2530 2531 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2532 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2533 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2534 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2535 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2536 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2537 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2538 2539 if (size == 0x3) { 2540 size = 4; 2541 align = 16; 2542 } else { 2543 if (size == 2) { 2544 size = 1 << size; 2545 align *= 8; 2546 } else { 2547 size = 1 << size; 2548 align *= 4*size; 2549 } 2550 } 2551 2552 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2553 return MCDisassembler::Fail; 2554 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2555 return MCDisassembler::Fail; 2556 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2557 return MCDisassembler::Fail; 2558 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2559 return MCDisassembler::Fail; 2560 if (Rm != 0xF) { 2561 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2562 return MCDisassembler::Fail; 2563 } 2564 2565 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2566 return MCDisassembler::Fail; 2567 Inst.addOperand(MCOperand::CreateImm(align)); 2568 2569 if (Rm == 0xD) 2570 Inst.addOperand(MCOperand::CreateReg(0)); 2571 else if (Rm != 0xF) { 2572 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2573 return MCDisassembler::Fail; 2574 } 2575 2576 return S; 2577 } 2578 2579 static DecodeStatus 2580 DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 2581 uint64_t Address, const void *Decoder) { 2582 DecodeStatus S = MCDisassembler::Success; 2583 2584 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2585 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2586 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2587 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2588 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2589 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2590 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2591 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2592 2593 if (Q) { 2594 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2595 return MCDisassembler::Fail; 2596 } else { 2597 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2598 return MCDisassembler::Fail; 2599 } 2600 2601 Inst.addOperand(MCOperand::CreateImm(imm)); 2602 2603 switch (Inst.getOpcode()) { 2604 case ARM::VORRiv4i16: 2605 case ARM::VORRiv2i32: 2606 case ARM::VBICiv4i16: 2607 case ARM::VBICiv2i32: 2608 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2609 return MCDisassembler::Fail; 2610 break; 2611 case ARM::VORRiv8i16: 2612 case ARM::VORRiv4i32: 2613 case ARM::VBICiv8i16: 2614 case ARM::VBICiv4i32: 2615 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2616 return MCDisassembler::Fail; 2617 break; 2618 default: 2619 break; 2620 } 2621 2622 return S; 2623 } 2624 2625 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2626 uint64_t Address, const void *Decoder) { 2627 DecodeStatus S = MCDisassembler::Success; 2628 2629 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2630 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2631 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2632 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2633 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2634 2635 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2636 return MCDisassembler::Fail; 2637 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2638 return MCDisassembler::Fail; 2639 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2640 2641 return S; 2642 } 2643 2644 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2645 uint64_t Address, const void *Decoder) { 2646 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2647 return MCDisassembler::Success; 2648 } 2649 2650 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2651 uint64_t Address, const void *Decoder) { 2652 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2653 return MCDisassembler::Success; 2654 } 2655 2656 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2657 uint64_t Address, const void *Decoder) { 2658 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2659 return MCDisassembler::Success; 2660 } 2661 2662 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2663 uint64_t Address, const void *Decoder) { 2664 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2665 return MCDisassembler::Success; 2666 } 2667 2668 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2669 uint64_t Address, const void *Decoder) { 2670 DecodeStatus S = MCDisassembler::Success; 2671 2672 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2673 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2674 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2675 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2676 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2677 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2678 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2679 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2680 2681 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2682 return MCDisassembler::Fail; 2683 if (op) { 2684 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2685 return MCDisassembler::Fail; // Writeback 2686 } 2687 2688 for (unsigned i = 0; i < length; ++i) { 2689 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder))) 2690 return MCDisassembler::Fail; 2691 } 2692 2693 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2694 return MCDisassembler::Fail; 2695 2696 return S; 2697 } 2698 2699 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2700 uint64_t Address, const void *Decoder) { 2701 DecodeStatus S = MCDisassembler::Success; 2702 2703 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2704 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2705 2706 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 2707 return MCDisassembler::Fail; 2708 2709 switch(Inst.getOpcode()) { 2710 default: 2711 return MCDisassembler::Fail; 2712 case ARM::tADR: 2713 break; // tADR does not explicitly represent the PC as an operand. 2714 case ARM::tADDrSPi: 2715 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2716 break; 2717 } 2718 2719 Inst.addOperand(MCOperand::CreateImm(imm)); 2720 return S; 2721 } 2722 2723 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2724 uint64_t Address, const void *Decoder) { 2725 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2726 return MCDisassembler::Success; 2727 } 2728 2729 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2730 uint64_t Address, const void *Decoder) { 2731 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2732 return MCDisassembler::Success; 2733 } 2734 2735 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2736 uint64_t Address, const void *Decoder) { 2737 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2738 return MCDisassembler::Success; 2739 } 2740 2741 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2742 uint64_t Address, const void *Decoder) { 2743 DecodeStatus S = MCDisassembler::Success; 2744 2745 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2746 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2747 2748 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2749 return MCDisassembler::Fail; 2750 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 2751 return MCDisassembler::Fail; 2752 2753 return S; 2754 } 2755 2756 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2757 uint64_t Address, const void *Decoder) { 2758 DecodeStatus S = MCDisassembler::Success; 2759 2760 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2761 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2762 2763 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2764 return MCDisassembler::Fail; 2765 Inst.addOperand(MCOperand::CreateImm(imm)); 2766 2767 return S; 2768 } 2769 2770 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2771 uint64_t Address, const void *Decoder) { 2772 unsigned imm = Val << 2; 2773 2774 Inst.addOperand(MCOperand::CreateImm(imm)); 2775 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 2776 2777 return MCDisassembler::Success; 2778 } 2779 2780 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2781 uint64_t Address, const void *Decoder) { 2782 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2783 Inst.addOperand(MCOperand::CreateImm(Val)); 2784 2785 return MCDisassembler::Success; 2786 } 2787 2788 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2789 uint64_t Address, const void *Decoder) { 2790 DecodeStatus S = MCDisassembler::Success; 2791 2792 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2793 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2794 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2795 2796 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2797 return MCDisassembler::Fail; 2798 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 2799 return MCDisassembler::Fail; 2800 Inst.addOperand(MCOperand::CreateImm(imm)); 2801 2802 return S; 2803 } 2804 2805 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2806 uint64_t Address, const void *Decoder) { 2807 DecodeStatus S = MCDisassembler::Success; 2808 2809 switch (Inst.getOpcode()) { 2810 case ARM::t2PLDs: 2811 case ARM::t2PLDWs: 2812 case ARM::t2PLIs: 2813 break; 2814 default: { 2815 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2816 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 2817 return MCDisassembler::Fail; 2818 } 2819 } 2820 2821 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2822 if (Rn == 0xF) { 2823 switch (Inst.getOpcode()) { 2824 case ARM::t2LDRBs: 2825 Inst.setOpcode(ARM::t2LDRBpci); 2826 break; 2827 case ARM::t2LDRHs: 2828 Inst.setOpcode(ARM::t2LDRHpci); 2829 break; 2830 case ARM::t2LDRSHs: 2831 Inst.setOpcode(ARM::t2LDRSHpci); 2832 break; 2833 case ARM::t2LDRSBs: 2834 Inst.setOpcode(ARM::t2LDRSBpci); 2835 break; 2836 case ARM::t2PLDs: 2837 Inst.setOpcode(ARM::t2PLDi12); 2838 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2839 break; 2840 default: 2841 return MCDisassembler::Fail; 2842 } 2843 2844 int imm = fieldFromInstruction32(Insn, 0, 12); 2845 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2846 Inst.addOperand(MCOperand::CreateImm(imm)); 2847 2848 return S; 2849 } 2850 2851 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2852 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2853 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2854 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 2855 return MCDisassembler::Fail; 2856 2857 return S; 2858 } 2859 2860 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2861 uint64_t Address, const void *Decoder) { 2862 int imm = Val & 0xFF; 2863 if (!(Val & 0x100)) imm *= -1; 2864 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2865 2866 return MCDisassembler::Success; 2867 } 2868 2869 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2870 uint64_t Address, const void *Decoder) { 2871 DecodeStatus S = MCDisassembler::Success; 2872 2873 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2874 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2875 2876 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2877 return MCDisassembler::Fail; 2878 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 2879 return MCDisassembler::Fail; 2880 2881 return S; 2882 } 2883 2884 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, 2885 uint64_t Address, const void *Decoder) { 2886 DecodeStatus S = MCDisassembler::Success; 2887 2888 unsigned Rn = fieldFromInstruction32(Val, 8, 4); 2889 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2890 2891 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2892 return MCDisassembler::Fail; 2893 2894 Inst.addOperand(MCOperand::CreateImm(imm)); 2895 2896 return S; 2897 } 2898 2899 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2900 uint64_t Address, const void *Decoder) { 2901 int imm = Val & 0xFF; 2902 if (Val == 0) 2903 imm = INT32_MIN; 2904 else if (!(Val & 0x100)) 2905 imm *= -1; 2906 Inst.addOperand(MCOperand::CreateImm(imm)); 2907 2908 return MCDisassembler::Success; 2909 } 2910 2911 2912 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2913 uint64_t Address, const void *Decoder) { 2914 DecodeStatus S = MCDisassembler::Success; 2915 2916 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2917 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2918 2919 // Some instructions always use an additive offset. 2920 switch (Inst.getOpcode()) { 2921 case ARM::t2LDRT: 2922 case ARM::t2LDRBT: 2923 case ARM::t2LDRHT: 2924 case ARM::t2LDRSBT: 2925 case ARM::t2LDRSHT: 2926 case ARM::t2STRT: 2927 case ARM::t2STRBT: 2928 case ARM::t2STRHT: 2929 imm |= 0x100; 2930 break; 2931 default: 2932 break; 2933 } 2934 2935 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2936 return MCDisassembler::Fail; 2937 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 2938 return MCDisassembler::Fail; 2939 2940 return S; 2941 } 2942 2943 static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn, 2944 uint64_t Address, const void *Decoder) { 2945 DecodeStatus S = MCDisassembler::Success; 2946 2947 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2948 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2949 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 2950 addr |= fieldFromInstruction32(Insn, 9, 1) << 8; 2951 addr |= Rn << 9; 2952 unsigned load = fieldFromInstruction32(Insn, 20, 1); 2953 2954 if (!load) { 2955 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2956 return MCDisassembler::Fail; 2957 } 2958 2959 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 2960 return MCDisassembler::Fail; 2961 2962 if (load) { 2963 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2964 return MCDisassembler::Fail; 2965 } 2966 2967 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 2968 return MCDisassembler::Fail; 2969 2970 return S; 2971 } 2972 2973 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2974 uint64_t Address, const void *Decoder) { 2975 DecodeStatus S = MCDisassembler::Success; 2976 2977 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2978 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2979 2980 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2981 return MCDisassembler::Fail; 2982 Inst.addOperand(MCOperand::CreateImm(imm)); 2983 2984 return S; 2985 } 2986 2987 2988 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2989 uint64_t Address, const void *Decoder) { 2990 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2991 2992 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2993 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2994 Inst.addOperand(MCOperand::CreateImm(imm)); 2995 2996 return MCDisassembler::Success; 2997 } 2998 2999 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 3000 uint64_t Address, const void *Decoder) { 3001 DecodeStatus S = MCDisassembler::Success; 3002 3003 if (Inst.getOpcode() == ARM::tADDrSP) { 3004 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 3005 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 3006 3007 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3008 return MCDisassembler::Fail; 3009 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3010 return MCDisassembler::Fail; 3011 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3012 } else if (Inst.getOpcode() == ARM::tADDspr) { 3013 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 3014 3015 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3016 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3017 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3018 return MCDisassembler::Fail; 3019 } 3020 3021 return S; 3022 } 3023 3024 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 3025 uint64_t Address, const void *Decoder) { 3026 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 3027 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 3028 3029 Inst.addOperand(MCOperand::CreateImm(imod)); 3030 Inst.addOperand(MCOperand::CreateImm(flags)); 3031 3032 return MCDisassembler::Success; 3033 } 3034 3035 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 3036 uint64_t Address, const void *Decoder) { 3037 DecodeStatus S = MCDisassembler::Success; 3038 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3039 unsigned add = fieldFromInstruction32(Insn, 4, 1); 3040 3041 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3042 return MCDisassembler::Fail; 3043 Inst.addOperand(MCOperand::CreateImm(add)); 3044 3045 return S; 3046 } 3047 3048 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 3049 uint64_t Address, const void *Decoder) { 3050 if (!tryAddingSymbolicOperand(Address, 3051 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4, 3052 true, 4, Inst, Decoder)) 3053 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3054 return MCDisassembler::Success; 3055 } 3056 3057 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 3058 uint64_t Address, const void *Decoder) { 3059 if (Val == 0xA || Val == 0xB) 3060 return MCDisassembler::Fail; 3061 3062 Inst.addOperand(MCOperand::CreateImm(Val)); 3063 return MCDisassembler::Success; 3064 } 3065 3066 static DecodeStatus 3067 DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn, 3068 uint64_t Address, const void *Decoder) { 3069 DecodeStatus S = MCDisassembler::Success; 3070 3071 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3072 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3073 3074 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3075 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3076 return MCDisassembler::Fail; 3077 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3078 return MCDisassembler::Fail; 3079 return S; 3080 } 3081 3082 static DecodeStatus 3083 DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 3084 uint64_t Address, const void *Decoder) { 3085 DecodeStatus S = MCDisassembler::Success; 3086 3087 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 3088 if (pred == 0xE || pred == 0xF) { 3089 unsigned opc = fieldFromInstruction32(Insn, 4, 28); 3090 switch (opc) { 3091 default: 3092 return MCDisassembler::Fail; 3093 case 0xf3bf8f4: 3094 Inst.setOpcode(ARM::t2DSB); 3095 break; 3096 case 0xf3bf8f5: 3097 Inst.setOpcode(ARM::t2DMB); 3098 break; 3099 case 0xf3bf8f6: 3100 Inst.setOpcode(ARM::t2ISB); 3101 break; 3102 } 3103 3104 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 3105 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3106 } 3107 3108 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 3109 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 3110 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 3111 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 3112 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 3113 3114 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3115 return MCDisassembler::Fail; 3116 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3117 return MCDisassembler::Fail; 3118 3119 return S; 3120 } 3121 3122 // Decode a shifted immediate operand. These basically consist 3123 // of an 8-bit value, and a 4-bit directive that specifies either 3124 // a splat operation or a rotation. 3125 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 3126 uint64_t Address, const void *Decoder) { 3127 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 3128 if (ctrl == 0) { 3129 unsigned byte = fieldFromInstruction32(Val, 8, 2); 3130 unsigned imm = fieldFromInstruction32(Val, 0, 8); 3131 switch (byte) { 3132 case 0: 3133 Inst.addOperand(MCOperand::CreateImm(imm)); 3134 break; 3135 case 1: 3136 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3137 break; 3138 case 2: 3139 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3140 break; 3141 case 3: 3142 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3143 (imm << 8) | imm)); 3144 break; 3145 } 3146 } else { 3147 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 3148 unsigned rot = fieldFromInstruction32(Val, 7, 5); 3149 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3150 Inst.addOperand(MCOperand::CreateImm(imm)); 3151 } 3152 3153 return MCDisassembler::Success; 3154 } 3155 3156 static DecodeStatus 3157 DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 3158 uint64_t Address, const void *Decoder){ 3159 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 3160 return MCDisassembler::Success; 3161 } 3162 3163 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 3164 uint64_t Address, const void *Decoder){ 3165 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3166 return MCDisassembler::Success; 3167 } 3168 3169 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 3170 uint64_t Address, const void *Decoder) { 3171 switch (Val) { 3172 default: 3173 return MCDisassembler::Fail; 3174 case 0xF: // SY 3175 case 0xE: // ST 3176 case 0xB: // ISH 3177 case 0xA: // ISHST 3178 case 0x7: // NSH 3179 case 0x6: // NSHST 3180 case 0x3: // OSH 3181 case 0x2: // OSHST 3182 break; 3183 } 3184 3185 Inst.addOperand(MCOperand::CreateImm(Val)); 3186 return MCDisassembler::Success; 3187 } 3188 3189 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 3190 uint64_t Address, const void *Decoder) { 3191 if (!Val) return MCDisassembler::Fail; 3192 Inst.addOperand(MCOperand::CreateImm(Val)); 3193 return MCDisassembler::Success; 3194 } 3195 3196 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 3197 uint64_t Address, const void *Decoder) { 3198 DecodeStatus S = MCDisassembler::Success; 3199 3200 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3201 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3202 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3203 3204 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3205 3206 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3207 return MCDisassembler::Fail; 3208 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3209 return MCDisassembler::Fail; 3210 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3211 return MCDisassembler::Fail; 3212 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3213 return MCDisassembler::Fail; 3214 3215 return S; 3216 } 3217 3218 3219 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 3220 uint64_t Address, const void *Decoder){ 3221 DecodeStatus S = MCDisassembler::Success; 3222 3223 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3224 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 3225 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3226 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3227 3228 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 3229 return MCDisassembler::Fail; 3230 3231 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3232 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 3233 3234 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3235 return MCDisassembler::Fail; 3236 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3237 return MCDisassembler::Fail; 3238 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3239 return MCDisassembler::Fail; 3240 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3241 return MCDisassembler::Fail; 3242 3243 return S; 3244 } 3245 3246 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 3247 uint64_t Address, const void *Decoder) { 3248 DecodeStatus S = MCDisassembler::Success; 3249 3250 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3251 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3252 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3253 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3254 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3255 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3256 3257 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3258 3259 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3260 return MCDisassembler::Fail; 3261 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3262 return MCDisassembler::Fail; 3263 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3264 return MCDisassembler::Fail; 3265 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3266 return MCDisassembler::Fail; 3267 3268 return S; 3269 } 3270 3271 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 3272 uint64_t Address, const void *Decoder) { 3273 DecodeStatus S = MCDisassembler::Success; 3274 3275 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3276 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3277 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3278 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3279 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3280 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3281 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3282 3283 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3284 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3285 3286 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3287 return MCDisassembler::Fail; 3288 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3289 return MCDisassembler::Fail; 3290 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3291 return MCDisassembler::Fail; 3292 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3293 return MCDisassembler::Fail; 3294 3295 return S; 3296 } 3297 3298 3299 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 3300 uint64_t Address, const void *Decoder) { 3301 DecodeStatus S = MCDisassembler::Success; 3302 3303 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3304 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3305 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3306 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3307 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3308 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3309 3310 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3311 3312 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3313 return MCDisassembler::Fail; 3314 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3315 return MCDisassembler::Fail; 3316 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3317 return MCDisassembler::Fail; 3318 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3319 return MCDisassembler::Fail; 3320 3321 return S; 3322 } 3323 3324 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 3325 uint64_t Address, const void *Decoder) { 3326 DecodeStatus S = MCDisassembler::Success; 3327 3328 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3329 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3330 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3331 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3332 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3333 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3334 3335 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3336 3337 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3338 return MCDisassembler::Fail; 3339 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3340 return MCDisassembler::Fail; 3341 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3342 return MCDisassembler::Fail; 3343 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3344 return MCDisassembler::Fail; 3345 3346 return S; 3347 } 3348 3349 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 3350 uint64_t Address, const void *Decoder) { 3351 DecodeStatus S = MCDisassembler::Success; 3352 3353 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3354 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3355 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3356 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3357 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3358 3359 unsigned align = 0; 3360 unsigned index = 0; 3361 switch (size) { 3362 default: 3363 return MCDisassembler::Fail; 3364 case 0: 3365 if (fieldFromInstruction32(Insn, 4, 1)) 3366 return MCDisassembler::Fail; // UNDEFINED 3367 index = fieldFromInstruction32(Insn, 5, 3); 3368 break; 3369 case 1: 3370 if (fieldFromInstruction32(Insn, 5, 1)) 3371 return MCDisassembler::Fail; // UNDEFINED 3372 index = fieldFromInstruction32(Insn, 6, 2); 3373 if (fieldFromInstruction32(Insn, 4, 1)) 3374 align = 2; 3375 break; 3376 case 2: 3377 if (fieldFromInstruction32(Insn, 6, 1)) 3378 return MCDisassembler::Fail; // UNDEFINED 3379 index = fieldFromInstruction32(Insn, 7, 1); 3380 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3381 align = 4; 3382 } 3383 3384 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3385 return MCDisassembler::Fail; 3386 if (Rm != 0xF) { // Writeback 3387 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3388 return MCDisassembler::Fail; 3389 } 3390 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3391 return MCDisassembler::Fail; 3392 Inst.addOperand(MCOperand::CreateImm(align)); 3393 if (Rm != 0xF) { 3394 if (Rm != 0xD) { 3395 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3396 return MCDisassembler::Fail; 3397 } else 3398 Inst.addOperand(MCOperand::CreateReg(0)); 3399 } 3400 3401 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3402 return MCDisassembler::Fail; 3403 Inst.addOperand(MCOperand::CreateImm(index)); 3404 3405 return S; 3406 } 3407 3408 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 3409 uint64_t Address, const void *Decoder) { 3410 DecodeStatus S = MCDisassembler::Success; 3411 3412 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3413 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3414 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3415 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3416 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3417 3418 unsigned align = 0; 3419 unsigned index = 0; 3420 switch (size) { 3421 default: 3422 return MCDisassembler::Fail; 3423 case 0: 3424 if (fieldFromInstruction32(Insn, 4, 1)) 3425 return MCDisassembler::Fail; // UNDEFINED 3426 index = fieldFromInstruction32(Insn, 5, 3); 3427 break; 3428 case 1: 3429 if (fieldFromInstruction32(Insn, 5, 1)) 3430 return MCDisassembler::Fail; // UNDEFINED 3431 index = fieldFromInstruction32(Insn, 6, 2); 3432 if (fieldFromInstruction32(Insn, 4, 1)) 3433 align = 2; 3434 break; 3435 case 2: 3436 if (fieldFromInstruction32(Insn, 6, 1)) 3437 return MCDisassembler::Fail; // UNDEFINED 3438 index = fieldFromInstruction32(Insn, 7, 1); 3439 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3440 align = 4; 3441 } 3442 3443 if (Rm != 0xF) { // Writeback 3444 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3445 return MCDisassembler::Fail; 3446 } 3447 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3448 return MCDisassembler::Fail; 3449 Inst.addOperand(MCOperand::CreateImm(align)); 3450 if (Rm != 0xF) { 3451 if (Rm != 0xD) { 3452 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3453 return MCDisassembler::Fail; 3454 } else 3455 Inst.addOperand(MCOperand::CreateReg(0)); 3456 } 3457 3458 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3459 return MCDisassembler::Fail; 3460 Inst.addOperand(MCOperand::CreateImm(index)); 3461 3462 return S; 3463 } 3464 3465 3466 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 3467 uint64_t Address, const void *Decoder) { 3468 DecodeStatus S = MCDisassembler::Success; 3469 3470 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3471 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3472 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3473 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3474 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3475 3476 unsigned align = 0; 3477 unsigned index = 0; 3478 unsigned inc = 1; 3479 switch (size) { 3480 default: 3481 return MCDisassembler::Fail; 3482 case 0: 3483 index = fieldFromInstruction32(Insn, 5, 3); 3484 if (fieldFromInstruction32(Insn, 4, 1)) 3485 align = 2; 3486 break; 3487 case 1: 3488 index = fieldFromInstruction32(Insn, 6, 2); 3489 if (fieldFromInstruction32(Insn, 4, 1)) 3490 align = 4; 3491 if (fieldFromInstruction32(Insn, 5, 1)) 3492 inc = 2; 3493 break; 3494 case 2: 3495 if (fieldFromInstruction32(Insn, 5, 1)) 3496 return MCDisassembler::Fail; // UNDEFINED 3497 index = fieldFromInstruction32(Insn, 7, 1); 3498 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3499 align = 8; 3500 if (fieldFromInstruction32(Insn, 6, 1)) 3501 inc = 2; 3502 break; 3503 } 3504 3505 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3506 return MCDisassembler::Fail; 3507 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3508 return MCDisassembler::Fail; 3509 if (Rm != 0xF) { // Writeback 3510 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3511 return MCDisassembler::Fail; 3512 } 3513 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3514 return MCDisassembler::Fail; 3515 Inst.addOperand(MCOperand::CreateImm(align)); 3516 if (Rm != 0xF) { 3517 if (Rm != 0xD) { 3518 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3519 return MCDisassembler::Fail; 3520 } else 3521 Inst.addOperand(MCOperand::CreateReg(0)); 3522 } 3523 3524 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3525 return MCDisassembler::Fail; 3526 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3527 return MCDisassembler::Fail; 3528 Inst.addOperand(MCOperand::CreateImm(index)); 3529 3530 return S; 3531 } 3532 3533 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 3534 uint64_t Address, const void *Decoder) { 3535 DecodeStatus S = MCDisassembler::Success; 3536 3537 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3538 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3539 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3540 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3541 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3542 3543 unsigned align = 0; 3544 unsigned index = 0; 3545 unsigned inc = 1; 3546 switch (size) { 3547 default: 3548 return MCDisassembler::Fail; 3549 case 0: 3550 index = fieldFromInstruction32(Insn, 5, 3); 3551 if (fieldFromInstruction32(Insn, 4, 1)) 3552 align = 2; 3553 break; 3554 case 1: 3555 index = fieldFromInstruction32(Insn, 6, 2); 3556 if (fieldFromInstruction32(Insn, 4, 1)) 3557 align = 4; 3558 if (fieldFromInstruction32(Insn, 5, 1)) 3559 inc = 2; 3560 break; 3561 case 2: 3562 if (fieldFromInstruction32(Insn, 5, 1)) 3563 return MCDisassembler::Fail; // UNDEFINED 3564 index = fieldFromInstruction32(Insn, 7, 1); 3565 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3566 align = 8; 3567 if (fieldFromInstruction32(Insn, 6, 1)) 3568 inc = 2; 3569 break; 3570 } 3571 3572 if (Rm != 0xF) { // Writeback 3573 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3574 return MCDisassembler::Fail; 3575 } 3576 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3577 return MCDisassembler::Fail; 3578 Inst.addOperand(MCOperand::CreateImm(align)); 3579 if (Rm != 0xF) { 3580 if (Rm != 0xD) { 3581 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3582 return MCDisassembler::Fail; 3583 } else 3584 Inst.addOperand(MCOperand::CreateReg(0)); 3585 } 3586 3587 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3588 return MCDisassembler::Fail; 3589 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3590 return MCDisassembler::Fail; 3591 Inst.addOperand(MCOperand::CreateImm(index)); 3592 3593 return S; 3594 } 3595 3596 3597 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 3598 uint64_t Address, const void *Decoder) { 3599 DecodeStatus S = MCDisassembler::Success; 3600 3601 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3602 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3603 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3604 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3605 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3606 3607 unsigned align = 0; 3608 unsigned index = 0; 3609 unsigned inc = 1; 3610 switch (size) { 3611 default: 3612 return MCDisassembler::Fail; 3613 case 0: 3614 if (fieldFromInstruction32(Insn, 4, 1)) 3615 return MCDisassembler::Fail; // UNDEFINED 3616 index = fieldFromInstruction32(Insn, 5, 3); 3617 break; 3618 case 1: 3619 if (fieldFromInstruction32(Insn, 4, 1)) 3620 return MCDisassembler::Fail; // UNDEFINED 3621 index = fieldFromInstruction32(Insn, 6, 2); 3622 if (fieldFromInstruction32(Insn, 5, 1)) 3623 inc = 2; 3624 break; 3625 case 2: 3626 if (fieldFromInstruction32(Insn, 4, 2)) 3627 return MCDisassembler::Fail; // UNDEFINED 3628 index = fieldFromInstruction32(Insn, 7, 1); 3629 if (fieldFromInstruction32(Insn, 6, 1)) 3630 inc = 2; 3631 break; 3632 } 3633 3634 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3635 return MCDisassembler::Fail; 3636 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3637 return MCDisassembler::Fail; 3638 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3639 return MCDisassembler::Fail; 3640 3641 if (Rm != 0xF) { // Writeback 3642 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3643 return MCDisassembler::Fail; 3644 } 3645 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3646 return MCDisassembler::Fail; 3647 Inst.addOperand(MCOperand::CreateImm(align)); 3648 if (Rm != 0xF) { 3649 if (Rm != 0xD) { 3650 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3651 return MCDisassembler::Fail; 3652 } else 3653 Inst.addOperand(MCOperand::CreateReg(0)); 3654 } 3655 3656 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3657 return MCDisassembler::Fail; 3658 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3659 return MCDisassembler::Fail; 3660 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3661 return MCDisassembler::Fail; 3662 Inst.addOperand(MCOperand::CreateImm(index)); 3663 3664 return S; 3665 } 3666 3667 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 3668 uint64_t Address, const void *Decoder) { 3669 DecodeStatus S = MCDisassembler::Success; 3670 3671 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3672 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3673 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3674 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3675 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3676 3677 unsigned align = 0; 3678 unsigned index = 0; 3679 unsigned inc = 1; 3680 switch (size) { 3681 default: 3682 return MCDisassembler::Fail; 3683 case 0: 3684 if (fieldFromInstruction32(Insn, 4, 1)) 3685 return MCDisassembler::Fail; // UNDEFINED 3686 index = fieldFromInstruction32(Insn, 5, 3); 3687 break; 3688 case 1: 3689 if (fieldFromInstruction32(Insn, 4, 1)) 3690 return MCDisassembler::Fail; // UNDEFINED 3691 index = fieldFromInstruction32(Insn, 6, 2); 3692 if (fieldFromInstruction32(Insn, 5, 1)) 3693 inc = 2; 3694 break; 3695 case 2: 3696 if (fieldFromInstruction32(Insn, 4, 2)) 3697 return MCDisassembler::Fail; // UNDEFINED 3698 index = fieldFromInstruction32(Insn, 7, 1); 3699 if (fieldFromInstruction32(Insn, 6, 1)) 3700 inc = 2; 3701 break; 3702 } 3703 3704 if (Rm != 0xF) { // Writeback 3705 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3706 return MCDisassembler::Fail; 3707 } 3708 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3709 return MCDisassembler::Fail; 3710 Inst.addOperand(MCOperand::CreateImm(align)); 3711 if (Rm != 0xF) { 3712 if (Rm != 0xD) { 3713 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3714 return MCDisassembler::Fail; 3715 } else 3716 Inst.addOperand(MCOperand::CreateReg(0)); 3717 } 3718 3719 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3720 return MCDisassembler::Fail; 3721 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3722 return MCDisassembler::Fail; 3723 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3724 return MCDisassembler::Fail; 3725 Inst.addOperand(MCOperand::CreateImm(index)); 3726 3727 return S; 3728 } 3729 3730 3731 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 3732 uint64_t Address, const void *Decoder) { 3733 DecodeStatus S = MCDisassembler::Success; 3734 3735 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3736 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3737 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3738 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3739 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3740 3741 unsigned align = 0; 3742 unsigned index = 0; 3743 unsigned inc = 1; 3744 switch (size) { 3745 default: 3746 return MCDisassembler::Fail; 3747 case 0: 3748 if (fieldFromInstruction32(Insn, 4, 1)) 3749 align = 4; 3750 index = fieldFromInstruction32(Insn, 5, 3); 3751 break; 3752 case 1: 3753 if (fieldFromInstruction32(Insn, 4, 1)) 3754 align = 8; 3755 index = fieldFromInstruction32(Insn, 6, 2); 3756 if (fieldFromInstruction32(Insn, 5, 1)) 3757 inc = 2; 3758 break; 3759 case 2: 3760 if (fieldFromInstruction32(Insn, 4, 2)) 3761 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3762 index = fieldFromInstruction32(Insn, 7, 1); 3763 if (fieldFromInstruction32(Insn, 6, 1)) 3764 inc = 2; 3765 break; 3766 } 3767 3768 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3769 return MCDisassembler::Fail; 3770 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3771 return MCDisassembler::Fail; 3772 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3773 return MCDisassembler::Fail; 3774 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3775 return MCDisassembler::Fail; 3776 3777 if (Rm != 0xF) { // Writeback 3778 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3779 return MCDisassembler::Fail; 3780 } 3781 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3782 return MCDisassembler::Fail; 3783 Inst.addOperand(MCOperand::CreateImm(align)); 3784 if (Rm != 0xF) { 3785 if (Rm != 0xD) { 3786 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3787 return MCDisassembler::Fail; 3788 } else 3789 Inst.addOperand(MCOperand::CreateReg(0)); 3790 } 3791 3792 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3793 return MCDisassembler::Fail; 3794 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3795 return MCDisassembler::Fail; 3796 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3797 return MCDisassembler::Fail; 3798 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3799 return MCDisassembler::Fail; 3800 Inst.addOperand(MCOperand::CreateImm(index)); 3801 3802 return S; 3803 } 3804 3805 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 3806 uint64_t Address, const void *Decoder) { 3807 DecodeStatus S = MCDisassembler::Success; 3808 3809 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3810 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3811 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3812 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3813 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3814 3815 unsigned align = 0; 3816 unsigned index = 0; 3817 unsigned inc = 1; 3818 switch (size) { 3819 default: 3820 return MCDisassembler::Fail; 3821 case 0: 3822 if (fieldFromInstruction32(Insn, 4, 1)) 3823 align = 4; 3824 index = fieldFromInstruction32(Insn, 5, 3); 3825 break; 3826 case 1: 3827 if (fieldFromInstruction32(Insn, 4, 1)) 3828 align = 8; 3829 index = fieldFromInstruction32(Insn, 6, 2); 3830 if (fieldFromInstruction32(Insn, 5, 1)) 3831 inc = 2; 3832 break; 3833 case 2: 3834 if (fieldFromInstruction32(Insn, 4, 2)) 3835 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3836 index = fieldFromInstruction32(Insn, 7, 1); 3837 if (fieldFromInstruction32(Insn, 6, 1)) 3838 inc = 2; 3839 break; 3840 } 3841 3842 if (Rm != 0xF) { // Writeback 3843 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3844 return MCDisassembler::Fail; 3845 } 3846 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3847 return MCDisassembler::Fail; 3848 Inst.addOperand(MCOperand::CreateImm(align)); 3849 if (Rm != 0xF) { 3850 if (Rm != 0xD) { 3851 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3852 return MCDisassembler::Fail; 3853 } else 3854 Inst.addOperand(MCOperand::CreateReg(0)); 3855 } 3856 3857 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3858 return MCDisassembler::Fail; 3859 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3860 return MCDisassembler::Fail; 3861 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3862 return MCDisassembler::Fail; 3863 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3864 return MCDisassembler::Fail; 3865 Inst.addOperand(MCOperand::CreateImm(index)); 3866 3867 return S; 3868 } 3869 3870 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 3871 uint64_t Address, const void *Decoder) { 3872 DecodeStatus S = MCDisassembler::Success; 3873 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3874 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3875 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3876 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3877 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3878 3879 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3880 S = MCDisassembler::SoftFail; 3881 3882 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3883 return MCDisassembler::Fail; 3884 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3885 return MCDisassembler::Fail; 3886 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3887 return MCDisassembler::Fail; 3888 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3889 return MCDisassembler::Fail; 3890 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3891 return MCDisassembler::Fail; 3892 3893 return S; 3894 } 3895 3896 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 3897 uint64_t Address, const void *Decoder) { 3898 DecodeStatus S = MCDisassembler::Success; 3899 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3900 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3901 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3902 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3903 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3904 3905 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3906 S = MCDisassembler::SoftFail; 3907 3908 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3909 return MCDisassembler::Fail; 3910 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3911 return MCDisassembler::Fail; 3912 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3913 return MCDisassembler::Fail; 3914 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3915 return MCDisassembler::Fail; 3916 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3917 return MCDisassembler::Fail; 3918 3919 return S; 3920 } 3921 3922 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn, 3923 uint64_t Address, const void *Decoder) { 3924 DecodeStatus S = MCDisassembler::Success; 3925 unsigned pred = fieldFromInstruction16(Insn, 4, 4); 3926 // The InstPrinter needs to have the low bit of the predicate in 3927 // the mask operand to be able to print it properly. 3928 unsigned mask = fieldFromInstruction16(Insn, 0, 5); 3929 3930 if (pred == 0xF) { 3931 pred = 0xE; 3932 S = MCDisassembler::SoftFail; 3933 } 3934 3935 if ((mask & 0xF) == 0) { 3936 // Preserve the high bit of the mask, which is the low bit of 3937 // the predicate. 3938 mask &= 0x10; 3939 mask |= 0x8; 3940 S = MCDisassembler::SoftFail; 3941 } 3942 3943 Inst.addOperand(MCOperand::CreateImm(pred)); 3944 Inst.addOperand(MCOperand::CreateImm(mask)); 3945 return S; 3946 } 3947 3948 static DecodeStatus 3949 DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 3950 uint64_t Address, const void *Decoder) { 3951 DecodeStatus S = MCDisassembler::Success; 3952 3953 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3954 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 3955 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3956 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3957 unsigned W = fieldFromInstruction32(Insn, 21, 1); 3958 unsigned U = fieldFromInstruction32(Insn, 23, 1); 3959 unsigned P = fieldFromInstruction32(Insn, 24, 1); 3960 bool writeback = (W == 1) | (P == 0); 3961 3962 addr |= (U << 8) | (Rn << 9); 3963 3964 if (writeback && (Rn == Rt || Rn == Rt2)) 3965 Check(S, MCDisassembler::SoftFail); 3966 if (Rt == Rt2) 3967 Check(S, MCDisassembler::SoftFail); 3968 3969 // Rt 3970 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3971 return MCDisassembler::Fail; 3972 // Rt2 3973 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 3974 return MCDisassembler::Fail; 3975 // Writeback operand 3976 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 3977 return MCDisassembler::Fail; 3978 // addr 3979 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 3980 return MCDisassembler::Fail; 3981 3982 return S; 3983 } 3984 3985 static DecodeStatus 3986 DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 3987 uint64_t Address, const void *Decoder) { 3988 DecodeStatus S = MCDisassembler::Success; 3989 3990 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3991 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 3992 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3993 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3994 unsigned W = fieldFromInstruction32(Insn, 21, 1); 3995 unsigned U = fieldFromInstruction32(Insn, 23, 1); 3996 unsigned P = fieldFromInstruction32(Insn, 24, 1); 3997 bool writeback = (W == 1) | (P == 0); 3998 3999 addr |= (U << 8) | (Rn << 9); 4000 4001 if (writeback && (Rn == Rt || Rn == Rt2)) 4002 Check(S, MCDisassembler::SoftFail); 4003 4004 // Writeback operand 4005 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4006 return MCDisassembler::Fail; 4007 // Rt 4008 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4009 return MCDisassembler::Fail; 4010 // Rt2 4011 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4012 return MCDisassembler::Fail; 4013 // addr 4014 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4015 return MCDisassembler::Fail; 4016 4017 return S; 4018 } 4019 4020 static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn, 4021 uint64_t Address, const void *Decoder) { 4022 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1); 4023 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1); 4024 if (sign1 != sign2) return MCDisassembler::Fail; 4025 4026 unsigned Val = fieldFromInstruction32(Insn, 0, 8); 4027 Val |= fieldFromInstruction32(Insn, 12, 3) << 8; 4028 Val |= fieldFromInstruction32(Insn, 26, 1) << 11; 4029 Val |= sign1 << 12; 4030 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4031 4032 return MCDisassembler::Success; 4033 } 4034 4035 static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, uint32_t Val, 4036 uint64_t Address, 4037 const void *Decoder) { 4038 DecodeStatus S = MCDisassembler::Success; 4039 4040 // Shift of "asr #32" is not allowed in Thumb2 mode. 4041 if (Val == 0x20) S = MCDisassembler::SoftFail; 4042 Inst.addOperand(MCOperand::CreateImm(Val)); 4043 return S; 4044 } 4045 4046