1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARM.h" 13 #include "ARMRegisterInfo.h" 14 #include "ARMSubtarget.h" 15 #include "MCTargetDesc/ARMAddressingModes.h" 16 #include "MCTargetDesc/ARMMCExpr.h" 17 #include "MCTargetDesc/ARMBaseInfo.h" 18 #include "llvm/MC/EDInstInfo.h" 19 #include "llvm/MC/MCInst.h" 20 #include "llvm/MC/MCExpr.h" 21 #include "llvm/MC/MCContext.h" 22 #include "llvm/MC/MCDisassembler.h" 23 #include "llvm/Support/Debug.h" 24 #include "llvm/Support/MemoryObject.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include "llvm/Support/raw_ostream.h" 28 29 using namespace llvm; 30 31 typedef MCDisassembler::DecodeStatus DecodeStatus; 32 33 namespace { 34 /// ARMDisassembler - ARM disassembler for all ARM platforms. 35 class ARMDisassembler : public MCDisassembler { 36 public: 37 /// Constructor - Initializes the disassembler. 38 /// 39 ARMDisassembler(const MCSubtargetInfo &STI) : 40 MCDisassembler(STI) { 41 } 42 43 ~ARMDisassembler() { 44 } 45 46 /// getInstruction - See MCDisassembler. 47 DecodeStatus getInstruction(MCInst &instr, 48 uint64_t &size, 49 const MemoryObject ®ion, 50 uint64_t address, 51 raw_ostream &vStream, 52 raw_ostream &cStream) const; 53 54 /// getEDInfo - See MCDisassembler. 55 EDInstInfo *getEDInfo() const; 56 private: 57 }; 58 59 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 60 class ThumbDisassembler : public MCDisassembler { 61 public: 62 /// Constructor - Initializes the disassembler. 63 /// 64 ThumbDisassembler(const MCSubtargetInfo &STI) : 65 MCDisassembler(STI) { 66 } 67 68 ~ThumbDisassembler() { 69 } 70 71 /// getInstruction - See MCDisassembler. 72 DecodeStatus getInstruction(MCInst &instr, 73 uint64_t &size, 74 const MemoryObject ®ion, 75 uint64_t address, 76 raw_ostream &vStream, 77 raw_ostream &cStream) const; 78 79 /// getEDInfo - See MCDisassembler. 80 EDInstInfo *getEDInfo() const; 81 private: 82 mutable std::vector<unsigned> ITBlock; 83 DecodeStatus AddThumbPredicate(MCInst&) const; 84 void UpdateThumbVFPPredicate(MCInst&) const; 85 }; 86 } 87 88 static bool Check(DecodeStatus &Out, DecodeStatus In) { 89 switch (In) { 90 case MCDisassembler::Success: 91 // Out stays the same. 92 return true; 93 case MCDisassembler::SoftFail: 94 Out = In; 95 return true; 96 case MCDisassembler::Fail: 97 Out = In; 98 return false; 99 } 100 return false; 101 } 102 103 104 // Forward declare these because the autogenerated code will reference them. 105 // Definitions are further down. 106 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 107 uint64_t Address, const void *Decoder); 108 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, 109 unsigned RegNo, uint64_t Address, 110 const void *Decoder); 111 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 112 uint64_t Address, const void *Decoder); 113 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 114 uint64_t Address, const void *Decoder); 115 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 116 uint64_t Address, const void *Decoder); 117 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 118 uint64_t Address, const void *Decoder); 119 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 120 uint64_t Address, const void *Decoder); 121 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 122 uint64_t Address, const void *Decoder); 123 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, 124 unsigned RegNo, 125 uint64_t Address, 126 const void *Decoder); 127 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 128 uint64_t Address, const void *Decoder); 129 130 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 131 uint64_t Address, const void *Decoder); 132 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 133 uint64_t Address, const void *Decoder); 134 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 135 uint64_t Address, const void *Decoder); 136 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 137 uint64_t Address, const void *Decoder); 138 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 139 uint64_t Address, const void *Decoder); 140 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 141 uint64_t Address, const void *Decoder); 142 143 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 144 uint64_t Address, const void *Decoder); 145 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 146 uint64_t Address, const void *Decoder); 147 static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, 148 unsigned Insn, 149 uint64_t Address, 150 const void *Decoder); 151 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 152 uint64_t Address, const void *Decoder); 153 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn, 154 uint64_t Address, const void *Decoder); 155 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 156 uint64_t Address, const void *Decoder); 157 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 158 uint64_t Address, const void *Decoder); 159 160 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 161 unsigned Insn, 162 uint64_t Adddress, 163 const void *Decoder); 164 static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 165 uint64_t Address, const void *Decoder); 166 static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 167 uint64_t Address, const void *Decoder); 168 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 171 uint64_t Address, const void *Decoder); 172 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 173 uint64_t Address, const void *Decoder); 174 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 175 uint64_t Address, const void *Decoder); 176 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 177 uint64_t Address, const void *Decoder); 178 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 179 uint64_t Address, const void *Decoder); 180 static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 185 uint64_t Address, const void *Decoder); 186 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 197 uint64_t Address, const void *Decoder); 198 static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val, 199 uint64_t Address, const void *Decoder); 200 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 201 uint64_t Address, const void *Decoder); 202 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 203 uint64_t Address, const void *Decoder); 204 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 205 uint64_t Address, const void *Decoder); 206 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 207 uint64_t Address, const void *Decoder); 208 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 209 uint64_t Address, const void *Decoder); 210 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 211 uint64_t Address, const void *Decoder); 212 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 213 uint64_t Address, const void *Decoder); 214 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 215 uint64_t Address, const void *Decoder); 216 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 217 uint64_t Address, const void *Decoder); 218 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 219 uint64_t Address, const void *Decoder); 220 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 221 uint64_t Address, const void *Decoder); 222 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 223 uint64_t Address, const void *Decoder); 224 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 225 uint64_t Address, const void *Decoder); 226 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 231 uint64_t Address, const void *Decoder); 232 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 233 uint64_t Address, const void *Decoder); 234 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 237 uint64_t Address, const void *Decoder); 238 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 239 uint64_t Address, const void *Decoder); 240 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 251 uint64_t Address, const void *Decoder); 252 253 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 254 uint64_t Address, const void *Decoder); 255 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 256 uint64_t Address, const void *Decoder); 257 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 258 uint64_t Address, const void *Decoder); 259 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 260 uint64_t Address, const void *Decoder); 261 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 262 uint64_t Address, const void *Decoder); 263 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 264 uint64_t Address, const void *Decoder); 265 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 266 uint64_t Address, const void *Decoder); 267 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 268 uint64_t Address, const void *Decoder); 269 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 270 uint64_t Address, const void *Decoder); 271 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 272 uint64_t Address, const void *Decoder); 273 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 274 uint64_t Address, const void *Decoder); 275 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 276 uint64_t Address, const void *Decoder); 277 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, 278 uint64_t Address, const void *Decoder); 279 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 280 uint64_t Address, const void *Decoder); 281 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 282 uint64_t Address, const void *Decoder); 283 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 284 uint64_t Address, const void *Decoder); 285 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 286 uint64_t Address, const void *Decoder); 287 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 288 uint64_t Address, const void *Decoder); 289 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 290 uint64_t Address, const void *Decoder); 291 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 292 uint64_t Address, const void *Decoder); 293 static DecodeStatus DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Val, 294 uint64_t Address, const void *Decoder); 295 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 296 uint64_t Address, const void *Decoder); 297 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 298 uint64_t Address, const void *Decoder); 299 static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val, 300 uint64_t Address, const void *Decoder); 301 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 302 uint64_t Address, const void *Decoder); 303 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val, 304 uint64_t Address, const void *Decoder); 305 static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 306 uint64_t Address, const void *Decoder); 307 static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 308 uint64_t Address, const void *Decoder); 309 static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val, 310 uint64_t Address, const void *Decoder); 311 static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val, 312 uint64_t Address, const void *Decoder); 313 static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, unsigned Val, 314 uint64_t Address, const void *Decoder); 315 316 317 318 #include "ARMGenDisassemblerTables.inc" 319 #include "ARMGenInstrInfo.inc" 320 #include "ARMGenEDInfo.inc" 321 322 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 323 return new ARMDisassembler(STI); 324 } 325 326 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 327 return new ThumbDisassembler(STI); 328 } 329 330 EDInstInfo *ARMDisassembler::getEDInfo() const { 331 return instInfoARM; 332 } 333 334 EDInstInfo *ThumbDisassembler::getEDInfo() const { 335 return instInfoARM; 336 } 337 338 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 339 const MemoryObject &Region, 340 uint64_t Address, 341 raw_ostream &os, 342 raw_ostream &cs) const { 343 CommentStream = &cs; 344 345 uint8_t bytes[4]; 346 347 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 348 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 349 350 // We want to read exactly 4 bytes of data. 351 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 352 Size = 0; 353 return MCDisassembler::Fail; 354 } 355 356 // Encoded as a small-endian 32-bit word in the stream. 357 uint32_t insn = (bytes[3] << 24) | 358 (bytes[2] << 16) | 359 (bytes[1] << 8) | 360 (bytes[0] << 0); 361 362 // Calling the auto-generated decoder function. 363 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI); 364 if (result != MCDisassembler::Fail) { 365 Size = 4; 366 return result; 367 } 368 369 // VFP and NEON instructions, similarly, are shared between ARM 370 // and Thumb modes. 371 MI.clear(); 372 result = decodeVFPInstruction32(MI, insn, Address, this, STI); 373 if (result != MCDisassembler::Fail) { 374 Size = 4; 375 return result; 376 } 377 378 MI.clear(); 379 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI); 380 if (result != MCDisassembler::Fail) { 381 Size = 4; 382 // Add a fake predicate operand, because we share these instruction 383 // definitions with Thumb2 where these instructions are predicable. 384 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 385 return MCDisassembler::Fail; 386 return result; 387 } 388 389 MI.clear(); 390 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI); 391 if (result != MCDisassembler::Fail) { 392 Size = 4; 393 // Add a fake predicate operand, because we share these instruction 394 // definitions with Thumb2 where these instructions are predicable. 395 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 396 return MCDisassembler::Fail; 397 return result; 398 } 399 400 MI.clear(); 401 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI); 402 if (result != MCDisassembler::Fail) { 403 Size = 4; 404 // Add a fake predicate operand, because we share these instruction 405 // definitions with Thumb2 where these instructions are predicable. 406 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 407 return MCDisassembler::Fail; 408 return result; 409 } 410 411 MI.clear(); 412 413 Size = 0; 414 return MCDisassembler::Fail; 415 } 416 417 namespace llvm { 418 extern MCInstrDesc ARMInsts[]; 419 } 420 421 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 422 /// immediate Value in the MCInst. The immediate Value has had any PC 423 /// adjustment made by the caller. If the instruction is a branch instruction 424 /// then isBranch is true, else false. If the getOpInfo() function was set as 425 /// part of the setupForSymbolicDisassembly() call then that function is called 426 /// to get any symbolic information at the Address for this instruction. If 427 /// that returns non-zero then the symbolic information it returns is used to 428 /// create an MCExpr and that is added as an operand to the MCInst. If 429 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 430 /// Value is done and if a symbol is found an MCExpr is created with that, else 431 /// an MCExpr with Value is created. This function returns true if it adds an 432 /// operand to the MCInst and false otherwise. 433 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 434 bool isBranch, uint64_t InstSize, 435 MCInst &MI, const void *Decoder) { 436 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 437 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback(); 438 if (!getOpInfo) 439 return false; 440 441 struct LLVMOpInfo1 SymbolicOp; 442 SymbolicOp.Value = Value; 443 void *DisInfo = Dis->getDisInfoBlock(); 444 if (!getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) { 445 if (isBranch) { 446 LLVMSymbolLookupCallback SymbolLookUp = 447 Dis->getLLVMSymbolLookupCallback(); 448 if (SymbolLookUp) { 449 uint64_t ReferenceType; 450 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch; 451 const char *ReferenceName; 452 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address, 453 &ReferenceName); 454 if (Name) { 455 SymbolicOp.AddSymbol.Name = Name; 456 SymbolicOp.AddSymbol.Present = true; 457 SymbolicOp.Value = 0; 458 } 459 else { 460 SymbolicOp.Value = Value; 461 } 462 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub) 463 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName; 464 } 465 else { 466 return false; 467 } 468 } 469 else { 470 return false; 471 } 472 } 473 474 MCContext *Ctx = Dis->getMCContext(); 475 const MCExpr *Add = NULL; 476 if (SymbolicOp.AddSymbol.Present) { 477 if (SymbolicOp.AddSymbol.Name) { 478 StringRef Name(SymbolicOp.AddSymbol.Name); 479 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 480 Add = MCSymbolRefExpr::Create(Sym, *Ctx); 481 } else { 482 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx); 483 } 484 } 485 486 const MCExpr *Sub = NULL; 487 if (SymbolicOp.SubtractSymbol.Present) { 488 if (SymbolicOp.SubtractSymbol.Name) { 489 StringRef Name(SymbolicOp.SubtractSymbol.Name); 490 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 491 Sub = MCSymbolRefExpr::Create(Sym, *Ctx); 492 } else { 493 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx); 494 } 495 } 496 497 const MCExpr *Off = NULL; 498 if (SymbolicOp.Value != 0) 499 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx); 500 501 const MCExpr *Expr; 502 if (Sub) { 503 const MCExpr *LHS; 504 if (Add) 505 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx); 506 else 507 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx); 508 if (Off != 0) 509 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx); 510 else 511 Expr = LHS; 512 } else if (Add) { 513 if (Off != 0) 514 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx); 515 else 516 Expr = Add; 517 } else { 518 if (Off != 0) 519 Expr = Off; 520 else 521 Expr = MCConstantExpr::Create(0, *Ctx); 522 } 523 524 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16) 525 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx))); 526 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16) 527 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx))); 528 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None) 529 MI.addOperand(MCOperand::CreateExpr(Expr)); 530 else 531 assert("bad SymbolicOp.VariantKind"); 532 533 return true; 534 } 535 536 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 537 /// referenced by a load instruction with the base register that is the Pc. 538 /// These can often be values in a literal pool near the Address of the 539 /// instruction. The Address of the instruction and its immediate Value are 540 /// used as a possible literal pool entry. The SymbolLookUp call back will 541 /// return the name of a symbol referenced by the the literal pool's entry if 542 /// the referenced address is that of a symbol. Or it will return a pointer to 543 /// a literal 'C' string if the referenced address of the literal pool's entry 544 /// is an address into a section with 'C' string literals. 545 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 546 const void *Decoder) { 547 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 548 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 549 if (SymbolLookUp) { 550 void *DisInfo = Dis->getDisInfoBlock(); 551 uint64_t ReferenceType; 552 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load; 553 const char *ReferenceName; 554 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName); 555 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr || 556 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr) 557 (*Dis->CommentStream) << "literal pool for: " << ReferenceName; 558 } 559 } 560 561 // Thumb1 instructions don't have explicit S bits. Rather, they 562 // implicitly set CPSR. Since it's not represented in the encoding, the 563 // auto-generated decoder won't inject the CPSR operand. We need to fix 564 // that as a post-pass. 565 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 566 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 567 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 568 MCInst::iterator I = MI.begin(); 569 for (unsigned i = 0; i < NumOps; ++i, ++I) { 570 if (I == MI.end()) break; 571 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 572 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 573 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 574 return; 575 } 576 } 577 578 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 579 } 580 581 // Most Thumb instructions don't have explicit predicates in the 582 // encoding, but rather get their predicates from IT context. We need 583 // to fix up the predicate operands using this context information as a 584 // post-pass. 585 MCDisassembler::DecodeStatus 586 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 587 MCDisassembler::DecodeStatus S = Success; 588 589 // A few instructions actually have predicates encoded in them. Don't 590 // try to overwrite it if we're seeing one of those. 591 switch (MI.getOpcode()) { 592 case ARM::tBcc: 593 case ARM::t2Bcc: 594 case ARM::tCBZ: 595 case ARM::tCBNZ: 596 case ARM::tCPS: 597 case ARM::t2CPS3p: 598 case ARM::t2CPS2p: 599 case ARM::t2CPS1p: 600 case ARM::tMOVSr: 601 // Some instructions (mostly conditional branches) are not 602 // allowed in IT blocks. 603 if (!ITBlock.empty()) 604 S = SoftFail; 605 else 606 return Success; 607 break; 608 case ARM::tB: 609 case ARM::t2B: 610 case ARM::t2TBB: 611 case ARM::t2TBH: 612 // Some instructions (mostly unconditional branches) can 613 // only appears at the end of, or outside of, an IT. 614 if (ITBlock.size() > 1) 615 S = SoftFail; 616 break; 617 default: 618 break; 619 } 620 621 // If we're in an IT block, base the predicate on that. Otherwise, 622 // assume a predicate of AL. 623 unsigned CC; 624 if (!ITBlock.empty()) { 625 CC = ITBlock.back(); 626 if (CC == 0xF) 627 CC = ARMCC::AL; 628 ITBlock.pop_back(); 629 } else 630 CC = ARMCC::AL; 631 632 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 633 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 634 MCInst::iterator I = MI.begin(); 635 for (unsigned i = 0; i < NumOps; ++i, ++I) { 636 if (I == MI.end()) break; 637 if (OpInfo[i].isPredicate()) { 638 I = MI.insert(I, MCOperand::CreateImm(CC)); 639 ++I; 640 if (CC == ARMCC::AL) 641 MI.insert(I, MCOperand::CreateReg(0)); 642 else 643 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 644 return S; 645 } 646 } 647 648 I = MI.insert(I, MCOperand::CreateImm(CC)); 649 ++I; 650 if (CC == ARMCC::AL) 651 MI.insert(I, MCOperand::CreateReg(0)); 652 else 653 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 654 655 return S; 656 } 657 658 // Thumb VFP instructions are a special case. Because we share their 659 // encodings between ARM and Thumb modes, and they are predicable in ARM 660 // mode, the auto-generated decoder will give them an (incorrect) 661 // predicate operand. We need to rewrite these operands based on the IT 662 // context as a post-pass. 663 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 664 unsigned CC; 665 if (!ITBlock.empty()) { 666 CC = ITBlock.back(); 667 ITBlock.pop_back(); 668 } else 669 CC = ARMCC::AL; 670 671 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 672 MCInst::iterator I = MI.begin(); 673 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 674 for (unsigned i = 0; i < NumOps; ++i, ++I) { 675 if (OpInfo[i].isPredicate() ) { 676 I->setImm(CC); 677 ++I; 678 if (CC == ARMCC::AL) 679 I->setReg(0); 680 else 681 I->setReg(ARM::CPSR); 682 return; 683 } 684 } 685 } 686 687 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 688 const MemoryObject &Region, 689 uint64_t Address, 690 raw_ostream &os, 691 raw_ostream &cs) const { 692 CommentStream = &cs; 693 694 uint8_t bytes[4]; 695 696 assert((STI.getFeatureBits() & ARM::ModeThumb) && 697 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 698 699 // We want to read exactly 2 bytes of data. 700 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 701 Size = 0; 702 return MCDisassembler::Fail; 703 } 704 705 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 706 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI); 707 if (result != MCDisassembler::Fail) { 708 Size = 2; 709 Check(result, AddThumbPredicate(MI)); 710 return result; 711 } 712 713 MI.clear(); 714 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI); 715 if (result) { 716 Size = 2; 717 bool InITBlock = !ITBlock.empty(); 718 Check(result, AddThumbPredicate(MI)); 719 AddThumb1SBit(MI, InITBlock); 720 return result; 721 } 722 723 MI.clear(); 724 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI); 725 if (result != MCDisassembler::Fail) { 726 Size = 2; 727 728 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 729 // the Thumb predicate. 730 if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty()) 731 result = MCDisassembler::SoftFail; 732 733 Check(result, AddThumbPredicate(MI)); 734 735 // If we find an IT instruction, we need to parse its condition 736 // code and mask operands so that we can apply them correctly 737 // to the subsequent instructions. 738 if (MI.getOpcode() == ARM::t2IT) { 739 740 // (3 - the number of trailing zeros) is the number of then / else. 741 unsigned firstcond = MI.getOperand(0).getImm(); 742 unsigned Mask = MI.getOperand(1).getImm(); 743 unsigned CondBit0 = Mask >> 4 & 1; 744 unsigned NumTZ = CountTrailingZeros_32(Mask); 745 assert(NumTZ <= 3 && "Invalid IT mask!"); 746 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { 747 bool T = ((Mask >> Pos) & 1) == CondBit0; 748 if (T) 749 ITBlock.insert(ITBlock.begin(), firstcond); 750 else 751 ITBlock.insert(ITBlock.begin(), firstcond ^ 1); 752 } 753 754 ITBlock.push_back(firstcond); 755 } 756 757 return result; 758 } 759 760 // We want to read exactly 4 bytes of data. 761 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 762 Size = 0; 763 return MCDisassembler::Fail; 764 } 765 766 uint32_t insn32 = (bytes[3] << 8) | 767 (bytes[2] << 0) | 768 (bytes[1] << 24) | 769 (bytes[0] << 16); 770 MI.clear(); 771 result = decodeThumbInstruction32(MI, insn32, Address, this, STI); 772 if (result != MCDisassembler::Fail) { 773 Size = 4; 774 bool InITBlock = ITBlock.size(); 775 Check(result, AddThumbPredicate(MI)); 776 AddThumb1SBit(MI, InITBlock); 777 return result; 778 } 779 780 MI.clear(); 781 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI); 782 if (result != MCDisassembler::Fail) { 783 Size = 4; 784 Check(result, AddThumbPredicate(MI)); 785 return result; 786 } 787 788 MI.clear(); 789 result = decodeVFPInstruction32(MI, insn32, Address, this, STI); 790 if (result != MCDisassembler::Fail) { 791 Size = 4; 792 UpdateThumbVFPPredicate(MI); 793 return result; 794 } 795 796 MI.clear(); 797 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI); 798 if (result != MCDisassembler::Fail) { 799 Size = 4; 800 Check(result, AddThumbPredicate(MI)); 801 return result; 802 } 803 804 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 805 MI.clear(); 806 uint32_t NEONLdStInsn = insn32; 807 NEONLdStInsn &= 0xF0FFFFFF; 808 NEONLdStInsn |= 0x04000000; 809 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI); 810 if (result != MCDisassembler::Fail) { 811 Size = 4; 812 Check(result, AddThumbPredicate(MI)); 813 return result; 814 } 815 } 816 817 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 818 MI.clear(); 819 uint32_t NEONDataInsn = insn32; 820 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 821 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 822 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 823 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI); 824 if (result != MCDisassembler::Fail) { 825 Size = 4; 826 Check(result, AddThumbPredicate(MI)); 827 return result; 828 } 829 } 830 831 Size = 0; 832 return MCDisassembler::Fail; 833 } 834 835 836 extern "C" void LLVMInitializeARMDisassembler() { 837 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 838 createARMDisassembler); 839 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 840 createThumbDisassembler); 841 } 842 843 static const unsigned GPRDecoderTable[] = { 844 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 845 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 846 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 847 ARM::R12, ARM::SP, ARM::LR, ARM::PC 848 }; 849 850 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 851 uint64_t Address, const void *Decoder) { 852 if (RegNo > 15) 853 return MCDisassembler::Fail; 854 855 unsigned Register = GPRDecoderTable[RegNo]; 856 Inst.addOperand(MCOperand::CreateReg(Register)); 857 return MCDisassembler::Success; 858 } 859 860 static DecodeStatus 861 DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 862 uint64_t Address, const void *Decoder) { 863 if (RegNo == 15) return MCDisassembler::Fail; 864 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 865 } 866 867 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 868 uint64_t Address, const void *Decoder) { 869 if (RegNo > 7) 870 return MCDisassembler::Fail; 871 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 872 } 873 874 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 875 uint64_t Address, const void *Decoder) { 876 unsigned Register = 0; 877 switch (RegNo) { 878 case 0: 879 Register = ARM::R0; 880 break; 881 case 1: 882 Register = ARM::R1; 883 break; 884 case 2: 885 Register = ARM::R2; 886 break; 887 case 3: 888 Register = ARM::R3; 889 break; 890 case 9: 891 Register = ARM::R9; 892 break; 893 case 12: 894 Register = ARM::R12; 895 break; 896 default: 897 return MCDisassembler::Fail; 898 } 899 900 Inst.addOperand(MCOperand::CreateReg(Register)); 901 return MCDisassembler::Success; 902 } 903 904 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 905 uint64_t Address, const void *Decoder) { 906 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 907 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 908 } 909 910 static const unsigned SPRDecoderTable[] = { 911 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 912 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 913 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 914 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 915 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 916 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 917 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 918 ARM::S28, ARM::S29, ARM::S30, ARM::S31 919 }; 920 921 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 922 uint64_t Address, const void *Decoder) { 923 if (RegNo > 31) 924 return MCDisassembler::Fail; 925 926 unsigned Register = SPRDecoderTable[RegNo]; 927 Inst.addOperand(MCOperand::CreateReg(Register)); 928 return MCDisassembler::Success; 929 } 930 931 static const unsigned DPRDecoderTable[] = { 932 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 933 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 934 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 935 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 936 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 937 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 938 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 939 ARM::D28, ARM::D29, ARM::D30, ARM::D31 940 }; 941 942 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 943 uint64_t Address, const void *Decoder) { 944 if (RegNo > 31) 945 return MCDisassembler::Fail; 946 947 unsigned Register = DPRDecoderTable[RegNo]; 948 Inst.addOperand(MCOperand::CreateReg(Register)); 949 return MCDisassembler::Success; 950 } 951 952 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 953 uint64_t Address, const void *Decoder) { 954 if (RegNo > 7) 955 return MCDisassembler::Fail; 956 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 957 } 958 959 static DecodeStatus 960 DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 961 uint64_t Address, const void *Decoder) { 962 if (RegNo > 15) 963 return MCDisassembler::Fail; 964 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 965 } 966 967 static const unsigned QPRDecoderTable[] = { 968 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 969 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 970 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 971 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 972 }; 973 974 975 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 976 uint64_t Address, const void *Decoder) { 977 if (RegNo > 31) 978 return MCDisassembler::Fail; 979 RegNo >>= 1; 980 981 unsigned Register = QPRDecoderTable[RegNo]; 982 Inst.addOperand(MCOperand::CreateReg(Register)); 983 return MCDisassembler::Success; 984 } 985 986 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 987 uint64_t Address, const void *Decoder) { 988 if (Val == 0xF) return MCDisassembler::Fail; 989 // AL predicate is not allowed on Thumb1 branches. 990 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 991 return MCDisassembler::Fail; 992 Inst.addOperand(MCOperand::CreateImm(Val)); 993 if (Val == ARMCC::AL) { 994 Inst.addOperand(MCOperand::CreateReg(0)); 995 } else 996 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 997 return MCDisassembler::Success; 998 } 999 1000 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 1001 uint64_t Address, const void *Decoder) { 1002 if (Val) 1003 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1004 else 1005 Inst.addOperand(MCOperand::CreateReg(0)); 1006 return MCDisassembler::Success; 1007 } 1008 1009 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 1010 uint64_t Address, const void *Decoder) { 1011 uint32_t imm = Val & 0xFF; 1012 uint32_t rot = (Val & 0xF00) >> 7; 1013 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); 1014 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1015 return MCDisassembler::Success; 1016 } 1017 1018 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 1019 uint64_t Address, const void *Decoder) { 1020 DecodeStatus S = MCDisassembler::Success; 1021 1022 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1023 unsigned type = fieldFromInstruction32(Val, 5, 2); 1024 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1025 1026 // Register-immediate 1027 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1028 return MCDisassembler::Fail; 1029 1030 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1031 switch (type) { 1032 case 0: 1033 Shift = ARM_AM::lsl; 1034 break; 1035 case 1: 1036 Shift = ARM_AM::lsr; 1037 break; 1038 case 2: 1039 Shift = ARM_AM::asr; 1040 break; 1041 case 3: 1042 Shift = ARM_AM::ror; 1043 break; 1044 } 1045 1046 if (Shift == ARM_AM::ror && imm == 0) 1047 Shift = ARM_AM::rrx; 1048 1049 unsigned Op = Shift | (imm << 3); 1050 Inst.addOperand(MCOperand::CreateImm(Op)); 1051 1052 return S; 1053 } 1054 1055 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 1056 uint64_t Address, const void *Decoder) { 1057 DecodeStatus S = MCDisassembler::Success; 1058 1059 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1060 unsigned type = fieldFromInstruction32(Val, 5, 2); 1061 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 1062 1063 // Register-register 1064 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1065 return MCDisassembler::Fail; 1066 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1067 return MCDisassembler::Fail; 1068 1069 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1070 switch (type) { 1071 case 0: 1072 Shift = ARM_AM::lsl; 1073 break; 1074 case 1: 1075 Shift = ARM_AM::lsr; 1076 break; 1077 case 2: 1078 Shift = ARM_AM::asr; 1079 break; 1080 case 3: 1081 Shift = ARM_AM::ror; 1082 break; 1083 } 1084 1085 Inst.addOperand(MCOperand::CreateImm(Shift)); 1086 1087 return S; 1088 } 1089 1090 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 1091 uint64_t Address, const void *Decoder) { 1092 DecodeStatus S = MCDisassembler::Success; 1093 1094 bool writebackLoad = false; 1095 unsigned writebackReg = 0; 1096 switch (Inst.getOpcode()) { 1097 default: 1098 break; 1099 case ARM::LDMIA_UPD: 1100 case ARM::LDMDB_UPD: 1101 case ARM::LDMIB_UPD: 1102 case ARM::LDMDA_UPD: 1103 case ARM::t2LDMIA_UPD: 1104 case ARM::t2LDMDB_UPD: 1105 writebackLoad = true; 1106 writebackReg = Inst.getOperand(0).getReg(); 1107 break; 1108 } 1109 1110 // Empty register lists are not allowed. 1111 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; 1112 for (unsigned i = 0; i < 16; ++i) { 1113 if (Val & (1 << i)) { 1114 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1115 return MCDisassembler::Fail; 1116 // Writeback not allowed if Rn is in the target list. 1117 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 1118 Check(S, MCDisassembler::SoftFail); 1119 } 1120 } 1121 1122 return S; 1123 } 1124 1125 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 1126 uint64_t Address, const void *Decoder) { 1127 DecodeStatus S = MCDisassembler::Success; 1128 1129 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 1130 unsigned regs = Val & 0xFF; 1131 1132 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1133 return MCDisassembler::Fail; 1134 for (unsigned i = 0; i < (regs - 1); ++i) { 1135 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1136 return MCDisassembler::Fail; 1137 } 1138 1139 return S; 1140 } 1141 1142 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 1143 uint64_t Address, const void *Decoder) { 1144 DecodeStatus S = MCDisassembler::Success; 1145 1146 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 1147 unsigned regs = (Val & 0xFF) / 2; 1148 1149 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1150 return MCDisassembler::Fail; 1151 for (unsigned i = 0; i < (regs - 1); ++i) { 1152 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1153 return MCDisassembler::Fail; 1154 } 1155 1156 return S; 1157 } 1158 1159 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 1160 uint64_t Address, const void *Decoder) { 1161 // This operand encodes a mask of contiguous zeros between a specified MSB 1162 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1163 // the mask of all bits LSB-and-lower, and then xor them to create 1164 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1165 // create the final mask. 1166 unsigned msb = fieldFromInstruction32(Val, 5, 5); 1167 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 1168 1169 DecodeStatus S = MCDisassembler::Success; 1170 if (lsb > msb) Check(S, MCDisassembler::SoftFail); 1171 1172 uint32_t msb_mask = 0xFFFFFFFF; 1173 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1174 uint32_t lsb_mask = (1U << lsb) - 1; 1175 1176 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1177 return S; 1178 } 1179 1180 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 1181 uint64_t Address, const void *Decoder) { 1182 DecodeStatus S = MCDisassembler::Success; 1183 1184 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1185 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 1186 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 1187 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 1188 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1189 unsigned U = fieldFromInstruction32(Insn, 23, 1); 1190 1191 switch (Inst.getOpcode()) { 1192 case ARM::LDC_OFFSET: 1193 case ARM::LDC_PRE: 1194 case ARM::LDC_POST: 1195 case ARM::LDC_OPTION: 1196 case ARM::LDCL_OFFSET: 1197 case ARM::LDCL_PRE: 1198 case ARM::LDCL_POST: 1199 case ARM::LDCL_OPTION: 1200 case ARM::STC_OFFSET: 1201 case ARM::STC_PRE: 1202 case ARM::STC_POST: 1203 case ARM::STC_OPTION: 1204 case ARM::STCL_OFFSET: 1205 case ARM::STCL_PRE: 1206 case ARM::STCL_POST: 1207 case ARM::STCL_OPTION: 1208 case ARM::t2LDC_OFFSET: 1209 case ARM::t2LDC_PRE: 1210 case ARM::t2LDC_POST: 1211 case ARM::t2LDC_OPTION: 1212 case ARM::t2LDCL_OFFSET: 1213 case ARM::t2LDCL_PRE: 1214 case ARM::t2LDCL_POST: 1215 case ARM::t2LDCL_OPTION: 1216 case ARM::t2STC_OFFSET: 1217 case ARM::t2STC_PRE: 1218 case ARM::t2STC_POST: 1219 case ARM::t2STC_OPTION: 1220 case ARM::t2STCL_OFFSET: 1221 case ARM::t2STCL_PRE: 1222 case ARM::t2STCL_POST: 1223 case ARM::t2STCL_OPTION: 1224 if (coproc == 0xA || coproc == 0xB) 1225 return MCDisassembler::Fail; 1226 break; 1227 default: 1228 break; 1229 } 1230 1231 Inst.addOperand(MCOperand::CreateImm(coproc)); 1232 Inst.addOperand(MCOperand::CreateImm(CRd)); 1233 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1234 return MCDisassembler::Fail; 1235 1236 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1237 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1238 1239 bool writeback = (P == 0) || (W == 1); 1240 unsigned idx_mode = 0; 1241 if (P && writeback) 1242 idx_mode = ARMII::IndexModePre; 1243 else if (!P && writeback) 1244 idx_mode = ARMII::IndexModePost; 1245 1246 switch (Inst.getOpcode()) { 1247 case ARM::LDCL_POST: 1248 case ARM::STCL_POST: 1249 case ARM::t2LDCL_POST: 1250 case ARM::t2STCL_POST: 1251 case ARM::LDC2L_POST: 1252 case ARM::STC2L_POST: 1253 imm |= U << 8; 1254 case ARM::LDC_OPTION: 1255 case ARM::LDCL_OPTION: 1256 case ARM::LDC2_OPTION: 1257 case ARM::LDC2L_OPTION: 1258 case ARM::STC_OPTION: 1259 case ARM::STCL_OPTION: 1260 case ARM::STC2_OPTION: 1261 case ARM::STC2L_OPTION: 1262 case ARM::t2LDC_OPTION: 1263 case ARM::t2LDCL_OPTION: 1264 case ARM::t2STC_OPTION: 1265 case ARM::t2STCL_OPTION: 1266 Inst.addOperand(MCOperand::CreateImm(imm)); 1267 break; 1268 default: 1269 if (U) 1270 Inst.addOperand(MCOperand::CreateImm( 1271 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode))); 1272 else 1273 Inst.addOperand(MCOperand::CreateImm( 1274 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode))); 1275 break; 1276 } 1277 1278 switch (Inst.getOpcode()) { 1279 case ARM::LDC_OFFSET: 1280 case ARM::LDC_PRE: 1281 case ARM::LDC_POST: 1282 case ARM::LDC_OPTION: 1283 case ARM::LDCL_OFFSET: 1284 case ARM::LDCL_PRE: 1285 case ARM::LDCL_POST: 1286 case ARM::LDCL_OPTION: 1287 case ARM::STC_OFFSET: 1288 case ARM::STC_PRE: 1289 case ARM::STC_POST: 1290 case ARM::STC_OPTION: 1291 case ARM::STCL_OFFSET: 1292 case ARM::STCL_PRE: 1293 case ARM::STCL_POST: 1294 case ARM::STCL_OPTION: 1295 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1296 return MCDisassembler::Fail; 1297 break; 1298 default: 1299 break; 1300 } 1301 1302 return S; 1303 } 1304 1305 static DecodeStatus 1306 DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 1307 uint64_t Address, const void *Decoder) { 1308 DecodeStatus S = MCDisassembler::Success; 1309 1310 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1311 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1312 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1313 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 1314 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1315 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 1316 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1317 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1318 1319 // On stores, the writeback operand precedes Rt. 1320 switch (Inst.getOpcode()) { 1321 case ARM::STR_POST_IMM: 1322 case ARM::STR_POST_REG: 1323 case ARM::STRB_POST_IMM: 1324 case ARM::STRB_POST_REG: 1325 case ARM::STRT_POST_REG: 1326 case ARM::STRT_POST_IMM: 1327 case ARM::STRBT_POST_REG: 1328 case ARM::STRBT_POST_IMM: 1329 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1330 return MCDisassembler::Fail; 1331 break; 1332 default: 1333 break; 1334 } 1335 1336 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1337 return MCDisassembler::Fail; 1338 1339 // On loads, the writeback operand comes after Rt. 1340 switch (Inst.getOpcode()) { 1341 case ARM::LDR_POST_IMM: 1342 case ARM::LDR_POST_REG: 1343 case ARM::LDRB_POST_IMM: 1344 case ARM::LDRB_POST_REG: 1345 case ARM::LDRBT_POST_REG: 1346 case ARM::LDRBT_POST_IMM: 1347 case ARM::LDRT_POST_REG: 1348 case ARM::LDRT_POST_IMM: 1349 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1350 return MCDisassembler::Fail; 1351 break; 1352 default: 1353 break; 1354 } 1355 1356 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1357 return MCDisassembler::Fail; 1358 1359 ARM_AM::AddrOpc Op = ARM_AM::add; 1360 if (!fieldFromInstruction32(Insn, 23, 1)) 1361 Op = ARM_AM::sub; 1362 1363 bool writeback = (P == 0) || (W == 1); 1364 unsigned idx_mode = 0; 1365 if (P && writeback) 1366 idx_mode = ARMII::IndexModePre; 1367 else if (!P && writeback) 1368 idx_mode = ARMII::IndexModePost; 1369 1370 if (writeback && (Rn == 15 || Rn == Rt)) 1371 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1372 1373 if (reg) { 1374 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1375 return MCDisassembler::Fail; 1376 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1377 switch( fieldFromInstruction32(Insn, 5, 2)) { 1378 case 0: 1379 Opc = ARM_AM::lsl; 1380 break; 1381 case 1: 1382 Opc = ARM_AM::lsr; 1383 break; 1384 case 2: 1385 Opc = ARM_AM::asr; 1386 break; 1387 case 3: 1388 Opc = ARM_AM::ror; 1389 break; 1390 default: 1391 return MCDisassembler::Fail; 1392 } 1393 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1394 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1395 1396 Inst.addOperand(MCOperand::CreateImm(imm)); 1397 } else { 1398 Inst.addOperand(MCOperand::CreateReg(0)); 1399 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1400 Inst.addOperand(MCOperand::CreateImm(tmp)); 1401 } 1402 1403 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1404 return MCDisassembler::Fail; 1405 1406 return S; 1407 } 1408 1409 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1410 uint64_t Address, const void *Decoder) { 1411 DecodeStatus S = MCDisassembler::Success; 1412 1413 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1414 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1415 unsigned type = fieldFromInstruction32(Val, 5, 2); 1416 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1417 unsigned U = fieldFromInstruction32(Val, 12, 1); 1418 1419 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1420 switch (type) { 1421 case 0: 1422 ShOp = ARM_AM::lsl; 1423 break; 1424 case 1: 1425 ShOp = ARM_AM::lsr; 1426 break; 1427 case 2: 1428 ShOp = ARM_AM::asr; 1429 break; 1430 case 3: 1431 ShOp = ARM_AM::ror; 1432 break; 1433 } 1434 1435 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1436 return MCDisassembler::Fail; 1437 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1438 return MCDisassembler::Fail; 1439 unsigned shift; 1440 if (U) 1441 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1442 else 1443 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1444 Inst.addOperand(MCOperand::CreateImm(shift)); 1445 1446 return S; 1447 } 1448 1449 static DecodeStatus 1450 DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1451 uint64_t Address, const void *Decoder) { 1452 DecodeStatus S = MCDisassembler::Success; 1453 1454 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1455 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1456 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1457 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1458 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1459 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1460 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1461 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1462 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1463 1464 bool writeback = (W == 1) | (P == 0); 1465 1466 // For {LD,ST}RD, Rt must be even, else undefined. 1467 switch (Inst.getOpcode()) { 1468 case ARM::STRD: 1469 case ARM::STRD_PRE: 1470 case ARM::STRD_POST: 1471 case ARM::LDRD: 1472 case ARM::LDRD_PRE: 1473 case ARM::LDRD_POST: 1474 if (Rt & 0x1) return MCDisassembler::Fail; 1475 break; 1476 default: 1477 break; 1478 } 1479 1480 if (writeback) { // Writeback 1481 if (P) 1482 U |= ARMII::IndexModePre << 9; 1483 else 1484 U |= ARMII::IndexModePost << 9; 1485 1486 // On stores, the writeback operand precedes Rt. 1487 switch (Inst.getOpcode()) { 1488 case ARM::STRD: 1489 case ARM::STRD_PRE: 1490 case ARM::STRD_POST: 1491 case ARM::STRH: 1492 case ARM::STRH_PRE: 1493 case ARM::STRH_POST: 1494 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1495 return MCDisassembler::Fail; 1496 break; 1497 default: 1498 break; 1499 } 1500 } 1501 1502 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1503 return MCDisassembler::Fail; 1504 switch (Inst.getOpcode()) { 1505 case ARM::STRD: 1506 case ARM::STRD_PRE: 1507 case ARM::STRD_POST: 1508 case ARM::LDRD: 1509 case ARM::LDRD_PRE: 1510 case ARM::LDRD_POST: 1511 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1512 return MCDisassembler::Fail; 1513 break; 1514 default: 1515 break; 1516 } 1517 1518 if (writeback) { 1519 // On loads, the writeback operand comes after Rt. 1520 switch (Inst.getOpcode()) { 1521 case ARM::LDRD: 1522 case ARM::LDRD_PRE: 1523 case ARM::LDRD_POST: 1524 case ARM::LDRH: 1525 case ARM::LDRH_PRE: 1526 case ARM::LDRH_POST: 1527 case ARM::LDRSH: 1528 case ARM::LDRSH_PRE: 1529 case ARM::LDRSH_POST: 1530 case ARM::LDRSB: 1531 case ARM::LDRSB_PRE: 1532 case ARM::LDRSB_POST: 1533 case ARM::LDRHTr: 1534 case ARM::LDRSBTr: 1535 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1536 return MCDisassembler::Fail; 1537 break; 1538 default: 1539 break; 1540 } 1541 } 1542 1543 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1544 return MCDisassembler::Fail; 1545 1546 if (type) { 1547 Inst.addOperand(MCOperand::CreateReg(0)); 1548 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1549 } else { 1550 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1551 return MCDisassembler::Fail; 1552 Inst.addOperand(MCOperand::CreateImm(U)); 1553 } 1554 1555 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1556 return MCDisassembler::Fail; 1557 1558 return S; 1559 } 1560 1561 static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1562 uint64_t Address, const void *Decoder) { 1563 DecodeStatus S = MCDisassembler::Success; 1564 1565 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1566 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1567 1568 switch (mode) { 1569 case 0: 1570 mode = ARM_AM::da; 1571 break; 1572 case 1: 1573 mode = ARM_AM::ia; 1574 break; 1575 case 2: 1576 mode = ARM_AM::db; 1577 break; 1578 case 3: 1579 mode = ARM_AM::ib; 1580 break; 1581 } 1582 1583 Inst.addOperand(MCOperand::CreateImm(mode)); 1584 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1585 return MCDisassembler::Fail; 1586 1587 return S; 1588 } 1589 1590 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1591 unsigned Insn, 1592 uint64_t Address, const void *Decoder) { 1593 DecodeStatus S = MCDisassembler::Success; 1594 1595 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1596 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1597 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1598 1599 if (pred == 0xF) { 1600 switch (Inst.getOpcode()) { 1601 case ARM::LDMDA: 1602 Inst.setOpcode(ARM::RFEDA); 1603 break; 1604 case ARM::LDMDA_UPD: 1605 Inst.setOpcode(ARM::RFEDA_UPD); 1606 break; 1607 case ARM::LDMDB: 1608 Inst.setOpcode(ARM::RFEDB); 1609 break; 1610 case ARM::LDMDB_UPD: 1611 Inst.setOpcode(ARM::RFEDB_UPD); 1612 break; 1613 case ARM::LDMIA: 1614 Inst.setOpcode(ARM::RFEIA); 1615 break; 1616 case ARM::LDMIA_UPD: 1617 Inst.setOpcode(ARM::RFEIA_UPD); 1618 break; 1619 case ARM::LDMIB: 1620 Inst.setOpcode(ARM::RFEIB); 1621 break; 1622 case ARM::LDMIB_UPD: 1623 Inst.setOpcode(ARM::RFEIB_UPD); 1624 break; 1625 case ARM::STMDA: 1626 Inst.setOpcode(ARM::SRSDA); 1627 break; 1628 case ARM::STMDA_UPD: 1629 Inst.setOpcode(ARM::SRSDA_UPD); 1630 break; 1631 case ARM::STMDB: 1632 Inst.setOpcode(ARM::SRSDB); 1633 break; 1634 case ARM::STMDB_UPD: 1635 Inst.setOpcode(ARM::SRSDB_UPD); 1636 break; 1637 case ARM::STMIA: 1638 Inst.setOpcode(ARM::SRSIA); 1639 break; 1640 case ARM::STMIA_UPD: 1641 Inst.setOpcode(ARM::SRSIA_UPD); 1642 break; 1643 case ARM::STMIB: 1644 Inst.setOpcode(ARM::SRSIB); 1645 break; 1646 case ARM::STMIB_UPD: 1647 Inst.setOpcode(ARM::SRSIB_UPD); 1648 break; 1649 default: 1650 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1651 } 1652 1653 // For stores (which become SRS's, the only operand is the mode. 1654 if (fieldFromInstruction32(Insn, 20, 1) == 0) { 1655 Inst.addOperand( 1656 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4))); 1657 return S; 1658 } 1659 1660 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1661 } 1662 1663 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1664 return MCDisassembler::Fail; 1665 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1666 return MCDisassembler::Fail; // Tied 1667 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1668 return MCDisassembler::Fail; 1669 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1670 return MCDisassembler::Fail; 1671 1672 return S; 1673 } 1674 1675 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1676 uint64_t Address, const void *Decoder) { 1677 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1678 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1679 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1680 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1681 1682 DecodeStatus S = MCDisassembler::Success; 1683 1684 // imod == '01' --> UNPREDICTABLE 1685 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1686 // return failure here. The '01' imod value is unprintable, so there's 1687 // nothing useful we could do even if we returned UNPREDICTABLE. 1688 1689 if (imod == 1) return MCDisassembler::Fail; 1690 1691 if (imod && M) { 1692 Inst.setOpcode(ARM::CPS3p); 1693 Inst.addOperand(MCOperand::CreateImm(imod)); 1694 Inst.addOperand(MCOperand::CreateImm(iflags)); 1695 Inst.addOperand(MCOperand::CreateImm(mode)); 1696 } else if (imod && !M) { 1697 Inst.setOpcode(ARM::CPS2p); 1698 Inst.addOperand(MCOperand::CreateImm(imod)); 1699 Inst.addOperand(MCOperand::CreateImm(iflags)); 1700 if (mode) S = MCDisassembler::SoftFail; 1701 } else if (!imod && M) { 1702 Inst.setOpcode(ARM::CPS1p); 1703 Inst.addOperand(MCOperand::CreateImm(mode)); 1704 if (iflags) S = MCDisassembler::SoftFail; 1705 } else { 1706 // imod == '00' && M == '0' --> UNPREDICTABLE 1707 Inst.setOpcode(ARM::CPS1p); 1708 Inst.addOperand(MCOperand::CreateImm(mode)); 1709 S = MCDisassembler::SoftFail; 1710 } 1711 1712 return S; 1713 } 1714 1715 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1716 uint64_t Address, const void *Decoder) { 1717 unsigned imod = fieldFromInstruction32(Insn, 9, 2); 1718 unsigned M = fieldFromInstruction32(Insn, 8, 1); 1719 unsigned iflags = fieldFromInstruction32(Insn, 5, 3); 1720 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1721 1722 DecodeStatus S = MCDisassembler::Success; 1723 1724 // imod == '01' --> UNPREDICTABLE 1725 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1726 // return failure here. The '01' imod value is unprintable, so there's 1727 // nothing useful we could do even if we returned UNPREDICTABLE. 1728 1729 if (imod == 1) return MCDisassembler::Fail; 1730 1731 if (imod && M) { 1732 Inst.setOpcode(ARM::t2CPS3p); 1733 Inst.addOperand(MCOperand::CreateImm(imod)); 1734 Inst.addOperand(MCOperand::CreateImm(iflags)); 1735 Inst.addOperand(MCOperand::CreateImm(mode)); 1736 } else if (imod && !M) { 1737 Inst.setOpcode(ARM::t2CPS2p); 1738 Inst.addOperand(MCOperand::CreateImm(imod)); 1739 Inst.addOperand(MCOperand::CreateImm(iflags)); 1740 if (mode) S = MCDisassembler::SoftFail; 1741 } else if (!imod && M) { 1742 Inst.setOpcode(ARM::t2CPS1p); 1743 Inst.addOperand(MCOperand::CreateImm(mode)); 1744 if (iflags) S = MCDisassembler::SoftFail; 1745 } else { 1746 // imod == '00' && M == '0' --> UNPREDICTABLE 1747 Inst.setOpcode(ARM::t2CPS1p); 1748 Inst.addOperand(MCOperand::CreateImm(mode)); 1749 S = MCDisassembler::SoftFail; 1750 } 1751 1752 return S; 1753 } 1754 1755 static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 1756 uint64_t Address, const void *Decoder) { 1757 DecodeStatus S = MCDisassembler::Success; 1758 1759 unsigned Rd = fieldFromInstruction32(Insn, 8, 4); 1760 unsigned imm = 0; 1761 1762 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0); 1763 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8); 1764 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12); 1765 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11); 1766 1767 if (Inst.getOpcode() == ARM::t2MOVTi16) 1768 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1769 return MCDisassembler::Fail; 1770 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1771 return MCDisassembler::Fail; 1772 1773 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1774 Inst.addOperand(MCOperand::CreateImm(imm)); 1775 1776 return S; 1777 } 1778 1779 static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 1780 uint64_t Address, const void *Decoder) { 1781 DecodeStatus S = MCDisassembler::Success; 1782 1783 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1784 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1785 unsigned imm = 0; 1786 1787 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0); 1788 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12); 1789 1790 if (Inst.getOpcode() == ARM::MOVTi16) 1791 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1792 return MCDisassembler::Fail; 1793 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1794 return MCDisassembler::Fail; 1795 1796 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1797 Inst.addOperand(MCOperand::CreateImm(imm)); 1798 1799 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1800 return MCDisassembler::Fail; 1801 1802 return S; 1803 } 1804 1805 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1806 uint64_t Address, const void *Decoder) { 1807 DecodeStatus S = MCDisassembler::Success; 1808 1809 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1810 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1811 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1812 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1813 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1814 1815 if (pred == 0xF) 1816 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1817 1818 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1819 return MCDisassembler::Fail; 1820 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1821 return MCDisassembler::Fail; 1822 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1823 return MCDisassembler::Fail; 1824 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 1825 return MCDisassembler::Fail; 1826 1827 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1828 return MCDisassembler::Fail; 1829 1830 return S; 1831 } 1832 1833 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1834 uint64_t Address, const void *Decoder) { 1835 DecodeStatus S = MCDisassembler::Success; 1836 1837 unsigned add = fieldFromInstruction32(Val, 12, 1); 1838 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1839 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1840 1841 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1842 return MCDisassembler::Fail; 1843 1844 if (!add) imm *= -1; 1845 if (imm == 0 && !add) imm = INT32_MIN; 1846 Inst.addOperand(MCOperand::CreateImm(imm)); 1847 if (Rn == 15) 1848 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 1849 1850 return S; 1851 } 1852 1853 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1854 uint64_t Address, const void *Decoder) { 1855 DecodeStatus S = MCDisassembler::Success; 1856 1857 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1858 unsigned U = fieldFromInstruction32(Val, 8, 1); 1859 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1860 1861 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1862 return MCDisassembler::Fail; 1863 1864 if (U) 1865 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1866 else 1867 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1868 1869 return S; 1870 } 1871 1872 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1873 uint64_t Address, const void *Decoder) { 1874 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1875 } 1876 1877 static DecodeStatus 1878 DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1879 uint64_t Address, const void *Decoder) { 1880 DecodeStatus S = MCDisassembler::Success; 1881 1882 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1883 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1884 1885 if (pred == 0xF) { 1886 Inst.setOpcode(ARM::BLXi); 1887 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1888 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1889 return S; 1890 } 1891 1892 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, true, 1893 4, Inst, Decoder)) 1894 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1895 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1896 return MCDisassembler::Fail; 1897 1898 return S; 1899 } 1900 1901 1902 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1903 uint64_t Address, const void *Decoder) { 1904 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1905 return MCDisassembler::Success; 1906 } 1907 1908 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1909 uint64_t Address, const void *Decoder) { 1910 DecodeStatus S = MCDisassembler::Success; 1911 1912 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1913 unsigned align = fieldFromInstruction32(Val, 4, 2); 1914 1915 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1916 return MCDisassembler::Fail; 1917 if (!align) 1918 Inst.addOperand(MCOperand::CreateImm(0)); 1919 else 1920 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1921 1922 return S; 1923 } 1924 1925 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1926 uint64_t Address, const void *Decoder) { 1927 DecodeStatus S = MCDisassembler::Success; 1928 1929 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1930 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1931 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1932 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1933 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1934 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1935 1936 // First output register 1937 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 1938 return MCDisassembler::Fail; 1939 1940 // Second output register 1941 switch (Inst.getOpcode()) { 1942 case ARM::VLD1q8: 1943 case ARM::VLD1q16: 1944 case ARM::VLD1q32: 1945 case ARM::VLD1q64: 1946 case ARM::VLD1q8_UPD: 1947 case ARM::VLD1q16_UPD: 1948 case ARM::VLD1q32_UPD: 1949 case ARM::VLD1q64_UPD: 1950 case ARM::VLD1d8T: 1951 case ARM::VLD1d16T: 1952 case ARM::VLD1d32T: 1953 case ARM::VLD1d64T: 1954 case ARM::VLD1d8T_UPD: 1955 case ARM::VLD1d16T_UPD: 1956 case ARM::VLD1d32T_UPD: 1957 case ARM::VLD1d64T_UPD: 1958 case ARM::VLD1d8Q: 1959 case ARM::VLD1d16Q: 1960 case ARM::VLD1d32Q: 1961 case ARM::VLD1d64Q: 1962 case ARM::VLD1d8Q_UPD: 1963 case ARM::VLD1d16Q_UPD: 1964 case ARM::VLD1d32Q_UPD: 1965 case ARM::VLD1d64Q_UPD: 1966 case ARM::VLD2d8: 1967 case ARM::VLD2d16: 1968 case ARM::VLD2d32: 1969 case ARM::VLD2d8_UPD: 1970 case ARM::VLD2d16_UPD: 1971 case ARM::VLD2d32_UPD: 1972 case ARM::VLD2q8: 1973 case ARM::VLD2q16: 1974 case ARM::VLD2q32: 1975 case ARM::VLD2q8_UPD: 1976 case ARM::VLD2q16_UPD: 1977 case ARM::VLD2q32_UPD: 1978 case ARM::VLD3d8: 1979 case ARM::VLD3d16: 1980 case ARM::VLD3d32: 1981 case ARM::VLD3d8_UPD: 1982 case ARM::VLD3d16_UPD: 1983 case ARM::VLD3d32_UPD: 1984 case ARM::VLD4d8: 1985 case ARM::VLD4d16: 1986 case ARM::VLD4d32: 1987 case ARM::VLD4d8_UPD: 1988 case ARM::VLD4d16_UPD: 1989 case ARM::VLD4d32_UPD: 1990 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 1991 return MCDisassembler::Fail; 1992 break; 1993 case ARM::VLD2b8: 1994 case ARM::VLD2b16: 1995 case ARM::VLD2b32: 1996 case ARM::VLD2b8_UPD: 1997 case ARM::VLD2b16_UPD: 1998 case ARM::VLD2b32_UPD: 1999 case ARM::VLD3q8: 2000 case ARM::VLD3q16: 2001 case ARM::VLD3q32: 2002 case ARM::VLD3q8_UPD: 2003 case ARM::VLD3q16_UPD: 2004 case ARM::VLD3q32_UPD: 2005 case ARM::VLD4q8: 2006 case ARM::VLD4q16: 2007 case ARM::VLD4q32: 2008 case ARM::VLD4q8_UPD: 2009 case ARM::VLD4q16_UPD: 2010 case ARM::VLD4q32_UPD: 2011 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2012 return MCDisassembler::Fail; 2013 default: 2014 break; 2015 } 2016 2017 // Third output register 2018 switch(Inst.getOpcode()) { 2019 case ARM::VLD1d8T: 2020 case ARM::VLD1d16T: 2021 case ARM::VLD1d32T: 2022 case ARM::VLD1d64T: 2023 case ARM::VLD1d8T_UPD: 2024 case ARM::VLD1d16T_UPD: 2025 case ARM::VLD1d32T_UPD: 2026 case ARM::VLD1d64T_UPD: 2027 case ARM::VLD1d8Q: 2028 case ARM::VLD1d16Q: 2029 case ARM::VLD1d32Q: 2030 case ARM::VLD1d64Q: 2031 case ARM::VLD1d8Q_UPD: 2032 case ARM::VLD1d16Q_UPD: 2033 case ARM::VLD1d32Q_UPD: 2034 case ARM::VLD1d64Q_UPD: 2035 case ARM::VLD2q8: 2036 case ARM::VLD2q16: 2037 case ARM::VLD2q32: 2038 case ARM::VLD2q8_UPD: 2039 case ARM::VLD2q16_UPD: 2040 case ARM::VLD2q32_UPD: 2041 case ARM::VLD3d8: 2042 case ARM::VLD3d16: 2043 case ARM::VLD3d32: 2044 case ARM::VLD3d8_UPD: 2045 case ARM::VLD3d16_UPD: 2046 case ARM::VLD3d32_UPD: 2047 case ARM::VLD4d8: 2048 case ARM::VLD4d16: 2049 case ARM::VLD4d32: 2050 case ARM::VLD4d8_UPD: 2051 case ARM::VLD4d16_UPD: 2052 case ARM::VLD4d32_UPD: 2053 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2054 return MCDisassembler::Fail; 2055 break; 2056 case ARM::VLD3q8: 2057 case ARM::VLD3q16: 2058 case ARM::VLD3q32: 2059 case ARM::VLD3q8_UPD: 2060 case ARM::VLD3q16_UPD: 2061 case ARM::VLD3q32_UPD: 2062 case ARM::VLD4q8: 2063 case ARM::VLD4q16: 2064 case ARM::VLD4q32: 2065 case ARM::VLD4q8_UPD: 2066 case ARM::VLD4q16_UPD: 2067 case ARM::VLD4q32_UPD: 2068 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2069 return MCDisassembler::Fail; 2070 break; 2071 default: 2072 break; 2073 } 2074 2075 // Fourth output register 2076 switch (Inst.getOpcode()) { 2077 case ARM::VLD1d8Q: 2078 case ARM::VLD1d16Q: 2079 case ARM::VLD1d32Q: 2080 case ARM::VLD1d64Q: 2081 case ARM::VLD1d8Q_UPD: 2082 case ARM::VLD1d16Q_UPD: 2083 case ARM::VLD1d32Q_UPD: 2084 case ARM::VLD1d64Q_UPD: 2085 case ARM::VLD2q8: 2086 case ARM::VLD2q16: 2087 case ARM::VLD2q32: 2088 case ARM::VLD2q8_UPD: 2089 case ARM::VLD2q16_UPD: 2090 case ARM::VLD2q32_UPD: 2091 case ARM::VLD4d8: 2092 case ARM::VLD4d16: 2093 case ARM::VLD4d32: 2094 case ARM::VLD4d8_UPD: 2095 case ARM::VLD4d16_UPD: 2096 case ARM::VLD4d32_UPD: 2097 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2098 return MCDisassembler::Fail; 2099 break; 2100 case ARM::VLD4q8: 2101 case ARM::VLD4q16: 2102 case ARM::VLD4q32: 2103 case ARM::VLD4q8_UPD: 2104 case ARM::VLD4q16_UPD: 2105 case ARM::VLD4q32_UPD: 2106 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2107 return MCDisassembler::Fail; 2108 break; 2109 default: 2110 break; 2111 } 2112 2113 // Writeback operand 2114 switch (Inst.getOpcode()) { 2115 case ARM::VLD1d8_UPD: 2116 case ARM::VLD1d16_UPD: 2117 case ARM::VLD1d32_UPD: 2118 case ARM::VLD1d64_UPD: 2119 case ARM::VLD1q8_UPD: 2120 case ARM::VLD1q16_UPD: 2121 case ARM::VLD1q32_UPD: 2122 case ARM::VLD1q64_UPD: 2123 case ARM::VLD1d8T_UPD: 2124 case ARM::VLD1d16T_UPD: 2125 case ARM::VLD1d32T_UPD: 2126 case ARM::VLD1d64T_UPD: 2127 case ARM::VLD1d8Q_UPD: 2128 case ARM::VLD1d16Q_UPD: 2129 case ARM::VLD1d32Q_UPD: 2130 case ARM::VLD1d64Q_UPD: 2131 case ARM::VLD2d8_UPD: 2132 case ARM::VLD2d16_UPD: 2133 case ARM::VLD2d32_UPD: 2134 case ARM::VLD2q8_UPD: 2135 case ARM::VLD2q16_UPD: 2136 case ARM::VLD2q32_UPD: 2137 case ARM::VLD2b8_UPD: 2138 case ARM::VLD2b16_UPD: 2139 case ARM::VLD2b32_UPD: 2140 case ARM::VLD3d8_UPD: 2141 case ARM::VLD3d16_UPD: 2142 case ARM::VLD3d32_UPD: 2143 case ARM::VLD3q8_UPD: 2144 case ARM::VLD3q16_UPD: 2145 case ARM::VLD3q32_UPD: 2146 case ARM::VLD4d8_UPD: 2147 case ARM::VLD4d16_UPD: 2148 case ARM::VLD4d32_UPD: 2149 case ARM::VLD4q8_UPD: 2150 case ARM::VLD4q16_UPD: 2151 case ARM::VLD4q32_UPD: 2152 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2153 return MCDisassembler::Fail; 2154 break; 2155 default: 2156 break; 2157 } 2158 2159 // AddrMode6 Base (register+alignment) 2160 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2161 return MCDisassembler::Fail; 2162 2163 // AddrMode6 Offset (register) 2164 if (Rm == 0xD) 2165 Inst.addOperand(MCOperand::CreateReg(0)); 2166 else if (Rm != 0xF) { 2167 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2168 return MCDisassembler::Fail; 2169 } 2170 2171 return S; 2172 } 2173 2174 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 2175 uint64_t Address, const void *Decoder) { 2176 DecodeStatus S = MCDisassembler::Success; 2177 2178 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2179 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2180 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 2181 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2182 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 2183 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2184 2185 // Writeback Operand 2186 switch (Inst.getOpcode()) { 2187 case ARM::VST1d8_UPD: 2188 case ARM::VST1d16_UPD: 2189 case ARM::VST1d32_UPD: 2190 case ARM::VST1d64_UPD: 2191 case ARM::VST1q8_UPD: 2192 case ARM::VST1q16_UPD: 2193 case ARM::VST1q32_UPD: 2194 case ARM::VST1q64_UPD: 2195 case ARM::VST1d8T_UPD: 2196 case ARM::VST1d16T_UPD: 2197 case ARM::VST1d32T_UPD: 2198 case ARM::VST1d64T_UPD: 2199 case ARM::VST1d8Q_UPD: 2200 case ARM::VST1d16Q_UPD: 2201 case ARM::VST1d32Q_UPD: 2202 case ARM::VST1d64Q_UPD: 2203 case ARM::VST2d8_UPD: 2204 case ARM::VST2d16_UPD: 2205 case ARM::VST2d32_UPD: 2206 case ARM::VST2q8_UPD: 2207 case ARM::VST2q16_UPD: 2208 case ARM::VST2q32_UPD: 2209 case ARM::VST2b8_UPD: 2210 case ARM::VST2b16_UPD: 2211 case ARM::VST2b32_UPD: 2212 case ARM::VST3d8_UPD: 2213 case ARM::VST3d16_UPD: 2214 case ARM::VST3d32_UPD: 2215 case ARM::VST3q8_UPD: 2216 case ARM::VST3q16_UPD: 2217 case ARM::VST3q32_UPD: 2218 case ARM::VST4d8_UPD: 2219 case ARM::VST4d16_UPD: 2220 case ARM::VST4d32_UPD: 2221 case ARM::VST4q8_UPD: 2222 case ARM::VST4q16_UPD: 2223 case ARM::VST4q32_UPD: 2224 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2225 return MCDisassembler::Fail; 2226 break; 2227 default: 2228 break; 2229 } 2230 2231 // AddrMode6 Base (register+alignment) 2232 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2233 return MCDisassembler::Fail; 2234 2235 // AddrMode6 Offset (register) 2236 if (Rm == 0xD) 2237 Inst.addOperand(MCOperand::CreateReg(0)); 2238 else if (Rm != 0xF) { 2239 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2240 return MCDisassembler::Fail; 2241 } 2242 2243 // First input register 2244 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2245 return MCDisassembler::Fail; 2246 2247 // Second input register 2248 switch (Inst.getOpcode()) { 2249 case ARM::VST1q8: 2250 case ARM::VST1q16: 2251 case ARM::VST1q32: 2252 case ARM::VST1q64: 2253 case ARM::VST1q8_UPD: 2254 case ARM::VST1q16_UPD: 2255 case ARM::VST1q32_UPD: 2256 case ARM::VST1q64_UPD: 2257 case ARM::VST1d8T: 2258 case ARM::VST1d16T: 2259 case ARM::VST1d32T: 2260 case ARM::VST1d64T: 2261 case ARM::VST1d8T_UPD: 2262 case ARM::VST1d16T_UPD: 2263 case ARM::VST1d32T_UPD: 2264 case ARM::VST1d64T_UPD: 2265 case ARM::VST1d8Q: 2266 case ARM::VST1d16Q: 2267 case ARM::VST1d32Q: 2268 case ARM::VST1d64Q: 2269 case ARM::VST1d8Q_UPD: 2270 case ARM::VST1d16Q_UPD: 2271 case ARM::VST1d32Q_UPD: 2272 case ARM::VST1d64Q_UPD: 2273 case ARM::VST2d8: 2274 case ARM::VST2d16: 2275 case ARM::VST2d32: 2276 case ARM::VST2d8_UPD: 2277 case ARM::VST2d16_UPD: 2278 case ARM::VST2d32_UPD: 2279 case ARM::VST2q8: 2280 case ARM::VST2q16: 2281 case ARM::VST2q32: 2282 case ARM::VST2q8_UPD: 2283 case ARM::VST2q16_UPD: 2284 case ARM::VST2q32_UPD: 2285 case ARM::VST3d8: 2286 case ARM::VST3d16: 2287 case ARM::VST3d32: 2288 case ARM::VST3d8_UPD: 2289 case ARM::VST3d16_UPD: 2290 case ARM::VST3d32_UPD: 2291 case ARM::VST4d8: 2292 case ARM::VST4d16: 2293 case ARM::VST4d32: 2294 case ARM::VST4d8_UPD: 2295 case ARM::VST4d16_UPD: 2296 case ARM::VST4d32_UPD: 2297 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2298 return MCDisassembler::Fail; 2299 break; 2300 case ARM::VST2b8: 2301 case ARM::VST2b16: 2302 case ARM::VST2b32: 2303 case ARM::VST2b8_UPD: 2304 case ARM::VST2b16_UPD: 2305 case ARM::VST2b32_UPD: 2306 case ARM::VST3q8: 2307 case ARM::VST3q16: 2308 case ARM::VST3q32: 2309 case ARM::VST3q8_UPD: 2310 case ARM::VST3q16_UPD: 2311 case ARM::VST3q32_UPD: 2312 case ARM::VST4q8: 2313 case ARM::VST4q16: 2314 case ARM::VST4q32: 2315 case ARM::VST4q8_UPD: 2316 case ARM::VST4q16_UPD: 2317 case ARM::VST4q32_UPD: 2318 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2319 return MCDisassembler::Fail; 2320 break; 2321 default: 2322 break; 2323 } 2324 2325 // Third input register 2326 switch (Inst.getOpcode()) { 2327 case ARM::VST1d8T: 2328 case ARM::VST1d16T: 2329 case ARM::VST1d32T: 2330 case ARM::VST1d64T: 2331 case ARM::VST1d8T_UPD: 2332 case ARM::VST1d16T_UPD: 2333 case ARM::VST1d32T_UPD: 2334 case ARM::VST1d64T_UPD: 2335 case ARM::VST1d8Q: 2336 case ARM::VST1d16Q: 2337 case ARM::VST1d32Q: 2338 case ARM::VST1d64Q: 2339 case ARM::VST1d8Q_UPD: 2340 case ARM::VST1d16Q_UPD: 2341 case ARM::VST1d32Q_UPD: 2342 case ARM::VST1d64Q_UPD: 2343 case ARM::VST2q8: 2344 case ARM::VST2q16: 2345 case ARM::VST2q32: 2346 case ARM::VST2q8_UPD: 2347 case ARM::VST2q16_UPD: 2348 case ARM::VST2q32_UPD: 2349 case ARM::VST3d8: 2350 case ARM::VST3d16: 2351 case ARM::VST3d32: 2352 case ARM::VST3d8_UPD: 2353 case ARM::VST3d16_UPD: 2354 case ARM::VST3d32_UPD: 2355 case ARM::VST4d8: 2356 case ARM::VST4d16: 2357 case ARM::VST4d32: 2358 case ARM::VST4d8_UPD: 2359 case ARM::VST4d16_UPD: 2360 case ARM::VST4d32_UPD: 2361 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2362 return MCDisassembler::Fail; 2363 break; 2364 case ARM::VST3q8: 2365 case ARM::VST3q16: 2366 case ARM::VST3q32: 2367 case ARM::VST3q8_UPD: 2368 case ARM::VST3q16_UPD: 2369 case ARM::VST3q32_UPD: 2370 case ARM::VST4q8: 2371 case ARM::VST4q16: 2372 case ARM::VST4q32: 2373 case ARM::VST4q8_UPD: 2374 case ARM::VST4q16_UPD: 2375 case ARM::VST4q32_UPD: 2376 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2377 return MCDisassembler::Fail; 2378 break; 2379 default: 2380 break; 2381 } 2382 2383 // Fourth input register 2384 switch (Inst.getOpcode()) { 2385 case ARM::VST1d8Q: 2386 case ARM::VST1d16Q: 2387 case ARM::VST1d32Q: 2388 case ARM::VST1d64Q: 2389 case ARM::VST1d8Q_UPD: 2390 case ARM::VST1d16Q_UPD: 2391 case ARM::VST1d32Q_UPD: 2392 case ARM::VST1d64Q_UPD: 2393 case ARM::VST2q8: 2394 case ARM::VST2q16: 2395 case ARM::VST2q32: 2396 case ARM::VST2q8_UPD: 2397 case ARM::VST2q16_UPD: 2398 case ARM::VST2q32_UPD: 2399 case ARM::VST4d8: 2400 case ARM::VST4d16: 2401 case ARM::VST4d32: 2402 case ARM::VST4d8_UPD: 2403 case ARM::VST4d16_UPD: 2404 case ARM::VST4d32_UPD: 2405 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2406 return MCDisassembler::Fail; 2407 break; 2408 case ARM::VST4q8: 2409 case ARM::VST4q16: 2410 case ARM::VST4q32: 2411 case ARM::VST4q8_UPD: 2412 case ARM::VST4q16_UPD: 2413 case ARM::VST4q32_UPD: 2414 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2415 return MCDisassembler::Fail; 2416 break; 2417 default: 2418 break; 2419 } 2420 2421 return S; 2422 } 2423 2424 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2425 uint64_t Address, const void *Decoder) { 2426 DecodeStatus S = MCDisassembler::Success; 2427 2428 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2429 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2430 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2431 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2432 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2433 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2434 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 2435 2436 align *= (1 << size); 2437 2438 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2439 return MCDisassembler::Fail; 2440 if (regs == 2) { 2441 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2442 return MCDisassembler::Fail; 2443 } 2444 if (Rm != 0xF) { 2445 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2446 return MCDisassembler::Fail; 2447 } 2448 2449 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2450 return MCDisassembler::Fail; 2451 Inst.addOperand(MCOperand::CreateImm(align)); 2452 2453 if (Rm == 0xD) 2454 Inst.addOperand(MCOperand::CreateReg(0)); 2455 else if (Rm != 0xF) { 2456 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2457 return MCDisassembler::Fail; 2458 } 2459 2460 return S; 2461 } 2462 2463 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2464 uint64_t Address, const void *Decoder) { 2465 DecodeStatus S = MCDisassembler::Success; 2466 2467 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2468 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2469 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2470 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2471 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2472 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 2473 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2474 align *= 2*size; 2475 2476 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2477 return MCDisassembler::Fail; 2478 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2479 return MCDisassembler::Fail; 2480 if (Rm != 0xF) { 2481 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2482 return MCDisassembler::Fail; 2483 } 2484 2485 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2486 return MCDisassembler::Fail; 2487 Inst.addOperand(MCOperand::CreateImm(align)); 2488 2489 if (Rm == 0xD) 2490 Inst.addOperand(MCOperand::CreateReg(0)); 2491 else if (Rm != 0xF) { 2492 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2493 return MCDisassembler::Fail; 2494 } 2495 2496 return S; 2497 } 2498 2499 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2500 uint64_t Address, const void *Decoder) { 2501 DecodeStatus S = MCDisassembler::Success; 2502 2503 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2504 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2505 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2506 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2507 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2508 2509 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2510 return MCDisassembler::Fail; 2511 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2512 return MCDisassembler::Fail; 2513 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2514 return MCDisassembler::Fail; 2515 if (Rm != 0xF) { 2516 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2517 return MCDisassembler::Fail; 2518 } 2519 2520 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2521 return MCDisassembler::Fail; 2522 Inst.addOperand(MCOperand::CreateImm(0)); 2523 2524 if (Rm == 0xD) 2525 Inst.addOperand(MCOperand::CreateReg(0)); 2526 else if (Rm != 0xF) { 2527 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2528 return MCDisassembler::Fail; 2529 } 2530 2531 return S; 2532 } 2533 2534 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2535 uint64_t Address, const void *Decoder) { 2536 DecodeStatus S = MCDisassembler::Success; 2537 2538 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2539 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2540 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2541 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2542 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2543 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2544 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2545 2546 if (size == 0x3) { 2547 size = 4; 2548 align = 16; 2549 } else { 2550 if (size == 2) { 2551 size = 1 << size; 2552 align *= 8; 2553 } else { 2554 size = 1 << size; 2555 align *= 4*size; 2556 } 2557 } 2558 2559 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2560 return MCDisassembler::Fail; 2561 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2562 return MCDisassembler::Fail; 2563 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2564 return MCDisassembler::Fail; 2565 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2566 return MCDisassembler::Fail; 2567 if (Rm != 0xF) { 2568 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2569 return MCDisassembler::Fail; 2570 } 2571 2572 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2573 return MCDisassembler::Fail; 2574 Inst.addOperand(MCOperand::CreateImm(align)); 2575 2576 if (Rm == 0xD) 2577 Inst.addOperand(MCOperand::CreateReg(0)); 2578 else if (Rm != 0xF) { 2579 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2580 return MCDisassembler::Fail; 2581 } 2582 2583 return S; 2584 } 2585 2586 static DecodeStatus 2587 DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 2588 uint64_t Address, const void *Decoder) { 2589 DecodeStatus S = MCDisassembler::Success; 2590 2591 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2592 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2593 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2594 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2595 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2596 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2597 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2598 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2599 2600 if (Q) { 2601 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2602 return MCDisassembler::Fail; 2603 } else { 2604 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2605 return MCDisassembler::Fail; 2606 } 2607 2608 Inst.addOperand(MCOperand::CreateImm(imm)); 2609 2610 switch (Inst.getOpcode()) { 2611 case ARM::VORRiv4i16: 2612 case ARM::VORRiv2i32: 2613 case ARM::VBICiv4i16: 2614 case ARM::VBICiv2i32: 2615 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2616 return MCDisassembler::Fail; 2617 break; 2618 case ARM::VORRiv8i16: 2619 case ARM::VORRiv4i32: 2620 case ARM::VBICiv8i16: 2621 case ARM::VBICiv4i32: 2622 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2623 return MCDisassembler::Fail; 2624 break; 2625 default: 2626 break; 2627 } 2628 2629 return S; 2630 } 2631 2632 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2633 uint64_t Address, const void *Decoder) { 2634 DecodeStatus S = MCDisassembler::Success; 2635 2636 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2637 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2638 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2639 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2640 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2641 2642 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2643 return MCDisassembler::Fail; 2644 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2645 return MCDisassembler::Fail; 2646 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2647 2648 return S; 2649 } 2650 2651 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2652 uint64_t Address, const void *Decoder) { 2653 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2654 return MCDisassembler::Success; 2655 } 2656 2657 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2658 uint64_t Address, const void *Decoder) { 2659 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2660 return MCDisassembler::Success; 2661 } 2662 2663 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2664 uint64_t Address, const void *Decoder) { 2665 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2666 return MCDisassembler::Success; 2667 } 2668 2669 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2670 uint64_t Address, const void *Decoder) { 2671 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2672 return MCDisassembler::Success; 2673 } 2674 2675 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2676 uint64_t Address, const void *Decoder) { 2677 DecodeStatus S = MCDisassembler::Success; 2678 2679 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2680 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2681 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2682 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2683 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2684 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2685 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2686 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2687 2688 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2689 return MCDisassembler::Fail; 2690 if (op) { 2691 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2692 return MCDisassembler::Fail; // Writeback 2693 } 2694 2695 for (unsigned i = 0; i < length; ++i) { 2696 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder))) 2697 return MCDisassembler::Fail; 2698 } 2699 2700 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2701 return MCDisassembler::Fail; 2702 2703 return S; 2704 } 2705 2706 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2707 uint64_t Address, const void *Decoder) { 2708 DecodeStatus S = MCDisassembler::Success; 2709 2710 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2711 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2712 2713 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 2714 return MCDisassembler::Fail; 2715 2716 switch(Inst.getOpcode()) { 2717 default: 2718 return MCDisassembler::Fail; 2719 case ARM::tADR: 2720 break; // tADR does not explicitly represent the PC as an operand. 2721 case ARM::tADDrSPi: 2722 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2723 break; 2724 } 2725 2726 Inst.addOperand(MCOperand::CreateImm(imm)); 2727 return S; 2728 } 2729 2730 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2731 uint64_t Address, const void *Decoder) { 2732 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2733 return MCDisassembler::Success; 2734 } 2735 2736 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2737 uint64_t Address, const void *Decoder) { 2738 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2739 return MCDisassembler::Success; 2740 } 2741 2742 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2743 uint64_t Address, const void *Decoder) { 2744 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2745 return MCDisassembler::Success; 2746 } 2747 2748 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2749 uint64_t Address, const void *Decoder) { 2750 DecodeStatus S = MCDisassembler::Success; 2751 2752 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2753 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2754 2755 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2756 return MCDisassembler::Fail; 2757 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 2758 return MCDisassembler::Fail; 2759 2760 return S; 2761 } 2762 2763 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2764 uint64_t Address, const void *Decoder) { 2765 DecodeStatus S = MCDisassembler::Success; 2766 2767 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2768 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2769 2770 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2771 return MCDisassembler::Fail; 2772 Inst.addOperand(MCOperand::CreateImm(imm)); 2773 2774 return S; 2775 } 2776 2777 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2778 uint64_t Address, const void *Decoder) { 2779 unsigned imm = Val << 2; 2780 2781 Inst.addOperand(MCOperand::CreateImm(imm)); 2782 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 2783 2784 return MCDisassembler::Success; 2785 } 2786 2787 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2788 uint64_t Address, const void *Decoder) { 2789 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2790 Inst.addOperand(MCOperand::CreateImm(Val)); 2791 2792 return MCDisassembler::Success; 2793 } 2794 2795 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2796 uint64_t Address, const void *Decoder) { 2797 DecodeStatus S = MCDisassembler::Success; 2798 2799 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2800 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2801 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2802 2803 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2804 return MCDisassembler::Fail; 2805 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 2806 return MCDisassembler::Fail; 2807 Inst.addOperand(MCOperand::CreateImm(imm)); 2808 2809 return S; 2810 } 2811 2812 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2813 uint64_t Address, const void *Decoder) { 2814 DecodeStatus S = MCDisassembler::Success; 2815 2816 switch (Inst.getOpcode()) { 2817 case ARM::t2PLDs: 2818 case ARM::t2PLDWs: 2819 case ARM::t2PLIs: 2820 break; 2821 default: { 2822 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2823 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 2824 return MCDisassembler::Fail; 2825 } 2826 } 2827 2828 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2829 if (Rn == 0xF) { 2830 switch (Inst.getOpcode()) { 2831 case ARM::t2LDRBs: 2832 Inst.setOpcode(ARM::t2LDRBpci); 2833 break; 2834 case ARM::t2LDRHs: 2835 Inst.setOpcode(ARM::t2LDRHpci); 2836 break; 2837 case ARM::t2LDRSHs: 2838 Inst.setOpcode(ARM::t2LDRSHpci); 2839 break; 2840 case ARM::t2LDRSBs: 2841 Inst.setOpcode(ARM::t2LDRSBpci); 2842 break; 2843 case ARM::t2PLDs: 2844 Inst.setOpcode(ARM::t2PLDi12); 2845 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2846 break; 2847 default: 2848 return MCDisassembler::Fail; 2849 } 2850 2851 int imm = fieldFromInstruction32(Insn, 0, 12); 2852 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2853 Inst.addOperand(MCOperand::CreateImm(imm)); 2854 2855 return S; 2856 } 2857 2858 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2859 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2860 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2861 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 2862 return MCDisassembler::Fail; 2863 2864 return S; 2865 } 2866 2867 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2868 uint64_t Address, const void *Decoder) { 2869 int imm = Val & 0xFF; 2870 if (!(Val & 0x100)) imm *= -1; 2871 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2872 2873 return MCDisassembler::Success; 2874 } 2875 2876 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2877 uint64_t Address, const void *Decoder) { 2878 DecodeStatus S = MCDisassembler::Success; 2879 2880 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2881 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2882 2883 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2884 return MCDisassembler::Fail; 2885 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 2886 return MCDisassembler::Fail; 2887 2888 return S; 2889 } 2890 2891 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, 2892 uint64_t Address, const void *Decoder) { 2893 DecodeStatus S = MCDisassembler::Success; 2894 2895 unsigned Rn = fieldFromInstruction32(Val, 8, 4); 2896 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2897 2898 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2899 return MCDisassembler::Fail; 2900 2901 Inst.addOperand(MCOperand::CreateImm(imm)); 2902 2903 return S; 2904 } 2905 2906 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2907 uint64_t Address, const void *Decoder) { 2908 int imm = Val & 0xFF; 2909 if (Val == 0) 2910 imm = INT32_MIN; 2911 else if (!(Val & 0x100)) 2912 imm *= -1; 2913 Inst.addOperand(MCOperand::CreateImm(imm)); 2914 2915 return MCDisassembler::Success; 2916 } 2917 2918 2919 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2920 uint64_t Address, const void *Decoder) { 2921 DecodeStatus S = MCDisassembler::Success; 2922 2923 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2924 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2925 2926 // Some instructions always use an additive offset. 2927 switch (Inst.getOpcode()) { 2928 case ARM::t2LDRT: 2929 case ARM::t2LDRBT: 2930 case ARM::t2LDRHT: 2931 case ARM::t2LDRSBT: 2932 case ARM::t2LDRSHT: 2933 case ARM::t2STRT: 2934 case ARM::t2STRBT: 2935 case ARM::t2STRHT: 2936 imm |= 0x100; 2937 break; 2938 default: 2939 break; 2940 } 2941 2942 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2943 return MCDisassembler::Fail; 2944 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 2945 return MCDisassembler::Fail; 2946 2947 return S; 2948 } 2949 2950 static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn, 2951 uint64_t Address, const void *Decoder) { 2952 DecodeStatus S = MCDisassembler::Success; 2953 2954 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2955 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2956 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 2957 addr |= fieldFromInstruction32(Insn, 9, 1) << 8; 2958 addr |= Rn << 9; 2959 unsigned load = fieldFromInstruction32(Insn, 20, 1); 2960 2961 if (!load) { 2962 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2963 return MCDisassembler::Fail; 2964 } 2965 2966 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 2967 return MCDisassembler::Fail; 2968 2969 if (load) { 2970 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2971 return MCDisassembler::Fail; 2972 } 2973 2974 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 2975 return MCDisassembler::Fail; 2976 2977 return S; 2978 } 2979 2980 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2981 uint64_t Address, const void *Decoder) { 2982 DecodeStatus S = MCDisassembler::Success; 2983 2984 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2985 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2986 2987 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2988 return MCDisassembler::Fail; 2989 Inst.addOperand(MCOperand::CreateImm(imm)); 2990 2991 return S; 2992 } 2993 2994 2995 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2996 uint64_t Address, const void *Decoder) { 2997 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2998 2999 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3000 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3001 Inst.addOperand(MCOperand::CreateImm(imm)); 3002 3003 return MCDisassembler::Success; 3004 } 3005 3006 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 3007 uint64_t Address, const void *Decoder) { 3008 DecodeStatus S = MCDisassembler::Success; 3009 3010 if (Inst.getOpcode() == ARM::tADDrSP) { 3011 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 3012 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 3013 3014 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3015 return MCDisassembler::Fail; 3016 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3017 return MCDisassembler::Fail; 3018 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3019 } else if (Inst.getOpcode() == ARM::tADDspr) { 3020 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 3021 3022 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3023 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3024 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3025 return MCDisassembler::Fail; 3026 } 3027 3028 return S; 3029 } 3030 3031 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 3032 uint64_t Address, const void *Decoder) { 3033 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 3034 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 3035 3036 Inst.addOperand(MCOperand::CreateImm(imod)); 3037 Inst.addOperand(MCOperand::CreateImm(flags)); 3038 3039 return MCDisassembler::Success; 3040 } 3041 3042 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 3043 uint64_t Address, const void *Decoder) { 3044 DecodeStatus S = MCDisassembler::Success; 3045 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3046 unsigned add = fieldFromInstruction32(Insn, 4, 1); 3047 3048 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3049 return MCDisassembler::Fail; 3050 Inst.addOperand(MCOperand::CreateImm(add)); 3051 3052 return S; 3053 } 3054 3055 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 3056 uint64_t Address, const void *Decoder) { 3057 if (!tryAddingSymbolicOperand(Address, 3058 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4, 3059 true, 4, Inst, Decoder)) 3060 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3061 return MCDisassembler::Success; 3062 } 3063 3064 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 3065 uint64_t Address, const void *Decoder) { 3066 if (Val == 0xA || Val == 0xB) 3067 return MCDisassembler::Fail; 3068 3069 Inst.addOperand(MCOperand::CreateImm(Val)); 3070 return MCDisassembler::Success; 3071 } 3072 3073 static DecodeStatus 3074 DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn, 3075 uint64_t Address, const void *Decoder) { 3076 DecodeStatus S = MCDisassembler::Success; 3077 3078 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3079 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3080 3081 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3082 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3083 return MCDisassembler::Fail; 3084 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3085 return MCDisassembler::Fail; 3086 return S; 3087 } 3088 3089 static DecodeStatus 3090 DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 3091 uint64_t Address, const void *Decoder) { 3092 DecodeStatus S = MCDisassembler::Success; 3093 3094 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 3095 if (pred == 0xE || pred == 0xF) { 3096 unsigned opc = fieldFromInstruction32(Insn, 4, 28); 3097 switch (opc) { 3098 default: 3099 return MCDisassembler::Fail; 3100 case 0xf3bf8f4: 3101 Inst.setOpcode(ARM::t2DSB); 3102 break; 3103 case 0xf3bf8f5: 3104 Inst.setOpcode(ARM::t2DMB); 3105 break; 3106 case 0xf3bf8f6: 3107 Inst.setOpcode(ARM::t2ISB); 3108 break; 3109 } 3110 3111 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 3112 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3113 } 3114 3115 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 3116 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 3117 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 3118 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 3119 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 3120 3121 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3122 return MCDisassembler::Fail; 3123 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3124 return MCDisassembler::Fail; 3125 3126 return S; 3127 } 3128 3129 // Decode a shifted immediate operand. These basically consist 3130 // of an 8-bit value, and a 4-bit directive that specifies either 3131 // a splat operation or a rotation. 3132 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 3133 uint64_t Address, const void *Decoder) { 3134 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 3135 if (ctrl == 0) { 3136 unsigned byte = fieldFromInstruction32(Val, 8, 2); 3137 unsigned imm = fieldFromInstruction32(Val, 0, 8); 3138 switch (byte) { 3139 case 0: 3140 Inst.addOperand(MCOperand::CreateImm(imm)); 3141 break; 3142 case 1: 3143 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3144 break; 3145 case 2: 3146 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3147 break; 3148 case 3: 3149 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3150 (imm << 8) | imm)); 3151 break; 3152 } 3153 } else { 3154 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 3155 unsigned rot = fieldFromInstruction32(Val, 7, 5); 3156 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3157 Inst.addOperand(MCOperand::CreateImm(imm)); 3158 } 3159 3160 return MCDisassembler::Success; 3161 } 3162 3163 static DecodeStatus 3164 DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 3165 uint64_t Address, const void *Decoder){ 3166 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 3167 return MCDisassembler::Success; 3168 } 3169 3170 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 3171 uint64_t Address, const void *Decoder){ 3172 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3173 return MCDisassembler::Success; 3174 } 3175 3176 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 3177 uint64_t Address, const void *Decoder) { 3178 switch (Val) { 3179 default: 3180 return MCDisassembler::Fail; 3181 case 0xF: // SY 3182 case 0xE: // ST 3183 case 0xB: // ISH 3184 case 0xA: // ISHST 3185 case 0x7: // NSH 3186 case 0x6: // NSHST 3187 case 0x3: // OSH 3188 case 0x2: // OSHST 3189 break; 3190 } 3191 3192 Inst.addOperand(MCOperand::CreateImm(Val)); 3193 return MCDisassembler::Success; 3194 } 3195 3196 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 3197 uint64_t Address, const void *Decoder) { 3198 if (!Val) return MCDisassembler::Fail; 3199 Inst.addOperand(MCOperand::CreateImm(Val)); 3200 return MCDisassembler::Success; 3201 } 3202 3203 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 3204 uint64_t Address, const void *Decoder) { 3205 DecodeStatus S = MCDisassembler::Success; 3206 3207 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3208 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3209 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3210 3211 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3212 3213 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3214 return MCDisassembler::Fail; 3215 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3216 return MCDisassembler::Fail; 3217 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3218 return MCDisassembler::Fail; 3219 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3220 return MCDisassembler::Fail; 3221 3222 return S; 3223 } 3224 3225 3226 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 3227 uint64_t Address, const void *Decoder){ 3228 DecodeStatus S = MCDisassembler::Success; 3229 3230 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3231 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 3232 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3233 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3234 3235 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 3236 return MCDisassembler::Fail; 3237 3238 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3239 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 3240 3241 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3242 return MCDisassembler::Fail; 3243 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3244 return MCDisassembler::Fail; 3245 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3246 return MCDisassembler::Fail; 3247 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3248 return MCDisassembler::Fail; 3249 3250 return S; 3251 } 3252 3253 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 3254 uint64_t Address, const void *Decoder) { 3255 DecodeStatus S = MCDisassembler::Success; 3256 3257 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3258 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3259 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3260 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3261 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3262 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3263 3264 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3265 3266 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3267 return MCDisassembler::Fail; 3268 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3269 return MCDisassembler::Fail; 3270 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3271 return MCDisassembler::Fail; 3272 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3273 return MCDisassembler::Fail; 3274 3275 return S; 3276 } 3277 3278 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 3279 uint64_t Address, const void *Decoder) { 3280 DecodeStatus S = MCDisassembler::Success; 3281 3282 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3283 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3284 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3285 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3286 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3287 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3288 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3289 3290 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3291 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3292 3293 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3294 return MCDisassembler::Fail; 3295 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3296 return MCDisassembler::Fail; 3297 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3298 return MCDisassembler::Fail; 3299 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3300 return MCDisassembler::Fail; 3301 3302 return S; 3303 } 3304 3305 3306 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 3307 uint64_t Address, const void *Decoder) { 3308 DecodeStatus S = MCDisassembler::Success; 3309 3310 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3311 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3312 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3313 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3314 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3315 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3316 3317 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3318 3319 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3320 return MCDisassembler::Fail; 3321 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3322 return MCDisassembler::Fail; 3323 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3324 return MCDisassembler::Fail; 3325 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3326 return MCDisassembler::Fail; 3327 3328 return S; 3329 } 3330 3331 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 3332 uint64_t Address, const void *Decoder) { 3333 DecodeStatus S = MCDisassembler::Success; 3334 3335 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3336 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3337 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3338 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3339 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3340 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3341 3342 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3343 3344 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3345 return MCDisassembler::Fail; 3346 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3347 return MCDisassembler::Fail; 3348 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3349 return MCDisassembler::Fail; 3350 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3351 return MCDisassembler::Fail; 3352 3353 return S; 3354 } 3355 3356 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 3357 uint64_t Address, const void *Decoder) { 3358 DecodeStatus S = MCDisassembler::Success; 3359 3360 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3361 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3362 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3363 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3364 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3365 3366 unsigned align = 0; 3367 unsigned index = 0; 3368 switch (size) { 3369 default: 3370 return MCDisassembler::Fail; 3371 case 0: 3372 if (fieldFromInstruction32(Insn, 4, 1)) 3373 return MCDisassembler::Fail; // UNDEFINED 3374 index = fieldFromInstruction32(Insn, 5, 3); 3375 break; 3376 case 1: 3377 if (fieldFromInstruction32(Insn, 5, 1)) 3378 return MCDisassembler::Fail; // UNDEFINED 3379 index = fieldFromInstruction32(Insn, 6, 2); 3380 if (fieldFromInstruction32(Insn, 4, 1)) 3381 align = 2; 3382 break; 3383 case 2: 3384 if (fieldFromInstruction32(Insn, 6, 1)) 3385 return MCDisassembler::Fail; // UNDEFINED 3386 index = fieldFromInstruction32(Insn, 7, 1); 3387 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3388 align = 4; 3389 } 3390 3391 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3392 return MCDisassembler::Fail; 3393 if (Rm != 0xF) { // Writeback 3394 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3395 return MCDisassembler::Fail; 3396 } 3397 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3398 return MCDisassembler::Fail; 3399 Inst.addOperand(MCOperand::CreateImm(align)); 3400 if (Rm != 0xF) { 3401 if (Rm != 0xD) { 3402 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3403 return MCDisassembler::Fail; 3404 } else 3405 Inst.addOperand(MCOperand::CreateReg(0)); 3406 } 3407 3408 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3409 return MCDisassembler::Fail; 3410 Inst.addOperand(MCOperand::CreateImm(index)); 3411 3412 return S; 3413 } 3414 3415 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 3416 uint64_t Address, const void *Decoder) { 3417 DecodeStatus S = MCDisassembler::Success; 3418 3419 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3420 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3421 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3422 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3423 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3424 3425 unsigned align = 0; 3426 unsigned index = 0; 3427 switch (size) { 3428 default: 3429 return MCDisassembler::Fail; 3430 case 0: 3431 if (fieldFromInstruction32(Insn, 4, 1)) 3432 return MCDisassembler::Fail; // UNDEFINED 3433 index = fieldFromInstruction32(Insn, 5, 3); 3434 break; 3435 case 1: 3436 if (fieldFromInstruction32(Insn, 5, 1)) 3437 return MCDisassembler::Fail; // UNDEFINED 3438 index = fieldFromInstruction32(Insn, 6, 2); 3439 if (fieldFromInstruction32(Insn, 4, 1)) 3440 align = 2; 3441 break; 3442 case 2: 3443 if (fieldFromInstruction32(Insn, 6, 1)) 3444 return MCDisassembler::Fail; // UNDEFINED 3445 index = fieldFromInstruction32(Insn, 7, 1); 3446 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3447 align = 4; 3448 } 3449 3450 if (Rm != 0xF) { // Writeback 3451 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3452 return MCDisassembler::Fail; 3453 } 3454 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3455 return MCDisassembler::Fail; 3456 Inst.addOperand(MCOperand::CreateImm(align)); 3457 if (Rm != 0xF) { 3458 if (Rm != 0xD) { 3459 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3460 return MCDisassembler::Fail; 3461 } else 3462 Inst.addOperand(MCOperand::CreateReg(0)); 3463 } 3464 3465 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3466 return MCDisassembler::Fail; 3467 Inst.addOperand(MCOperand::CreateImm(index)); 3468 3469 return S; 3470 } 3471 3472 3473 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 3474 uint64_t Address, const void *Decoder) { 3475 DecodeStatus S = MCDisassembler::Success; 3476 3477 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3478 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3479 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3480 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3481 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3482 3483 unsigned align = 0; 3484 unsigned index = 0; 3485 unsigned inc = 1; 3486 switch (size) { 3487 default: 3488 return MCDisassembler::Fail; 3489 case 0: 3490 index = fieldFromInstruction32(Insn, 5, 3); 3491 if (fieldFromInstruction32(Insn, 4, 1)) 3492 align = 2; 3493 break; 3494 case 1: 3495 index = fieldFromInstruction32(Insn, 6, 2); 3496 if (fieldFromInstruction32(Insn, 4, 1)) 3497 align = 4; 3498 if (fieldFromInstruction32(Insn, 5, 1)) 3499 inc = 2; 3500 break; 3501 case 2: 3502 if (fieldFromInstruction32(Insn, 5, 1)) 3503 return MCDisassembler::Fail; // UNDEFINED 3504 index = fieldFromInstruction32(Insn, 7, 1); 3505 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3506 align = 8; 3507 if (fieldFromInstruction32(Insn, 6, 1)) 3508 inc = 2; 3509 break; 3510 } 3511 3512 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3513 return MCDisassembler::Fail; 3514 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3515 return MCDisassembler::Fail; 3516 if (Rm != 0xF) { // Writeback 3517 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3518 return MCDisassembler::Fail; 3519 } 3520 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3521 return MCDisassembler::Fail; 3522 Inst.addOperand(MCOperand::CreateImm(align)); 3523 if (Rm != 0xF) { 3524 if (Rm != 0xD) { 3525 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3526 return MCDisassembler::Fail; 3527 } else 3528 Inst.addOperand(MCOperand::CreateReg(0)); 3529 } 3530 3531 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3532 return MCDisassembler::Fail; 3533 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3534 return MCDisassembler::Fail; 3535 Inst.addOperand(MCOperand::CreateImm(index)); 3536 3537 return S; 3538 } 3539 3540 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 3541 uint64_t Address, const void *Decoder) { 3542 DecodeStatus S = MCDisassembler::Success; 3543 3544 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3545 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3546 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3547 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3548 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3549 3550 unsigned align = 0; 3551 unsigned index = 0; 3552 unsigned inc = 1; 3553 switch (size) { 3554 default: 3555 return MCDisassembler::Fail; 3556 case 0: 3557 index = fieldFromInstruction32(Insn, 5, 3); 3558 if (fieldFromInstruction32(Insn, 4, 1)) 3559 align = 2; 3560 break; 3561 case 1: 3562 index = fieldFromInstruction32(Insn, 6, 2); 3563 if (fieldFromInstruction32(Insn, 4, 1)) 3564 align = 4; 3565 if (fieldFromInstruction32(Insn, 5, 1)) 3566 inc = 2; 3567 break; 3568 case 2: 3569 if (fieldFromInstruction32(Insn, 5, 1)) 3570 return MCDisassembler::Fail; // UNDEFINED 3571 index = fieldFromInstruction32(Insn, 7, 1); 3572 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3573 align = 8; 3574 if (fieldFromInstruction32(Insn, 6, 1)) 3575 inc = 2; 3576 break; 3577 } 3578 3579 if (Rm != 0xF) { // Writeback 3580 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3581 return MCDisassembler::Fail; 3582 } 3583 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3584 return MCDisassembler::Fail; 3585 Inst.addOperand(MCOperand::CreateImm(align)); 3586 if (Rm != 0xF) { 3587 if (Rm != 0xD) { 3588 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3589 return MCDisassembler::Fail; 3590 } else 3591 Inst.addOperand(MCOperand::CreateReg(0)); 3592 } 3593 3594 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3595 return MCDisassembler::Fail; 3596 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3597 return MCDisassembler::Fail; 3598 Inst.addOperand(MCOperand::CreateImm(index)); 3599 3600 return S; 3601 } 3602 3603 3604 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 3605 uint64_t Address, const void *Decoder) { 3606 DecodeStatus S = MCDisassembler::Success; 3607 3608 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3609 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3610 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3611 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3612 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3613 3614 unsigned align = 0; 3615 unsigned index = 0; 3616 unsigned inc = 1; 3617 switch (size) { 3618 default: 3619 return MCDisassembler::Fail; 3620 case 0: 3621 if (fieldFromInstruction32(Insn, 4, 1)) 3622 return MCDisassembler::Fail; // UNDEFINED 3623 index = fieldFromInstruction32(Insn, 5, 3); 3624 break; 3625 case 1: 3626 if (fieldFromInstruction32(Insn, 4, 1)) 3627 return MCDisassembler::Fail; // UNDEFINED 3628 index = fieldFromInstruction32(Insn, 6, 2); 3629 if (fieldFromInstruction32(Insn, 5, 1)) 3630 inc = 2; 3631 break; 3632 case 2: 3633 if (fieldFromInstruction32(Insn, 4, 2)) 3634 return MCDisassembler::Fail; // UNDEFINED 3635 index = fieldFromInstruction32(Insn, 7, 1); 3636 if (fieldFromInstruction32(Insn, 6, 1)) 3637 inc = 2; 3638 break; 3639 } 3640 3641 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3642 return MCDisassembler::Fail; 3643 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3644 return MCDisassembler::Fail; 3645 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3646 return MCDisassembler::Fail; 3647 3648 if (Rm != 0xF) { // Writeback 3649 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3650 return MCDisassembler::Fail; 3651 } 3652 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3653 return MCDisassembler::Fail; 3654 Inst.addOperand(MCOperand::CreateImm(align)); 3655 if (Rm != 0xF) { 3656 if (Rm != 0xD) { 3657 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3658 return MCDisassembler::Fail; 3659 } else 3660 Inst.addOperand(MCOperand::CreateReg(0)); 3661 } 3662 3663 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3664 return MCDisassembler::Fail; 3665 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3666 return MCDisassembler::Fail; 3667 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3668 return MCDisassembler::Fail; 3669 Inst.addOperand(MCOperand::CreateImm(index)); 3670 3671 return S; 3672 } 3673 3674 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 3675 uint64_t Address, const void *Decoder) { 3676 DecodeStatus S = MCDisassembler::Success; 3677 3678 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3679 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3680 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3681 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3682 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3683 3684 unsigned align = 0; 3685 unsigned index = 0; 3686 unsigned inc = 1; 3687 switch (size) { 3688 default: 3689 return MCDisassembler::Fail; 3690 case 0: 3691 if (fieldFromInstruction32(Insn, 4, 1)) 3692 return MCDisassembler::Fail; // UNDEFINED 3693 index = fieldFromInstruction32(Insn, 5, 3); 3694 break; 3695 case 1: 3696 if (fieldFromInstruction32(Insn, 4, 1)) 3697 return MCDisassembler::Fail; // UNDEFINED 3698 index = fieldFromInstruction32(Insn, 6, 2); 3699 if (fieldFromInstruction32(Insn, 5, 1)) 3700 inc = 2; 3701 break; 3702 case 2: 3703 if (fieldFromInstruction32(Insn, 4, 2)) 3704 return MCDisassembler::Fail; // UNDEFINED 3705 index = fieldFromInstruction32(Insn, 7, 1); 3706 if (fieldFromInstruction32(Insn, 6, 1)) 3707 inc = 2; 3708 break; 3709 } 3710 3711 if (Rm != 0xF) { // Writeback 3712 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3713 return MCDisassembler::Fail; 3714 } 3715 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3716 return MCDisassembler::Fail; 3717 Inst.addOperand(MCOperand::CreateImm(align)); 3718 if (Rm != 0xF) { 3719 if (Rm != 0xD) { 3720 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3721 return MCDisassembler::Fail; 3722 } else 3723 Inst.addOperand(MCOperand::CreateReg(0)); 3724 } 3725 3726 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3727 return MCDisassembler::Fail; 3728 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3729 return MCDisassembler::Fail; 3730 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3731 return MCDisassembler::Fail; 3732 Inst.addOperand(MCOperand::CreateImm(index)); 3733 3734 return S; 3735 } 3736 3737 3738 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 3739 uint64_t Address, const void *Decoder) { 3740 DecodeStatus S = MCDisassembler::Success; 3741 3742 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3743 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3744 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3745 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3746 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3747 3748 unsigned align = 0; 3749 unsigned index = 0; 3750 unsigned inc = 1; 3751 switch (size) { 3752 default: 3753 return MCDisassembler::Fail; 3754 case 0: 3755 if (fieldFromInstruction32(Insn, 4, 1)) 3756 align = 4; 3757 index = fieldFromInstruction32(Insn, 5, 3); 3758 break; 3759 case 1: 3760 if (fieldFromInstruction32(Insn, 4, 1)) 3761 align = 8; 3762 index = fieldFromInstruction32(Insn, 6, 2); 3763 if (fieldFromInstruction32(Insn, 5, 1)) 3764 inc = 2; 3765 break; 3766 case 2: 3767 if (fieldFromInstruction32(Insn, 4, 2)) 3768 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3769 index = fieldFromInstruction32(Insn, 7, 1); 3770 if (fieldFromInstruction32(Insn, 6, 1)) 3771 inc = 2; 3772 break; 3773 } 3774 3775 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3776 return MCDisassembler::Fail; 3777 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3778 return MCDisassembler::Fail; 3779 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3780 return MCDisassembler::Fail; 3781 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3782 return MCDisassembler::Fail; 3783 3784 if (Rm != 0xF) { // Writeback 3785 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3786 return MCDisassembler::Fail; 3787 } 3788 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3789 return MCDisassembler::Fail; 3790 Inst.addOperand(MCOperand::CreateImm(align)); 3791 if (Rm != 0xF) { 3792 if (Rm != 0xD) { 3793 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3794 return MCDisassembler::Fail; 3795 } else 3796 Inst.addOperand(MCOperand::CreateReg(0)); 3797 } 3798 3799 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3800 return MCDisassembler::Fail; 3801 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3802 return MCDisassembler::Fail; 3803 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3804 return MCDisassembler::Fail; 3805 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3806 return MCDisassembler::Fail; 3807 Inst.addOperand(MCOperand::CreateImm(index)); 3808 3809 return S; 3810 } 3811 3812 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 3813 uint64_t Address, const void *Decoder) { 3814 DecodeStatus S = MCDisassembler::Success; 3815 3816 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3817 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3818 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3819 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3820 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3821 3822 unsigned align = 0; 3823 unsigned index = 0; 3824 unsigned inc = 1; 3825 switch (size) { 3826 default: 3827 return MCDisassembler::Fail; 3828 case 0: 3829 if (fieldFromInstruction32(Insn, 4, 1)) 3830 align = 4; 3831 index = fieldFromInstruction32(Insn, 5, 3); 3832 break; 3833 case 1: 3834 if (fieldFromInstruction32(Insn, 4, 1)) 3835 align = 8; 3836 index = fieldFromInstruction32(Insn, 6, 2); 3837 if (fieldFromInstruction32(Insn, 5, 1)) 3838 inc = 2; 3839 break; 3840 case 2: 3841 if (fieldFromInstruction32(Insn, 4, 2)) 3842 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3843 index = fieldFromInstruction32(Insn, 7, 1); 3844 if (fieldFromInstruction32(Insn, 6, 1)) 3845 inc = 2; 3846 break; 3847 } 3848 3849 if (Rm != 0xF) { // Writeback 3850 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3851 return MCDisassembler::Fail; 3852 } 3853 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3854 return MCDisassembler::Fail; 3855 Inst.addOperand(MCOperand::CreateImm(align)); 3856 if (Rm != 0xF) { 3857 if (Rm != 0xD) { 3858 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3859 return MCDisassembler::Fail; 3860 } else 3861 Inst.addOperand(MCOperand::CreateReg(0)); 3862 } 3863 3864 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3865 return MCDisassembler::Fail; 3866 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3867 return MCDisassembler::Fail; 3868 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3869 return MCDisassembler::Fail; 3870 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3871 return MCDisassembler::Fail; 3872 Inst.addOperand(MCOperand::CreateImm(index)); 3873 3874 return S; 3875 } 3876 3877 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 3878 uint64_t Address, const void *Decoder) { 3879 DecodeStatus S = MCDisassembler::Success; 3880 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3881 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3882 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3883 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3884 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3885 3886 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3887 S = MCDisassembler::SoftFail; 3888 3889 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3890 return MCDisassembler::Fail; 3891 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3892 return MCDisassembler::Fail; 3893 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3894 return MCDisassembler::Fail; 3895 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3896 return MCDisassembler::Fail; 3897 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3898 return MCDisassembler::Fail; 3899 3900 return S; 3901 } 3902 3903 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 3904 uint64_t Address, const void *Decoder) { 3905 DecodeStatus S = MCDisassembler::Success; 3906 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3907 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3908 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3909 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3910 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3911 3912 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3913 S = MCDisassembler::SoftFail; 3914 3915 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3916 return MCDisassembler::Fail; 3917 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3918 return MCDisassembler::Fail; 3919 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3920 return MCDisassembler::Fail; 3921 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3922 return MCDisassembler::Fail; 3923 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3924 return MCDisassembler::Fail; 3925 3926 return S; 3927 } 3928 3929 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn, 3930 uint64_t Address, const void *Decoder) { 3931 DecodeStatus S = MCDisassembler::Success; 3932 unsigned pred = fieldFromInstruction16(Insn, 4, 4); 3933 // The InstPrinter needs to have the low bit of the predicate in 3934 // the mask operand to be able to print it properly. 3935 unsigned mask = fieldFromInstruction16(Insn, 0, 5); 3936 3937 if (pred == 0xF) { 3938 pred = 0xE; 3939 S = MCDisassembler::SoftFail; 3940 } 3941 3942 if ((mask & 0xF) == 0) { 3943 // Preserve the high bit of the mask, which is the low bit of 3944 // the predicate. 3945 mask &= 0x10; 3946 mask |= 0x8; 3947 S = MCDisassembler::SoftFail; 3948 } 3949 3950 Inst.addOperand(MCOperand::CreateImm(pred)); 3951 Inst.addOperand(MCOperand::CreateImm(mask)); 3952 return S; 3953 } 3954 3955 static DecodeStatus 3956 DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 3957 uint64_t Address, const void *Decoder) { 3958 DecodeStatus S = MCDisassembler::Success; 3959 3960 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3961 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 3962 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3963 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3964 unsigned W = fieldFromInstruction32(Insn, 21, 1); 3965 unsigned U = fieldFromInstruction32(Insn, 23, 1); 3966 unsigned P = fieldFromInstruction32(Insn, 24, 1); 3967 bool writeback = (W == 1) | (P == 0); 3968 3969 addr |= (U << 8) | (Rn << 9); 3970 3971 if (writeback && (Rn == Rt || Rn == Rt2)) 3972 Check(S, MCDisassembler::SoftFail); 3973 if (Rt == Rt2) 3974 Check(S, MCDisassembler::SoftFail); 3975 3976 // Rt 3977 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3978 return MCDisassembler::Fail; 3979 // Rt2 3980 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 3981 return MCDisassembler::Fail; 3982 // Writeback operand 3983 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 3984 return MCDisassembler::Fail; 3985 // addr 3986 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 3987 return MCDisassembler::Fail; 3988 3989 return S; 3990 } 3991 3992 static DecodeStatus 3993 DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 3994 uint64_t Address, const void *Decoder) { 3995 DecodeStatus S = MCDisassembler::Success; 3996 3997 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3998 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 3999 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4000 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 4001 unsigned W = fieldFromInstruction32(Insn, 21, 1); 4002 unsigned U = fieldFromInstruction32(Insn, 23, 1); 4003 unsigned P = fieldFromInstruction32(Insn, 24, 1); 4004 bool writeback = (W == 1) | (P == 0); 4005 4006 addr |= (U << 8) | (Rn << 9); 4007 4008 if (writeback && (Rn == Rt || Rn == Rt2)) 4009 Check(S, MCDisassembler::SoftFail); 4010 4011 // Writeback operand 4012 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4013 return MCDisassembler::Fail; 4014 // Rt 4015 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4016 return MCDisassembler::Fail; 4017 // Rt2 4018 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4019 return MCDisassembler::Fail; 4020 // addr 4021 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4022 return MCDisassembler::Fail; 4023 4024 return S; 4025 } 4026 4027 static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn, 4028 uint64_t Address, const void *Decoder) { 4029 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1); 4030 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1); 4031 if (sign1 != sign2) return MCDisassembler::Fail; 4032 4033 unsigned Val = fieldFromInstruction32(Insn, 0, 8); 4034 Val |= fieldFromInstruction32(Insn, 12, 3) << 8; 4035 Val |= fieldFromInstruction32(Insn, 26, 1) << 11; 4036 Val |= sign1 << 12; 4037 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4038 4039 return MCDisassembler::Success; 4040 } 4041 4042 static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, uint32_t Val, 4043 uint64_t Address, 4044 const void *Decoder) { 4045 DecodeStatus S = MCDisassembler::Success; 4046 4047 // Shift of "asr #32" is not allowed in Thumb2 mode. 4048 if (Val == 0x20) S = MCDisassembler::SoftFail; 4049 Inst.addOperand(MCOperand::CreateImm(Val)); 4050 return S; 4051 } 4052 4053