MachineScheduler: enable biasCriticalPath for all DAGs.

llvm-svn: 173318

Follow-up typo correction from building the wrong branch.

llvm-svn: 172224

Fix typo from r170452. Affects -enable-misched heuristics.

llvm-svn: 172223

MIsched: add an ILP window property to machine model.

This was an experimental option, but needs to be defined
per-target. e.g. PPC A2 needs to aggressively hide latency.

I converted some in-order

MIsched: add an ILP window property to machine model.

This was an experimental option, but needs to be defined
per-target. e.g. PPC A2 needs to aggressively hide latency.

I converted some in-order scheduling tests to A2. Hal is working on
more test cases.

llvm-svn: 171946

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MISched: Cleanup, redundant statement.

llvm-svn: 170453

MISched: Heuristics, compare latency more precisely. It matters more for some targets.

llvm-svn: 170452

MISched: Remove SchedRemainder::IsResourceLimited. I don't know how to compute it.

llvm-svn: 170451

MISched: cleanup, use the proper iterator type.

llvm-svn: 170450

MISched: minor improvement, initialize remaining resources before the first scheduling decision.

llvm-svn: 170449

Use the new script to sort the includes of every file under lib.

Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module

Use the new script to sort the includes of every file under lib.

Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

llvm-svn: 169131

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misched: Fix RegisterPressureTracker handling of DebugVals.

Assertion failed: (TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker").
rdar://12790302.

llvm-svn: 169072

misched: fix RegionBegin when DebugValues get shuffled to the top.

assert (RemainingInstrs == 0 && "Instruction count mismatch!")

rdar://12776937.

llvm-svn: 169069

misched: Recompute priority queue when DFSResults are updated.

This was found by MSVC10's STL debug mode on a test from the test suite. Sadly
std::is_heap isn't standard so there is no way to assert

misched: Recompute priority queue when DFSResults are updated.

This was found by MSVC10's STL debug mode on a test from the test suite. Sadly
std::is_heap isn't standard so there is no way to assert this without writing
our own heap verify, which looks like overkill to me.

llvm-svn: 168885

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misched: Analysis that partitions the DAG into subtrees.

This is a simple, cheap infrastructure for analyzing the shape of a
DAG. It recognizes uniform DAGs that take the shape of bottom-up
subtrees

misched: Analysis that partitions the DAG into subtrees.

This is a simple, cheap infrastructure for analyzing the shape of a
DAG. It recognizes uniform DAGs that take the shape of bottom-up
subtrees, such as the included matrix multiplication example. This is
useful for heuristics that balance register pressure with ILP. Two
canonical expressions of the heuristic are implemented in scheduling
modes: -misched-ilpmin and -misched-ilpmax.

llvm-svn: 168773

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misched: rename ScheduleDAGILP to ScheduleDFS to prepare for other heuristics.

llvm-svn: 168772

misched: Debug output fix. Use an always valid iterator.

llvm-svn: 168767

misched: Allow subtargets to enable misched and dependent options.

This allows me to begin enabling (or backing out) misched by default
for one subtarget at a time. To run misched we typically want

misched: Allow subtargets to enable misched and dependent options.

This allows me to begin enabling (or backing out) misched by default
for one subtarget at a time. To run misched we typically want to:
- Disable SelectionDAG scheduling (use the source order scheduler)
- Enable more aggressive coalescing (until we decide to always run the coalescer this way)
- Enable MachineScheduler pass itself.

Disabling PostRA sched may follow for some subtargets.

llvm-svn: 167826

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misched: rename interfaceto avoid gcc warnings

llvm-svn: 167753

misched: Target-independent support for MacroFusion.

Uses the infrastructure from r167742 to support clustering instructure
that the target processor can "fuse". e.g. cmp+jmp.

Next step: target hoo

misched: Target-independent support for MacroFusion.

Uses the infrastructure from r167742 to support clustering instructure
that the target processor can "fuse". e.g. cmp+jmp.

Next step: target hook implementations with test cases, and enable.

llvm-svn: 167744

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misched: Target-independent support for load/store clustering.

This infrastructure is generally useful for any target that wants to
strongly prefer two instructions to be adjacent after scheduling.

misched: Target-independent support for load/store clustering.

This infrastructure is generally useful for any target that wants to
strongly prefer two instructions to be adjacent after scheduling.

A following checkin will add target-specific hooks with unit
tests. Then this feature will be enabled by default with misched.

llvm-svn: 167742

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misched: Infrastructure for weak DAG edges.

This adds support for weak DAG edges to the general scheduling
infrastructure in preparation for MachineScheduler support for
heuristics based on weak edg

misched: Infrastructure for weak DAG edges.

This adds support for weak DAG edges to the general scheduling
infrastructure in preparation for MachineScheduler support for
heuristics based on weak edges.

llvm-svn: 167738

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Silence GCC warning about falling off the end of a non-void function.

llvm-svn: 167618

misched: Heuristics based on the machine model.

misched is disabled by default. With -enable-misched, these heuristics
balance the schedule to simultaneously avoid saturating processor
resources, ex

misched: Heuristics based on the machine model.

misched is disabled by default. With -enable-misched, these heuristics
balance the schedule to simultaneously avoid saturating processor
resources, expose ILP, and minimize register pressure. I've been
analyzing the performance of these heuristics on everything in the
llvm test suite in addition to a few other benchmarks. I would like
each heuristic check to be verified by a unit test, but I'm still
trying to figure out the best way to do that. The heuristics are still
in considerable flux, but as they are refined we should be rigorous
about unit testing the improvements.

llvm-svn: 167527

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misched: Rename RemainingCount to avoid confusion with remaining resources.

llvm-svn: 167443

misched: Added handleMove support for updating all kill flags, not just for allocatable regs.

This is a medium term workaround until we have a more robust solution
in the form of a register liveness

misched: Added handleMove support for updating all kill flags, not just for allocatable regs.

This is a medium term workaround until we have a more robust solution
in the form of a register liveness utility for postRA passes.

llvm-svn: 166001

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