MI-Sched: Rename IssueCount to CurrMOps.

"Counts" refer to scaled resource counts within a region. CurrMOps is
simply the number of micro-ops to be issue in the current cycle.

llvm-svn: 184031

MI-Sched: Remove the temporary EnableCopyConstrain flag.

llvm-svn: 184030

MI-Sched: added tracking of dependent latency for better heuristics.

Heuristics compare the critical path in the scheduled code, called
ExpectedLatency, with the latency of instructions remaining to

MI-Sched: added tracking of dependent latency for better heuristics.

Heuristics compare the critical path in the scheduled code, called
ExpectedLatency, with the latency of instructions remaining to be
scheduled. There are two ways to look at remaining latency:

(1) Dependent latency includes the latency between unscheduled and
scheduled instructions.

(2) Independent latency is simply the height (bottom-up) or depth
(top-down) of instructions currently in the ready Q.

llvm-svn: 184029

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MI-Sched: DEBUG: print critical resource.

llvm-svn: 184028

Move #include from .h to .cpp file.

llvm-svn: 183960

MI Sched: revert a minor heuristic that snuck in with -misched-vcopy.

I'll fix the heuristic in a general way in a follow-up commit.

llvm-svn: 180815

Fix for r180193 - MI Sched: eliminate local vreg.

Fixes PR15838. Need to check for blocks with nothing but dbg.value.

I'm not sure how to force this situation with a unit test. I tried to
reduce th

Fix for r180193 - MI Sched: eliminate local vreg.

Fixes PR15838. Need to check for blocks with nothing but dbg.value.

I'm not sure how to force this situation with a unit test. I tried to
reduce the test case in PR15838 (1k lines of metadata) but gave up.

llvm-svn: 180227

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MI Sched: eliminate local vreg copies.

For now, we just reschedule instructions that use the copied vregs and
let regalloc elliminate it. I would really like to eliminate the
copies on-the-fly durin

MI Sched: eliminate local vreg copies.

For now, we just reschedule instructions that use the copied vregs and
let regalloc elliminate it. I would really like to eliminate the
copies on-the-fly during scheduling, but we need a complete
implementation of repairIntervalsInRange() first.

The general strategy is for the register coalescer to eliminate as
many global copies as possible and shrink live ranges to be
extended-basic-block local. The coalescer should not have to worry
about resolving local copies (e.g. it shouldn't attemp to reorder
instructions). The scheduler is a much better place to deal with local
interference. The coalescer side of this equation needs work.

llvm-svn: 180193

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MI Sched: regpressure tracing.

llvm-svn: 180191

MI-Sched: DEBUG formatting.

llvm-svn: 179452

MI-Sched: schedule physreg copies.

The register allocator expects minimal physreg live ranges. Schedule
physreg copies accordingly. This is slightly tricky when they occur in
the middle of the sched

MI-Sched: schedule physreg copies.

The register allocator expects minimal physreg live ranges. Schedule
physreg copies accordingly. This is slightly tricky when they occur in
the middle of the scheduling region. For now, this is handled by
rescheduling the copy when its associated instruction is
scheduled. Eventually we may instead bundle them, but only if we can
preserve the bundles as parallel copies during regalloc.

llvm-svn: 179449

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RegisterPressure heuristics currently require signed comparisons.

llvm-svn: 178823

Disable DFSResult for ConvergingScheduler.

For now, just save the compile time since the ConvergingScheduler
heuristics don't use this analysis. We'll probably enable it later
after compile-time inv

Disable DFSResult for ConvergingScheduler.

For now, just save the compile time since the ConvergingScheduler
heuristics don't use this analysis. We'll probably enable it later
after compile-time investigation.

llvm-svn: 178822

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MachineScheduler: format DEBUG output.

I'm getting more serious about tuning and enabling on x86/ARM. Start
by making the trace readable.

llvm-svn: 178821

Fix missing std::. Not sure how this compiles for anyone else.

llvm-svn: 177620

Cleanup #includes.

llvm-svn: 176787

Add -verify-misched option.

This verifies live intervals both before and after scheduling. It's
useful for anyone hacking on live interval update.

Note that we don't yet pass verification all the t

Add -verify-misched option.

This verifies live intervals both before and after scheduling. It's
useful for anyone hacking on live interval update.

Note that we don't yet pass verification all the time. We don't yet
handle updating nonallocatable live intervals perfectly.

llvm-svn: 176685

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Use const reference instead of vector object when passing an argument to
updateScheduledPressure method.

llvm-svn: 175362

MIsched: HazardRecognizers are created for each DAG. Free them.

llvm-svn: 175067

MIsched: cleanup code. Use isBoundaryNode().

llvm-svn: 173775

Use const reference instead of vector copying.

llvm-svn: 173497

MIsched: Print block name. No functionality.

llvm-svn: 173433

MachineScheduler support for viewGraph.

llvm-svn: 173432

MIsched: Improve the interface to SchedDFS analysis (subtrees).

Allow the strategy to select SchedDFS. Allow the results of SchedDFS
to affect initialization of the scheduler state.

llvm-svn: 173425

MISched: Add SchedDFSResult to ScheduleDAGMI to formalize the
interface and allow other strategies to select it.

llvm-svn: 173413