Added -misched-regpressure option.

Register pressure tracking is half the complexity of the
scheduler. It's useful to be able to turn it off for compile time and
performance comparisons.

llvm-svn:

Added -misched-regpressure option.

Register pressure tracking is half the complexity of the
scheduler. It's useful to be able to turn it off for compile time and
performance comparisons.

llvm-svn: 189987

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Fix my previous checkin to updatePressureDiffs.

There was one case that we could hit a DebugValue where I didn't think
to check. DebugValues are evil. No checkinable test case, sorry. It's
an obviou

Fix my previous checkin to updatePressureDiffs.

There was one case that we could hit a DebugValue where I didn't think
to check. DebugValues are evil. No checkinable test case, sorry. It's
an obvious fix.

llvm-svn: 189717

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mi-sched: update PressureDiffs on-the-fly for liveness.

This removes all expensive pressure tracking logic from the scheduling
critical path of node comparison.

llvm-svn: 189643

mi-sched: improve the generic register pressure comparison.

Only compare pressure within the same set. When multiple sets are
affected, we prioritize the most constrained set.

llvm-svn: 189641

mi-sched: Precompute a PressureDiff for each instruction, adjust for liveness later.

Created SUPressureDiffs array to hold the per node PDiff computed during DAG building.

Added a getUpwardPressure

mi-sched: Precompute a PressureDiff for each instruction, adjust for liveness later.

Created SUPressureDiffs array to hold the per node PDiff computed during DAG building.

Added a getUpwardPressureDelta API that will soon replace the old
one. Compute PressureDelta here from the precomputed PressureDiffs.

Updating for liveness will come next.

llvm-svn: 189640

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comment typo

llvm-svn: 189635

Comment and revise the cyclic critical path code.

This should be much more clear now. It's still disabled pending testing.

llvm-svn: 189597

Adds cyclic critical path computation and heuristics, temporarily disabled.

Estimate the cyclic critical path within a single block loop. If the
acyclic critical path is longer, then the loop will e

Adds cyclic critical path computation and heuristics, temporarily disabled.

Estimate the cyclic critical path within a single block loop. If the
acyclic critical path is longer, then the loop will exhaust OOO
resources after some number of iterations. If lag between the acyclic
critical path and cyclic critical path is longer the the time it takes
to issue those loop iterations, then aggressively schedule for
latency.

llvm-svn: 189120

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mi-sched: Don't call MBB.size() in initSUnits. The driver already has instr count.

This fixes a pathological compile time problem with very large blocks
and lots of scheduling boundaries.

llvm-svn:

mi-sched: Don't call MBB.size() in initSUnits. The driver already has instr count.

This fixes a pathological compile time problem with very large blocks
and lots of scheduling boundaries.

llvm-svn: 189116

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Confusing comment typo.

llvm-svn: 187895

MI Sched: Track live-thru registers.

When registers must be live throughout the scheduling region, increase
the limit for the register class. Once we exceed the original limit,
they will be spilled,

MI Sched: Track live-thru registers.

When registers must be live throughout the scheduling region, increase
the limit for the register class. Once we exceed the original limit,
they will be spilled, and there's no point further reducing pressure.

This isn't a perfect heuristics but avoids a situation where the
scheduler could become trapped by trying to achieve the impossible.

llvm-svn: 187436

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MI Sched fix: assert "Disconnected LRG within the scheduling region."

llvm-svn: 187435

MI Sched: Register pressure heuristics.

Consider which set is being increased or decreased before comparing.

llvm-svn: 187110

Dump LIS before regalloc. MI sched changes them.

llvm-svn: 187107

Fix uninitialized memory read found by MemorySanitizer: always set output parameter of ConvergingScheduler::SchedBoundary::getOtherResourceCount

llvm-svn: 186658

MI Sched: Update the way resources are tracked so the current heuristics make more sense.

llvm-svn: 186632

MI-Sched: cleanup DEBUG output.

llvm-svn: 184565

MI-Sched: Adjust regpressure limits for reserved regs.

llvm-svn: 184564

Give RegMax higher priority.

llvm-svn: 184133

Remove compareRPDelta.

A complex, expensive heuristic with little value in the current design.

llvm-svn: 184132

MI-Sched: Remove another heuristic that is sensitive to queue order.

llvm-svn: 184130

MI-Sched: Track multiple candidates with the same priority level.

This eliminates the MultiPressure scheduling "reason". It was
sensitive to queue order. We don't like being sensitive to queue
order

MI-Sched: Track multiple candidates with the same priority level.

This eliminates the MultiPressure scheduling "reason". It was
sensitive to queue order. We don't like being sensitive to queue
order.

llvm-svn: 184129

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Missing NDEBUGs.

llvm-svn: 184039

MI-Sched: heuristics using the new latency and machine model.

llvm-svn: 184038

Machine Model: Add MicroOpBufferSize and resource BufferSize.

Replace the ill-defined MinLatency and ILPWindow properties with
with straightforward buffer sizes:
MCSchedMode::MicroOpBufferSize
MCPro

Machine Model: Add MicroOpBufferSize and resource BufferSize.

Replace the ill-defined MinLatency and ILPWindow properties with
with straightforward buffer sizes:
MCSchedMode::MicroOpBufferSize
MCProcResourceDesc::BufferSize

These can be used to more precisely model instruction execution if desired.

Disabled some misched tests temporarily. They'll be reenabled in a few commits.

llvm-svn: 184032

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