jme: Enable PHY calibration to fix compat issue w/ certain switches

EA settings are obtained from JMicron Linux driver.

See-also: FreeBSD PR kern/177400

jme: RX interrupt to ~6000Hz, TX interrupt to ~4000Hz

jme: Support multiple MSI-X interrupt model

jme: Rework software reset procedure

There is a wired TX/RX clock synchronization issues during software reset.
To address these issues we have to disable and enable TX/RX clocks several
times accor

jme: Rework software reset procedure

There is a wired TX/RX clock synchronization issues during software reset.
To address these issues we have to disable and enable TX/RX clocks several
times according to JMicron's document.

These clock synchronization issues seem to affect JMC250C/JMC260C chips,
however, it is claimed that these issues affact all JMC250/JMC260 chips.

Thank JMicron for providing JMC250C samples and detailed document.

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jme(4): Pass packet info to ether_input_chain()

jme(4): Using code logic to create redirect table.

- Avoid using magic number when creating redirect table, apply
code logic instead.
- Add comment about how the redirect table is filled.

jme(4): Get key from Toeplitz code

Allow packet count based RX/TX interrupt coalescing to be disabled.
This is helpful if large amount of small packets are injected into or
bumped from the NIC; pure timeout based RX/TX interrupt coale

Allow packet count based RX/TX interrupt coalescing to be disabled.
This is helpful if large amount of small packets are injected into or
bumped from the NIC; pure timeout based RX/TX interrupt coalescing is
more effective under this situation.

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Bring in RSS (receive side scaling) support, i.e. multiple RX queues

First step toward multiple RX ring support

- JMC260 with full mask revision 2 and ECO revision 0 does not support
64bits DMA operatoin.
- Newer parts (full mask revision >= 2) of JMC250/JMC260 require driver
to configure TX offload engine

- JMC260 with full mask revision 2 and ECO revision 0 does not support
64bits DMA operatoin.
- Newer parts (full mask revision >= 2) of JMC250/JMC260 require driver
to configure TX offload engine and TX MAC clock source according to the
current link speed.
- New datasheet no longer uses PCI revision ID to identify chip generation,
but chipmode's full mask revision and ECO revision are used; update
driver accordingly.

Thank Ethan <ethanhsiao@jmicron.com> for pointing out necessary updates
and sending me an EVB.

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- RX/TX coal parameters could be set at any time.
- Set default RX coal packets to 64, so RX coal timeout takes control during
bulk data operations. This greately reduces the interrupt rate while

- RX/TX coal parameters could be set at any time.
- Set default RX coal packets to 64, so RX coal timeout takes control during
bulk data operations. This greately reduces the interrupt rate while keeps
bulk data performance.
- Set default TX coal packets to 64 and TX coal timeout to 65535us (maximum
allowable value). This greately reduce the interrupt rate while greately
increases (almost doubles) small packet TX performance.
- Remove unused field in jme_softc

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Add workaround for JMC250A2 under 10/100 hdx mode.

Information provided by Ethen <ethanhsiao@jmicron.com>

- Clean up header inclusion
- Add revid for JMC250

Use IDs from pcidevs.h

Add support for JMicron Gigabit/Fast Ethernet chips.

Thank Ethan <ethanhsiao@jmicron.com> for sending me a board and several
very detailed documents about these chips.
Thank Pyun YongHyeon <yongari@

Add support for JMicron Gigabit/Fast Ethernet chips.

Thank Ethan <ethanhsiao@jmicron.com> for sending me a board and several
very detailed documents about these chips.
Thank Pyun YongHyeon <yongari@freebsd.org> for bridging me and JMicron.

Obtained-from: FreeBSD (yongari@freebsd.org) w/ modification

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