1 /*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/jme/if_jmereg.h,v 1.1 2008/05/27 01:42:01 yongari Exp $ 28 * $DragonFly: src/sys/dev/netif/jme/if_jmereg.h,v 1.2 2008/09/13 02:30:37 sephe Exp $ 29 */ 30 31 #ifndef _IF_JMEREG_H 32 #define _IF_JMEREG_H 33 34 /* JMC250 PCI configuration register. */ 35 #define JME_PCIR_BAR PCIR_BAR(0) 36 37 #define JME_PCI_EROM 0x30 38 39 #define JME_PCI_DBG 0x9C 40 41 #define JME_PCI_SPI 0xB0 42 43 #define SPI_ENB 0x00000010 44 #define SPI_SO_STATUS 0x00000008 45 #define SPI_SI_CTRL 0x00000004 46 #define SPI_SCK_CTRL 0x00000002 47 #define SPI_CS_N_CTRL 0x00000001 48 49 #define JME_PCI_PHYCFG0 0xC0 50 51 #define JME_PCI_PHYCFG1 0xC4 52 53 #define JME_PCI_PHYCFG2 0xC8 54 55 #define JME_PCI_PHYCFG3 0xCC 56 57 #define JME_PCI_PIPECTL1 0xD0 58 59 #define JME_PCI_PIPECTL2 0xD4 60 61 /* PCIe link error/status. */ 62 #define JME_PCI_LES 0xD8 63 64 /* propeietary register 0. */ 65 #define JME_PCI_PE0 0xE0 66 #define PE0_SPI_EXIST 0x00200000 67 #define PE0_PME_D0 0x00100000 68 #define PE0_PME_D3H 0x00080000 69 #define PE0_PME_SPI_PAD 0x00040000 70 #define PE0_MASK_ASPM 0x00020000 71 #define PE0_EEPROM_RW_DIS 0x00008000 72 #define PE0_PCI_INTA 0x00001000 73 #define PE0_PCI_INTB 0x00002000 74 #define PE0_PCI_INTC 0x00003000 75 #define PE0_PCI_INTD 0x00004000 76 #define PE0_PCI_SVSSID_WR_ENB 0x00000800 77 #define PE0_MSIX_SIZE_8 0x00000700 78 #define PE0_MSIX_SIZE_7 0x00000600 79 #define PE0_MSIX_SIZE_6 0x00000500 80 #define PE0_MSIX_SIZE_5 0x00000400 81 #define PE0_MSIX_SIZE_4 0x00000300 82 #define PE0_MSIX_SIZE_3 0x00000200 83 #define PE0_MSIX_SIZE_2 0x00000100 84 #define PE0_MSIX_SIZE_1 0x00000000 85 #define PE0_MSIX_SIZE_DEF 0x00000700 86 #define PE0_MSIX_CAP_DIS 0x00000080 87 #define PE0_MSI_PVMC_ENB 0x00000040 88 #define PE0_LCAP_EXIT_LAT_MASK 0x00000038 89 #define PE0_LCAP_EXIT_LAT_DEF 0x00000038 90 #define PE0_PM_AUXC_MASK 0x00000007 91 #define PE0_PM_AUXC_DEF 0x00000007 92 93 #define JME_PCI_PE1 0xE4 94 95 #define JME_PCI_PHYTEST 0xF8 96 97 #define JME_PCI_GPR 0xFC 98 99 /* 100 * JMC Register Map. 101 * ----------------------------------------------------------------------- 102 * Register Size IO space Memory space 103 * ----------------------------------------------------------------------- 104 * Tx/Rx MAC registers 128 bytes BAR1 + 0x00 ~ BAR0 + 0x00 ~ 105 * BAR1 + 0x7F BAR0 + 0x7F 106 * ----------------------------------------------------------------------- 107 * PHY registers 128 bytes BAR2 + 0x00 ~ BAR0 + 0x400 ~ 108 * BAR2 + 0x7F BAR0 + 0x47F 109 * ----------------------------------------------------------------------- 110 * Misc registers 128 bytes BAR2 + 0x80 ~ BAR0 + 0x800 ~ 111 * BAR2 + 0x7F BAR0 + 0x87F 112 * ----------------------------------------------------------------------- 113 * To simplify register access fuctions and to get better performance 114 * this driver doesn't support IO space access. It could be implemented 115 * as a function which selects appropriate BARs to access requested 116 * register. 117 */ 118 119 /* Tx control and status. */ 120 #define JME_TXCSR 0x0000 121 #define TXCSR_QWEIGHT_MASK 0x0F000000 122 #define TXCSR_QWEIGHT_SHIFT 24 123 #define TXCSR_TXQ_SEL_MASK 0x00070000 124 #define TXCSR_TXQ_SEL_SHIFT 16 125 #define TXCSR_TXQ_START 0x00000001 126 #define TXCSR_TXQ_START_SHIFT 8 127 #define TXCSR_FIFO_THRESH_4QW 0x00000000 128 #define TXCSR_FIFO_THRESH_8QW 0x00000040 129 #define TXCSR_FIFO_THRESH_12QW 0x00000080 130 #define TXCSR_FIFO_THRESH_16QW 0x000000C0 131 #define TXCSR_DMA_SIZE_64 0x00000000 132 #define TXCSR_DMA_SIZE_128 0x00000010 133 #define TXCSR_DMA_SIZE_256 0x00000020 134 #define TXCSR_DMA_SIZE_512 0x00000030 135 #define TXCSR_DMA_BURST 0x00000004 136 #define TXCSR_TX_SUSPEND 0x00000002 137 #define TXCSR_TX_ENB 0x00000001 138 #define TXCSR_TXQ0 0 139 #define TXCSR_TXQ1 1 140 #define TXCSR_TXQ2 2 141 #define TXCSR_TXQ3 3 142 #define TXCSR_TXQ4 4 143 #define TXCSR_TXQ5 5 144 #define TXCSR_TXQ6 6 145 #define TXCSR_TXQ7 7 146 #define TXCSR_TXQ_WEIGHT(x) \ 147 (((x) << TXCSR_QWEIGHT_SHIFT) & TXCSR_QWEIGHT_MASK) 148 #define TXCSR_TXQ_WEIGHT_MIN 0 149 #define TXCSR_TXQ_WEIGHT_MAX 15 150 #define TXCSR_TXQ_N_SEL(x) \ 151 (((x) << TXCSR_TXQ_SEL_SHIFT) & TXCSR_TXQ_SEL_MASK) 152 #define TXCSR_TXQ_N_START(x) \ 153 (TXCSR_TXQ_START << (TXCSR_TXQ_START_SHIFT + (x))) 154 155 /* Tx queue descriptor base address. 16bytes alignment required. */ 156 #define JME_TXDBA_LO 0x0004 157 #define JME_TXDBA_HI 0x0008 158 159 /* Tx queue descriptor count. multiple of 16(max = 1024). */ 160 #define JME_TXQDC 0x000C 161 #define TXQDC_MASK 0x0000007F0 162 163 /* Tx queue next descriptor address. */ 164 #define JME_TXNDA 0x0010 165 #define TXNDA_ADDR_MASK 0xFFFFFFF0 166 #define TXNDA_DESC_EMPTY 0x00000008 167 #define TXNDA_DESC_VALID 0x00000004 168 #define TXNDA_DESC_WAIT 0x00000002 169 #define TXNDA_DESC_FETCH 0x00000001 170 171 /* Tx MAC control ans status. */ 172 #define JME_TXMAC 0x0014 173 #define TXMAC_IFG2_MASK 0xC0000000 174 #define TXMAC_IFG2_DEFAULT 0x40000000 175 #define TXMAC_IFG1_MASK 0x30000000 176 #define TXMAC_IFG1_DEFAULT 0x20000000 177 #define TXMAC_THRESH_1_PKT 0x00000300 178 #define TXMAC_THRESH_1_2_PKT 0x00000200 179 #define TXMAC_THRESH_1_4_PKT 0x00000100 180 #define TXMAC_THRESH_1_8_PKT 0x00000000 181 #define TXMAC_FRAME_BURST 0x00000080 182 #define TXMAC_CARRIER_EXT 0x00000040 183 #define TXMAC_IFG_ENB 0x00000020 184 #define TXMAC_BACKOFF 0x00000010 185 #define TXMAC_CARRIER_SENSE 0x00000008 186 #define TXMAC_COLL_ENB 0x00000004 187 #define TXMAC_CRC_ENB 0x00000002 188 #define TXMAC_PAD_ENB 0x00000001 189 190 /* Tx pause frame control. */ 191 #define JME_TXPFC 0x0018 192 #define TXPFC_VLAN_TAG_MASK 0xFFFF0000 193 #define TXPFC_VLAN_TAG_SHIFT 16 194 #define TXPFC_VLAN_ENB 0x00008000 195 #define TXPFC_PAUSE_ENB 0x00000001 196 197 /* Tx timer/retry at half duplex. */ 198 #define JME_TXTRHD 0x001C 199 #define TXTRHD_RT_PERIOD_ENB 0x80000000 200 #define TXTRHD_RT_PERIOD_MASK 0x7FFFFF00 201 #define TXTRHD_RT_PERIOD_SHIFT 8 202 #define TXTRHD_RT_LIMIT_ENB 0x00000080 203 #define TXTRHD_RT_LIMIT_MASK 0x0000007F 204 #define TXTRHD_RT_LIMIT_SHIFT 0 205 #define TXTRHD_RT_PERIOD_DEFAULT 8192 206 #define TXTRHD_RT_LIMIT_DEFAULT 8 207 208 /* Rx control & status. */ 209 #define JME_RXCSR 0x0020 210 #define RXCSR_FIFO_FTHRESH_16T 0x00000000 211 #define RXCSR_FIFO_FTHRESH_32T 0x10000000 212 #define RXCSR_FIFO_FTHRESH_64T 0x20000000 213 #define RXCSR_FIFO_FTHRESH_128T 0x30000000 214 #define RXCSR_FIFO_FTHRESH_MASK 0x30000000 215 #define RXCSR_FIFO_THRESH_16QW 0x00000000 216 #define RXCSR_FIFO_THRESH_32QW 0x04000000 217 #define RXCSR_FIFO_THRESH_64QW 0x08000000 218 #define RXCSR_FIFO_THRESH_128QW 0x0C000000 219 #define RXCSR_FIFO_THRESH_MASK 0x0C000000 220 #define RXCSR_DMA_SIZE_16 0x00000000 221 #define RXCSR_DMA_SIZE_32 0x01000000 222 #define RXCSR_DMA_SIZE_64 0x02000000 223 #define RXCSR_DMA_SIZE_128 0x03000000 224 #define RXCSR_RXQ_SEL_MASK 0x00030000 225 #define RXCSR_RXQ_SEL_SHIFT 16 226 #define RXCSR_DESC_RT_GAP_MASK 0x0000F000 227 #define RXCSR_DESC_RT_GAP_SHIFT 12 228 #define RXCSR_DESC_RT_GAP_256 0x00000000 229 #define RXCSR_DESC_RT_GAP_512 0x00001000 230 #define RXCSR_DESC_RT_GAP_1024 0x00002000 231 #define RXCSR_DESC_RT_GAP_2048 0x00003000 232 #define RXCSR_DESC_RT_GAP_4096 0x00004000 233 #define RXCSR_DESC_RT_GAP_8192 0x00005000 234 #define RXCSR_DESC_RT_GAP_16384 0x00006000 235 #define RXCSR_DESC_RT_GAP_32768 0x00007000 236 #define RXCSR_DESC_RT_CNT_MASK 0x00000F00 237 #define RXCSR_DESC_RT_CNT_SHIFT 8 238 #define RXCSR_PASS_WAKEUP_PKT 0x00000040 239 #define RXCSR_PASS_MAGIC_PKT 0x00000020 240 #define RXCSR_PASS_RUNT_PKT 0x00000010 241 #define RXCSR_PASS_BAD_PKT 0x00000008 242 #define RXCSR_RXQ_START 0x00000004 243 #define RXCSR_RX_SUSPEND 0x00000002 244 #define RXCSR_RX_ENB 0x00000001 245 246 #define RXCSR_RXQ_N_SEL(x) ((x) << RXCSR_RXQ_SEL_SHIFT) 247 #define RXCSR_RXQ0 0 248 #define RXCSR_RXQ1 1 249 #define RXCSR_RXQ2 2 250 #define RXCSR_RXQ3 3 251 #define RXCSR_DESC_RT_CNT(x) \ 252 ((((x) / 4) << RXCSR_DESC_RT_CNT_SHIFT) & RXCSR_DESC_RT_CNT_MASK) 253 #define RXCSR_DESC_RT_CNT_DEFAULT 32 254 255 /* Rx queue descriptor base address. 16bytes alignment needed. */ 256 #define JME_RXDBA_LO 0x0024 257 #define JME_RXDBA_HI 0x0028 258 259 /* Rx queue descriptor count. multiple of 16(max = 1024). */ 260 #define JME_RXQDC 0x002C 261 #define RXQDC_MASK 0x0000007F0 262 263 /* Rx queue next descriptor address. */ 264 #define JME_RXNDA 0x0030 265 #define RXNDA_ADDR_MASK 0xFFFFFFF0 266 #define RXNDA_DESC_EMPTY 0x00000008 267 #define RXNDA_DESC_VALID 0x00000004 268 #define RXNDA_DESC_WAIT 0x00000002 269 #define RXNDA_DESC_FETCH 0x00000001 270 271 /* Rx MAC control and status. */ 272 #define JME_RXMAC 0x0034 273 #define RXMAC_RSS_UNICAST 0x00000000 274 #define RXMAC_RSS_UNI_MULTICAST 0x00010000 275 #define RXMAC_RSS_UNI_MULTI_BROADCAST 0x00020000 276 #define RXMAC_RSS_ALLFRAME 0x00030000 277 #define RXMAC_PROMISC 0x00000800 278 #define RXMAC_BROADCAST 0x00000400 279 #define RXMAC_MULTICAST 0x00000200 280 #define RXMAC_UNICAST 0x00000100 281 #define RXMAC_ALLMULTI 0x00000080 282 #define RXMAC_MULTICAST_FILTER 0x00000040 283 #define RXMAC_COLL_DET_ENB 0x00000020 284 #define RXMAC_FC_ENB 0x00000008 285 #define RXMAC_VLAN_ENB 0x00000004 286 #define RXMAC_PAD_10BYTES 0x00000002 287 #define RXMAC_CSUM_ENB 0x00000001 288 289 /* Rx unicast MAC address. */ 290 #define JME_PAR0 0x0038 291 #define JME_PAR1 0x003C 292 293 /* Rx multicast address hash table. */ 294 #define JME_MAR0 0x0040 295 #define JME_MAR1 0x0044 296 297 /* Wakeup frame output data port. */ 298 #define JME_WFODP 0x0048 299 300 /* Wakeup frame output interface. */ 301 #define JME_WFOI 0x004C 302 #define WFOI_MASK_0_31 0x00000000 303 #define WFOI_MASK_31_63 0x00000010 304 #define WFOI_MASK_64_95 0x00000020 305 #define WFOI_MASK_96_127 0x00000030 306 #define WFOI_MASK_SEL 0x00000008 307 #define WFOI_CRC_SEL 0x00000000 308 #define WFOI_WAKEUP_FRAME_MASK 0x00000007 309 #define WFOI_WAKEUP_FRAME_SEL(x) ((x) & WFOI_WAKEUP_FRAME_MASK) 310 311 /* Station management interface. */ 312 #define JME_SMI 0x0050 313 #define SMI_DATA_MASK 0xFFFF0000 314 #define SMI_DATA_SHIFT 16 315 #define SMI_REG_ADDR_MASK 0x0000F800 316 #define SMI_REG_ADDR_SHIFT 11 317 #define SMI_PHY_ADDR_MASK 0x000007C0 318 #define SMI_PHY_ADDR_SHIFT 6 319 #define SMI_OP_WRITE 0x00000020 320 #define SMI_OP_READ 0x00000000 321 #define SMI_OP_EXECUTE 0x00000010 322 #define SMI_MDIO 0x00000008 323 #define SMI_MDOE 0x00000004 324 #define SMI_MDC 0x00000002 325 #define SMI_MDEN 0x00000001 326 #define SMI_REG_ADDR(x) \ 327 (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK) 328 #define SMI_PHY_ADDR(x) \ 329 (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK) 330 331 /* Global host control. */ 332 #define JME_GHC 0x0054 333 #define GHC_LOOPBACK 0x80000000 334 #define GHC_RESET 0x40000000 335 #define GHC_FULL_DUPLEX 0x00000040 336 #define GHC_SPEED_UNKNOWN 0x00000000 337 #define GHC_SPEED_10 0x00000010 338 #define GHC_SPEED_100 0x00000020 339 #define GHC_SPEED_1000 0x00000030 340 #define GHC_SPEED_MASK 0x00000030 341 #define GHC_LINK_OFF 0x00000004 342 #define GHC_LINK_ON 0x00000002 343 #define GHC_LINK_STAT_POLLING 0x00000001 344 345 /* Power management control and status. */ 346 #define JME_PMCS 0x0060 347 #define PMCS_WAKEUP_FRAME_7 0x80000000 348 #define PMCS_WAKEUP_FRAME_6 0x40000000 349 #define PMCS_WAKEUP_FRAME_5 0x20000000 350 #define PMCS_WAKEUP_FRAME_4 0x10000000 351 #define PMCS_WAKEUP_FRAME_3 0x08000000 352 #define PMCS_WAKEUP_FRAME_2 0x04000000 353 #define PMCS_WAKEUP_FRAME_1 0x02000000 354 #define PMCS_WAKEUP_FRAME_0 0x01000000 355 #define PMCS_LINK_FAIL 0x00040000 356 #define PMCS_LINK_RISING 0x00020000 357 #define PMCS_MAGIC_FRAME 0x00010000 358 #define PMCS_WAKEUP_FRAME_7_ENB 0x00008000 359 #define PMCS_WAKEUP_FRAME_6_ENB 0x00004000 360 #define PMCS_WAKEUP_FRAME_5_ENB 0x00002000 361 #define PMCS_WAKEUP_FRAME_4_ENB 0x00001000 362 #define PMCS_WAKEUP_FRAME_3_ENB 0x00000800 363 #define PMCS_WAKEUP_FRAME_2_ENB 0x00000400 364 #define PMCS_WAKEUP_FRAME_1_ENB 0x00000200 365 #define PMCS_WAKEUP_FRAME_0_ENB 0x00000100 366 #define PMCS_LINK_FAIL_ENB 0x00000004 367 #define PMCS_LINK_RISING_ENB 0x00000002 368 #define PMCS_MAGIC_FRAME_ENB 0x00000001 369 #define PMCS_WOL_ENB_MASK 0x0000FFFF 370 371 /* Giga PHY & EEPROM registers. */ 372 #define JME_PHY_EEPROM_BASE_ADDR 0x0400 373 374 #define JME_GIGAR0LO 0x0400 375 #define JME_GIGAR0HI 0x0404 376 #define JME_GIGARALO 0x0408 377 #define JME_GIGARAHI 0x040C 378 #define JME_GIGARBLO 0x0410 379 #define JME_GIGARBHI 0x0414 380 #define JME_GIGARCLO 0x0418 381 #define JME_GIGARCHI 0x041C 382 #define JME_GIGARDLO 0x0420 383 #define JME_GIGARDHI 0x0424 384 385 /* BIST status and control. */ 386 #define JME_GIGACSR 0x0428 387 #define GIGACSR_STATUS 0x40000000 388 #define GIGACSR_CTRL_MASK 0x30000000 389 #define GIGACSR_CTRL_DEFAULT 0x30000000 390 #define GIGACSR_TX_CLK_MASK 0x0F000000 391 #define GIGACSR_RX_CLK_MASK 0x00F00000 392 #define GIGACSR_TX_CLK_INV 0x00080000 393 #define GIGACSR_RX_CLK_INV 0x00040000 394 #define GIGACSR_PHY_RST 0x00010000 395 #define GIGACSR_IRQ_N_O 0x00001000 396 #define GIGACSR_BIST_OK 0x00000200 397 #define GIGACSR_BIST_DONE 0x00000100 398 #define GIGACSR_BIST_LED_ENB 0x00000010 399 #define GIGACSR_BIST_MASK 0x00000003 400 401 /* PHY Link Status. */ 402 #define JME_LNKSTS 0x0430 403 #define LINKSTS_SPEED_10 0x00000000 404 #define LINKSTS_SPEED_100 0x00004000 405 #define LINKSTS_SPEED_1000 0x00008000 406 #define LINKSTS_FULL_DUPLEX 0x00002000 407 #define LINKSTS_PAGE_RCVD 0x00001000 408 #define LINKSTS_SPDDPX_RESOLVED 0x00000800 409 #define LINKSTS_UP 0x00000400 410 #define LINKSTS_ANEG_COMP 0x00000200 411 #define LINKSTS_MDI_CROSSOVR 0x00000040 412 #define LINKSTS_LPAR_PAUSE_ASYM 0x00000002 413 #define LINKSTS_LPAR_PAUSE 0x00000001 414 415 /* SMB control and status. */ 416 #define JME_SMBCSR 0x0440 417 #define SMBCSR_SLAVE_ADDR_MASK 0x7F000000 418 #define SMBCSR_WR_DATA_NACK 0x00040000 419 #define SMBCSR_CMD_NACK 0x00020000 420 #define SMBCSR_RELOAD 0x00010000 421 #define SMBCSR_CMD_ADDR_MASK 0x0000FF00 422 #define SMBCSR_SCL_STAT 0x00000080 423 #define SMBCSR_SDA_STAT 0x00000040 424 #define SMBCSR_EEPROM_PRESENT 0x00000020 425 #define SMBCSR_INIT_LD_DONE 0x00000010 426 #define SMBCSR_HW_BUSY_MASK 0x0000000F 427 #define SMBCSR_HW_IDLE 0x00000000 428 429 /* SMB interface. */ 430 #define JME_SMBINTF 0x0444 431 #define SMBINTF_RD_DATA_MASK 0xFF000000 432 #define SMBINTF_RD_DATA_SHIFT 24 433 #define SMBINTF_WR_DATA_MASK 0x00FF0000 434 #define SMBINTF_WR_DATA_SHIFT 16 435 #define SMBINTF_ADDR_MASK 0x0000FF00 436 #define SMBINTF_ADDR_SHIFT 8 437 #define SMBINTF_RD 0x00000020 438 #define SMBINTF_WR 0x00000000 439 #define SMBINTF_CMD_TRIGGER 0x00000010 440 #define SMBINTF_BUSY 0x00000010 441 #define SMBINTF_FAST_MODE 0x00000008 442 #define SMBINTF_GPIO_SCL 0x00000004 443 #define SMBINTF_GPIO_SDA 0x00000002 444 #define SMBINTF_GPIO_ENB 0x00000001 445 446 #define JME_EEPROM_SIG0 0x55 447 #define JME_EEPROM_SIG1 0xAA 448 #define JME_EEPROM_DESC_BYTES 3 449 #define JME_EEPROM_DESC_END 0x80 450 #define JME_EEPROM_FUNC_MASK 0x70 451 #define JME_EEPROM_FUNC_SHIFT 4 452 #define JME_EEPROM_PAGE_MASK 0x0F 453 #define JME_EEPROM_PAGE_SHIFT 0 454 455 #define JME_EEPROM_FUNC0 0 456 /* PCI configuration space. */ 457 #define JME_EEPROM_PAGE_BAR0 0 458 /* 128 bytes I/O window. */ 459 #define JME_EEPROM_PAGE_BAR1 1 460 /* 256 bytes I/O window. */ 461 #define JME_EEPROM_PAGE_BAR2 2 462 463 #define JME_EEPROM_END 0xFF 464 465 #define JME_EEPROM_MKDESC(f, p) \ 466 ((((f) & JME_EEPROM_FUNC_MASK) << JME_EEPROM_FUNC_SHIFT) | \ 467 (((p) & JME_EEPROM_PAGE_MASK) << JME_EEPROM_PAGE_SHIFT)) 468 469 /* 3-wire EEPROM interface. Obsolete interface, use SMBCSR. */ 470 #define JME_EEPINTF 0x0448 471 #define EEPINTF_DATA_MASK 0xFFFF0000 472 #define EEPINTF_DATA_SHIFT 16 473 #define EEPINTF_ADDR_MASK 0x0000FC00 474 #define EEPINTF_ADDR_SHIFT 10 475 #define EEPRINTF_OP_MASK 0x00000300 476 #define EEPINTF_OP_EXECUTE 0x00000080 477 #define EEPINTF_DATA_OUT 0x00000008 478 #define EEPINTF_DATA_IN 0x00000004 479 #define EEPINTF_CLK 0x00000002 480 #define EEPINTF_SEL 0x00000001 481 482 /* 3-wire EEPROM control and status. Obsolete interface, use SMBCSR. */ 483 #define JME_EEPCSR 0x044C 484 #define EEPCSR_EEPROM_RELOAD 0x00000002 485 #define EEPCSR_EEPROM_PRESENT 0x00000001 486 487 /* Misc registers. */ 488 #define JME_MISC_BASE_ADDR 0x800 489 490 /* Timer control and status. */ 491 #define JME_TMCSR 0x0800 492 #define TMCSR_SW_INTR 0x80000000 493 #define TMCSR_TIMER_INTR 0x10000000 494 #define TMCSR_TIMER_ENB 0x01000000 495 #define TMCSR_TIMER_COUNT_MASK 0x00FFFFFF 496 497 /* GPIO control and status. */ 498 #define JME_GPIO 0x0804 499 #define GPIO_4_SPI_IN 0x80000000 500 #define GPIO_3_SPI_IN 0x40000000 501 #define GPIO_4_SPI_OUT 0x20000000 502 #define GPIO_4_SPI_OUT_ENB 0x10000000 503 #define GPIO_3_SPI_OUT 0x08000000 504 #define GPIO_3_SPI_OUT_ENB 0x04000000 505 #define GPIO_3_4_LED 0x00000000 506 #define GPIO_3_4_GPIO 0x02000000 507 #define GPIO_2_CLKREQN_IN 0x00100000 508 #define GPIO_2_CLKREQN_OUT 0x00040000 509 #define GPIO_2_CLKREQN_OUT_ENB 0x00020000 510 #define GPIO_1_LED42_IN 0x00001000 511 #define GPIO_1_LED42_OUT 0x00000400 512 #define GPIO_1_LED42_OUT_ENB 0x00000200 513 #define GPIO_1_LED42_ENB 0x00000100 514 #define GPIO_0_SDA_IN 0x00000010 515 #define GPIO_0_SDA_OUT 0x00000004 516 #define GPIO_0_SDA_OUT_ENB 0x00000002 517 #define GPIO_0_SDA_ENB 0x00000001 518 519 /* General purpose register 0. */ 520 #define JME_GPREG0 0x0808 521 #define GPREG0_SH_POST_DW7_DIS 0x80000000 522 #define GPREG0_SH_POST_DW6_DIS 0x40000000 523 #define GPREG0_SH_POST_DW5_DIS 0x20000000 524 #define GPREG0_SH_POST_DW4_DIS 0x10000000 525 #define GPREG0_SH_POST_DW3_DIS 0x08000000 526 #define GPREG0_SH_POST_DW2_DIS 0x04000000 527 #define GPREG0_SH_POST_DW1_DIS 0x02000000 528 #define GPREG0_SH_POST_DW0_DIS 0x01000000 529 #define GPREG0_DMA_RD_REQ_8 0x00000000 530 #define GPREG0_DMA_RD_REQ_6 0x00100000 531 #define GPREG0_DMA_RD_REQ_5 0x00200000 532 #define GPREG0_DMA_RD_REQ_4 0x00300000 533 #define GPREG0_POST_DW0_ENB 0x00040000 534 #define GPREG0_PCC_CLR_DIS 0x00020000 535 #define GPREG0_FORCE_SCL_OUT 0x00010000 536 #define GPREG0_DL_RSTB_DIS 0x00008000 537 #define GPREG0_STICKY_RESET 0x00004000 538 #define GPREG0_DL_RSTB_CFG_DIS 0x00002000 539 #define GPREG0_LINK_CHG_POLL 0x00001000 540 #define GPREG0_LINK_CHG_DIRECT 0x00000000 541 #define GPREG0_MSI_GEN_SEL 0x00000800 542 #define GPREG0_SMB_PAD_PU_DIS 0x00000400 543 #define GPREG0_PCC_UNIT_16US 0x00000000 544 #define GPREG0_PCC_UNIT_256US 0x00000100 545 #define GPREG0_PCC_UNIT_US 0x00000200 546 #define GPREG0_PCC_UNIT_MS 0x00000300 547 #define GPREG0_PCC_UNIT_MASK 0x00000300 548 #define GPREG0_INTR_EVENT_ENB 0x00000080 549 #define GPREG0_PME_ENB 0x00000020 550 #define GPREG0_PHY_ADDR_MASK 0x0000001F 551 #define GPREG0_PHY_ADDR_SHIFT 0 552 #define GPREG0_PHY_ADDR 1 553 554 /* General purpose register 1. reserved for future use. */ 555 #define JME_GPREG1 0x080C 556 557 /* MSIX entry number of interrupt source. */ 558 #define JME_MSINUM_BASE 0x0810 559 #define JME_MSINUM_END 0x081F 560 #define MSINUM_MASK 0x7FFFFFFF 561 #define MSINUM_ENTRY_MASK 7 562 #define MSINUM_REG_INDEX(x) ((x) / 8) 563 #define MSINUM_INTR_SOURCE(x, y) \ 564 (((x) & MSINUM_ENTRY_MASK) << (((y) & 7) * 4)) 565 #define MSINUM_NUM_INTR_SOURCE 32 566 567 /* Interrupt event status. */ 568 #define JME_INTR_STATUS 0x0820 569 #define INTR_SW 0x80000000 570 #define INTR_TIMER 0x40000000 571 #define INTR_LINKCHG 0x20000000 572 #define INTR_PAUSE 0x10000000 573 #define INTR_MAGIC_PKT 0x08000000 574 #define INTR_WAKEUP_PKT 0x04000000 575 #define INTR_RXQ0_COAL_TO 0x02000000 576 #define INTR_RXQ1_COAL_TO 0x01000000 577 #define INTR_RXQ2_COAL_TO 0x00800000 578 #define INTR_RXQ3_COAL_TO 0x00400000 579 #define INTR_TXQ_COAL_TO 0x00200000 580 #define INTR_RXQ0_COAL 0x00100000 581 #define INTR_RXQ1_COAL 0x00080000 582 #define INTR_RXQ2_COAL 0x00040000 583 #define INTR_RXQ3_COAL 0x00020000 584 #define INTR_TXQ_COAL 0x00010000 585 #define INTR_RXQ3_DESC_EMPTY 0x00008000 586 #define INTR_RXQ2_DESC_EMPTY 0x00004000 587 #define INTR_RXQ1_DESC_EMPTY 0x00002000 588 #define INTR_RXQ0_DESC_EMPTY 0x00001000 589 #define INTR_RXQ3_COMP 0x00000800 590 #define INTR_RXQ2_COMP 0x00000400 591 #define INTR_RXQ1_COMP 0x00000200 592 #define INTR_RXQ0_COMP 0x00000100 593 #define INTR_TXQ7_COMP 0x00000080 594 #define INTR_TXQ6_COMP 0x00000040 595 #define INTR_TXQ5_COMP 0x00000020 596 #define INTR_TXQ4_COMP 0x00000010 597 #define INTR_TXQ3_COMP 0x00000008 598 #define INTR_TXQ2_COMP 0x00000004 599 #define INTR_TXQ1_COMP 0x00000002 600 #define INTR_TXQ0_COMP 0x00000001 601 602 #define INTR_RXQ_COAL_TO \ 603 (INTR_RXQ0_COAL_TO | INTR_RXQ1_COAL_TO | \ 604 INTR_RXQ2_COAL_TO | INTR_RXQ3_COAL_TO) 605 606 #define INTR_RXQ_COAL \ 607 (INTR_RXQ0_COAL | INTR_RXQ1_COAL | INTR_RXQ2_COAL | \ 608 INTR_RXQ3_COAL) 609 610 #define INTR_RXQ_COMP \ 611 (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \ 612 INTR_RXQ3_COMP) 613 614 #define INTR_RXQ_DESC_EMPTY \ 615 (INTR_RXQ0_DESC_EMPTY | INTR_RXQ1_DESC_EMPTY | \ 616 INTR_RXQ2_DESC_EMPTY | INTR_RXQ3_DESC_EMPTY) 617 618 #define INTR_RXQ_COMP \ 619 (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \ 620 INTR_RXQ3_COMP) 621 622 #define INTR_TXQ_COMP \ 623 (INTR_TXQ0_COMP | INTR_TXQ1_COMP | INTR_TXQ2_COMP | \ 624 INTR_TXQ3_COMP | INTR_TXQ4_COMP | INTR_TXQ5_COMP | \ 625 INTR_TXQ6_COMP | INTR_TXQ7_COMP) 626 627 #define JME_INTRS \ 628 (INTR_RXQ_COAL_TO | INTR_TXQ_COAL_TO | INTR_RXQ_COAL | \ 629 INTR_TXQ_COAL | INTR_RXQ_DESC_EMPTY) 630 631 #define N_INTR_SW 31 632 #define N_INTR_TIMER 30 633 #define N_INTR_LINKCHG 29 634 #define N_INTR_PAUSE 28 635 #define N_INTR_MAGIC_PKT 27 636 #define N_INTR_WAKEUP_PKT 26 637 #define N_INTR_RXQ0_COAL_TO 25 638 #define N_INTR_RXQ1_COAL_TO 24 639 #define N_INTR_RXQ2_COAL_TO 23 640 #define N_INTR_RXQ3_COAL_TO 22 641 #define N_INTR_TXQ_COAL_TO 21 642 #define N_INTR_RXQ0_COAL 20 643 #define N_INTR_RXQ1_COAL 19 644 #define N_INTR_RXQ2_COAL 18 645 #define N_INTR_RXQ3_COAL 17 646 #define N_INTR_TXQ_COAL 16 647 #define N_INTR_RXQ3_DESC_EMPTY 15 648 #define N_INTR_RXQ2_DESC_EMPTY 14 649 #define N_INTR_RXQ1_DESC_EMPTY 13 650 #define N_INTR_RXQ0_DESC_EMPTY 12 651 #define N_INTR_RXQ3_COMP 11 652 #define N_INTR_RXQ2_COMP 10 653 #define N_INTR_RXQ1_COMP 9 654 #define N_INTR_RXQ0_COMP 8 655 #define N_INTR_TXQ7_COMP 7 656 #define N_INTR_TXQ6_COMP 6 657 #define N_INTR_TXQ5_COMP 5 658 #define N_INTR_TXQ4_COMP 4 659 #define N_INTR_TXQ3_COMP 3 660 #define N_INTR_TXQ2_COMP 2 661 #define N_INTR_TXQ1_COMP 1 662 #define N_INTR_TXQ0_COMP 0 663 664 /* Interrupt request status. */ 665 #define JME_INTR_REQ_STATUS 0x0824 666 667 /* Interrupt enable - setting port. */ 668 #define JME_INTR_MASK_SET 0x0828 669 670 /* Interrupt enable - clearing port. */ 671 #define JME_INTR_MASK_CLR 0x082C 672 673 /* Packet completion coalescing control of Rx queue 0, 1, 2 and 3. */ 674 #define JME_PCCRX0 0x0830 675 #define JME_PCCRX1 0x0834 676 #define JME_PCCRX2 0x0838 677 #define JME_PCCRX3 0x083C 678 #define PCCRX_COAL_TO_MASK 0xFFFF0000 679 #define PCCRX_COAL_TO_SHIFT 16 680 #define PCCRX_COAL_PKT_MASK 0x0000FF00 681 #define PCCRX_COAL_PKT_SHIFT 8 682 683 #define PCCRX_COAL_TO_MIN 1 684 #define PCCRX_COAL_TO_DEFAULT 100 685 #define PCCRX_COAL_TO_MAX 65535 686 687 #define PCCRX_COAL_PKT_MIN 1 688 #define PCCRX_COAL_PKT_DEFAULT 2 689 #define PCCRX_COAL_PKT_MAX 255 690 691 /* Packet completion coalescing control of Tx queue. */ 692 #define JME_PCCTX 0x0840 693 #define PCCTX_COAL_TO_MASK 0xFFFF0000 694 #define PCCTX_COAL_TO_SHIFT 16 695 #define PCCTX_COAL_PKT_MASK 0x0000FF00 696 #define PCCTX_COAL_PKT_SHIFT 8 697 #define PCCTX_COAL_TXQ7 0x00000080 698 #define PCCTX_COAL_TXQ6 0x00000040 699 #define PCCTX_COAL_TXQ5 0x00000020 700 #define PCCTX_COAL_TXQ4 0x00000010 701 #define PCCTX_COAL_TXQ3 0x00000008 702 #define PCCTX_COAL_TXQ2 0x00000004 703 #define PCCTX_COAL_TXQ1 0x00000002 704 #define PCCTX_COAL_TXQ0 0x00000001 705 706 #define PCCTX_COAL_TO_MIN 1 707 #define PCCTX_COAL_TO_DEFAULT 100 708 #define PCCTX_COAL_TO_MAX 65535 709 710 #define PCCTX_COAL_PKT_MIN 1 711 #define PCCTX_COAL_PKT_DEFAULT 8 712 #define PCCTX_COAL_PKT_MAX 255 713 714 /* Chip mode and FPGA version. */ 715 #define JME_CHIPMODE 0x0844 716 #define CHIPMODE_FPGA_REV_MASK 0xFFFF0000 717 #define CHIPMODE_FPGA_REV_SHIFT 16 718 #define CHIPMODE_NOT_FPGA 0 719 #define CHIPMODE_REV_MASK 0x0000FF00 720 #define CHIPMODE_REV_SHIFT 8 721 #define CHIPMODE_MODE_48P 0x0000000C 722 #define CHIPMODE_MODE_64P 0x00000004 723 #define CHIPMODE_MODE_128P_MAC 0x00000003 724 #define CHIPMODE_MODE_128P_DBG 0x00000002 725 #define CHIPMODE_MODE_128P_PHY 0x00000000 726 727 /* Shadow status base address high/low. */ 728 #define JME_SHBASE_ADDR_HI 0x0848 729 #define JME_SHBASE_ADDR_LO 0x084C 730 #define SHBASE_ADDR_LO_MASK 0xFFFFFFE0 731 #define SHBASE_POST_FORCE 0x00000002 732 #define SHBASE_POST_ENB 0x00000001 733 734 /* Timer 1 and 2. */ 735 #define JME_TIMER1 0x0870 736 #define JME_TIMER2 0x0874 737 #define TIMER_ENB 0x01000000 738 #define TIMER_CNT_MASK 0x00FFFFFF 739 #define TIMER_CNT_SHIFT 0 740 #define TIMER_UNIT 1024 /* 1024us */ 741 742 /* Aggresive power mode control. */ 743 #define JME_APMC 0x087C 744 #define APMC_PCIE_SDOWN_STAT 0x80000000 745 #define APMC_PCIE_SDOWN_ENB 0x40000000 746 #define APMC_PSEUDO_HOT_PLUG 0x20000000 747 #define APMC_EXT_PLUGIN_ENB 0x04000000 748 #define APMC_EXT_PLUGIN_CTL_MSK 0x03000000 749 #define APMC_DIS_SRAM 0x00000004 750 #define APMC_DIS_CLKPM 0x00000002 751 #define APMC_DIS_CLKTX 0x00000001 752 753 /* Packet completion coalesing status of Rx queue 0, 1, 2 and 3. */ 754 #define JME_PCCSRX_BASE 0x0880 755 #define JME_PCCSRX_END 0x088F 756 #define PCCSRX_REG(x) (JME_PCCSRX_BASE + ((x) * 4)) 757 #define PCCSRX_TO_MASK 0xFFFF0000 758 #define PCCSRX_TO_SHIFT 16 759 #define PCCSRX_PKT_CNT_MASK 0x0000FF00 760 #define PCCSRX_PKT_CNT_SHIFT 8 761 762 /* Packet completion coalesing status of Tx queue. */ 763 #define JME_PCCSTX 0x0890 764 #define PCCSTX_TO_MASK 0xFFFF0000 765 #define PCCSTX_TO_SHIFT 16 766 #define PCCSTX_PKT_CNT_MASK 0x0000FF00 767 #define PCCSTX_PKT_CNT_SHIFT 8 768 769 /* Tx queues empty indicator. */ 770 #define JME_TXQEMPTY 0x0894 771 #define TXQEMPTY_TXQ7 0x00000080 772 #define TXQEMPTY_TXQ6 0x00000040 773 #define TXQEMPTY_TXQ5 0x00000020 774 #define TXQEMPTY_TXQ4 0x00000010 775 #define TXQEMPTY_TXQ3 0x00000008 776 #define TXQEMPTY_TXQ2 0x00000004 777 #define TXQEMPTY_TXQ1 0x00000002 778 #define TXQEMPTY_TXQ0 0x00000001 779 #define TXQEMPTY_N_TXQ(x, y) ((x) & (0x01 << (y))) 780 781 /* RSS control registers. */ 782 #define JME_RSS_BASE 0x0C00 783 784 #define JME_RSSC 0x0C00 785 #define RSSC_HASH_LEN_MASK 0x0000E000 786 #define RSSC_HASH_64_ENTRY 0x0000A000 787 #define RSSC_HASH_128_ENTRY 0x0000E000 788 #define RSSC_HASH_NONE 0x00001000 789 #define RSSC_HASH_IPV6 0x00000800 790 #define RSSC_HASH_IPV4 0x00000400 791 #define RSSC_HASH_IPV6_TCP 0x00000200 792 #define RSSC_HASH_IPV4_TCP 0x00000100 793 #define RSSC_NCPU_MASK 0x000000F8 794 #define RSSC_NCPU_SHIFT 3 795 #define RSSC_DIS_RSS 0x00000000 796 #define RSSC_2RXQ_ENB 0x00000001 797 #define RSSS_4RXQ_ENB 0x00000002 798 799 /* CPU vector. */ 800 #define JME_RSSCPU 0x0C04 801 #define RSSCPU_N_SEL(x) ((1 << (x)) 802 803 /* RSS Hash value. */ 804 #define JME_RSSHASH 0x0C10 805 806 #define JME_RSSHASH_STAT 0x0C14 807 808 #define JME_RSS_RDATA0 0x0C18 809 810 #define JME_RSS_RDATA1 0x0C1C 811 812 /* RSS secret key. */ 813 #define JME_RSSKEY_BASE 0x0C40 814 #define JME_RSSKEY_LAST 0x0C64 815 #define JME_RSSKEY_END 0x0C67 816 #define HASHKEY_NBYTES 40 817 #define RSSKEY_REG(x) (JME_RSSKEY_LAST - (4 * ((x) / 4))) 818 #define RSSKEY_VALUE(x, y) ((x) << (24 - 8 * ((y) % 4))) 819 820 /* RSS indirection table entries. */ 821 #define JME_RSSTBL_BASE 0x0C80 822 #define JME_RSSTBL_END 0x0CFF 823 #define RSSTBL_NENTRY 128 824 #define RSSTBL_REG(x) (JME_RSSTBL_BASE + ((x) / 4)) 825 #define RSSTBL_VALUE(x, y) ((x) << (8 * ((y) % 4))) 826 827 /* MSI-X table. */ 828 #define JME_MSIX_BASE_ADDR 0x2000 829 830 #define JME_MSIX_BASE 0x2000 831 #define JME_MSIX_END 0x207F 832 #define JME_MSIX_NENTRY 8 833 #define MSIX_REG(x) (JME_MSIX_BASE + ((x) * 0x10)) 834 #define MSIX_ADDR_HI_OFF 0x00 835 #define MSIX_ADDR_LO_OFF 0x04 836 #define MSIX_ADDR_LO_MASK 0xFFFFFFFC 837 #define MSIX_DATA_OFF 0x08 838 #define MSIX_VECTOR_OFF 0x0C 839 #define MSIX_VECTOR_RSVD 0x80000000 840 #define MSIX_VECTOR_DIS 0x00000001 841 842 /* MSI-X PBA. */ 843 #define JME_MSIX_PBA_BASE_ADDR 0x3000 844 845 #define JME_MSIX_PBA 0x3000 846 #define MSIX_PBA_RSVD_MASK 0xFFFFFF00 847 #define MSIX_PBA_RSVD_SHIFT 8 848 #define MSIX_PBA_PEND_MASK 0x000000FF 849 #define MSIX_PBA_PEND_SHIFT 0 850 #define MSIX_PBA_PEND_ENTRY7 0x00000080 851 #define MSIX_PBA_PEND_ENTRY6 0x00000040 852 #define MSIX_PBA_PEND_ENTRY5 0x00000020 853 #define MSIX_PBA_PEND_ENTRY4 0x00000010 854 #define MSIX_PBA_PEND_ENTRY3 0x00000008 855 #define MSIX_PBA_PEND_ENTRY2 0x00000004 856 #define MSIX_PBA_PEND_ENTRY1 0x00000002 857 #define MSIX_PBA_PEND_ENTRY0 0x00000001 858 859 #define JME_PHY_OUI 0x001B8C 860 #define JME_PHY_MODEL 0x21 861 #define JME_PHY_REV 0x01 862 #define JME_PHY_ADDR 1 863 864 /* JMC250 shadow status block. */ 865 struct jme_ssb { 866 uint32_t dw0; 867 uint32_t dw1; 868 uint32_t dw2; 869 uint32_t dw3; 870 uint32_t dw4; 871 uint32_t dw5; 872 uint32_t dw6; 873 uint32_t dw7; 874 }; 875 876 /* JMC250 descriptor structures. */ 877 struct jme_desc { 878 uint32_t flags; 879 uint32_t buflen; 880 uint32_t addr_hi; 881 uint32_t addr_lo; 882 }; 883 884 #define JME_TD_OWN 0x80000000 885 #define JME_TD_INTR 0x40000000 886 #define JME_TD_64BIT 0x20000000 887 #define JME_TD_TCPCSUM 0x10000000 888 #define JME_TD_UDPCSUM 0x08000000 889 #define JME_TD_IPCSUM 0x04000000 890 #define JME_TD_TSO 0x02000000 891 #define JME_TD_VLAN_TAG 0x01000000 892 #define JME_TD_VLAN_MASK 0x0000FFFF 893 894 #define JME_TD_MSS_MASK 0xFFFC0000 895 #define JME_TD_MSS_SHIFT 18 896 #define JME_TD_BUF_LEN_MASK 0x0000FFFF 897 #define JME_TD_BUF_LEN_SHIFT 0 898 899 #define JME_TD_FRAME_LEN_MASK 0x0000FFFF 900 #define JME_TD_FRAME_LEN_SHIFT 0 901 902 /* 903 * Only the first Tx descriptor of a packet is updated 904 * after packet transmission. 905 */ 906 #define JME_TD_TMOUT 0x20000000 907 #define JME_TD_RETRY_EXP 0x10000000 908 #define JME_TD_COLLISION 0x08000000 909 #define JME_TD_UNDERRUN 0x04000000 910 #define JME_TD_EHDR_SIZE_MASK 0x000000FF 911 #define JME_TD_EHDR_SIZE_SHIFT 0 912 913 #define JME_TD_SEG_CNT_MASK 0xFFFF0000 914 #define JME_TD_SEG_CNT_SHIFT 16 915 #define JME_TD_RETRY_CNT_MASK 0x0000FFFF 916 #define JME_TD_RETRY_CNT_SHIFT 0 917 918 #define JME_RD_OWN 0x80000000 919 #define JME_RD_INTR 0x40000000 920 #define JME_RD_64BIT 0x20000000 921 922 #define JME_RD_BUF_LEN_MASK 0x0000FFFF 923 #define JME_RD_BUF_LEN_SHIFT 0 924 925 /* 926 * Only the first Rx descriptor of a packet is updated 927 * after packet reception. 928 */ 929 #define JME_RD_MORE_FRAG 0x20000000 930 #define JME_RD_TCP 0x10000000 931 #define JME_RD_UDP 0x08000000 932 #define JME_RD_IPCSUM 0x04000000 933 #define JME_RD_TCPCSUM 0x02000000 934 #define JME_RD_UDPCSUM 0x01000000 935 #define JME_RD_VLAN_TAG 0x00800000 936 #define JME_RD_IPV4 0x00400000 937 #define JME_RD_IPV6 0x00200000 938 #define JME_RD_PAUSE 0x00100000 939 #define JME_RD_MAGIC 0x00080000 940 #define JME_RD_WAKEUP 0x00040000 941 #define JME_RD_BCAST 0x00030000 942 #define JME_RD_MCAST 0x00020000 943 #define JME_RD_UCAST 0x00010000 944 #define JME_RD_VLAN_MASK 0x0000FFFF 945 #define JME_RD_VLAN_SHIFT 0 946 947 #define JME_RD_VALID 0x80000000 948 #define JME_RD_CNT_MASK 0x7F000000 949 #define JME_RD_CNT_SHIFT 24 950 #define JME_RD_GIANT 0x00800000 951 #define JME_RD_GMII_ERR 0x00400000 952 #define JME_RD_NBL_RCVD 0x00200000 953 #define JME_RD_COLL 0x00100000 954 #define JME_RD_ABORT 0x00080000 955 #define JME_RD_RUNT 0x00040000 956 #define JME_RD_FIFO_OVRN 0x00020000 957 #define JME_RD_CRC_ERR 0x00010000 958 #define JME_RD_FRAME_LEN_MASK 0x0000FFFF 959 960 #define JME_RX_ERR_STAT \ 961 (JME_RD_GIANT | JME_RD_GMII_ERR | JME_RD_NBL_RCVD | \ 962 JME_RD_COLL | JME_RD_ABORT | JME_RD_RUNT | \ 963 JME_RD_FIFO_OVRN | JME_RD_CRC_ERR) 964 965 #define JME_RD_ERR_MASK 0x00FF0000 966 #define JME_RD_ERR_SHIFT 16 967 #define JME_RX_ERR(x) (((x) & JME_RD_ERR_MASK) >> JME_RD_ERR_SHIFT) 968 #define JME_RX_ERR_BITS "\20" \ 969 "\1CRCERR\2FIFOOVRN\3RUNT\4ABORT" \ 970 "\5COLL\6NBLRCVD\7GMIIERR\10" 971 972 #define JME_RX_NSEGS(x) (((x) & JME_RD_CNT_MASK) >> JME_RD_CNT_SHIFT) 973 #define JME_RX_BYTES(x) ((x) & JME_RD_FRAME_LEN_MASK) 974 #define JME_RX_PAD_BYTES 10 975 976 #define JME_RD_RSS_HASH_VALUE 0xFFFFFFFF 977 978 #define JME_RD_RSS_HASH_MASK 0x00003F00 979 #define JME_RD_RSS_HASH_SHIFT 8 980 #define JME_RD_RSS_HASH_NONE 0x00000000 981 #define JME_RD_RSS_HASH_IPV4 0x00000100 982 #define JME_RD_RSS_HASH_IPV4TCP 0x00000200 983 #define JME_RD_RSS_HASH_IPV6 0x00000400 984 #define JME_RD_RSS_HASH_IPV6TCP 0x00001000 985 #define JME_RD_HASH_FN_NONE 0x00000000 986 #define JME_RD_HASH_FN_TOEPLITZ 0x00000001 987 988 #endif 989