1TEXT ainc(SB),$0 /* long ainc(long *); */ 2 MOVW R3, R4 3xincloop: 4 LWAR (R4), R3 5 ADD $1, R3 6 DCBT (R4) /* fix 405 errata cpu_210 */ 7 STWCCC R3, (R4) 8 BNE xincloop 9 RETURN 10 11TEXT adec(SB),$0 /* long adec(long *); */ 12 MOVW R3, R4 13xdecloop: 14 LWAR (R4), R3 15 ADD $-1, R3 16 DCBT (R4) /* fix 405 errata cpu_210 */ 17 STWCCC R3, (R4) 18 BNE xdecloop 19 RETURN 20 21TEXT loadlink(SB), $0 22 23 LWAR (R3), R3 24 RETURN 25 26TEXT storecond(SB), $0 27 28 MOVW val+4(FP), R4 29 DCBT (R3) /* fix 405 errata cpu_210 */ 30 STWCCC R4, (R3) 31 BNE storecondfail 32 MOVW $1, R3 33 RETURN 34storecondfail: 35 MOVW $0, R3 36 RETURN 37 38/* 39 * int cas32(u32int *p, u32int ov, u32int nv); 40 * int cas(uint *p, int ov, int nv); 41 * int casp(void **p, void *ov, void *nv); 42 * int casl(ulong *p, ulong ov, ulong nv); 43 */ 44 45TEXT cas32+0(SB),0,$0 46TEXT cas+0(SB),0,$0 47TEXT casp+0(SB),0,$0 48TEXT casl+0(SB),0,$0 49 MOVW ov+4(FP),R4 50 MOVW nv+8(FP),R8 51 LWAR (R3),R5 52 CMP R5,R4 53 BNE fail 54 DCBT (R3) /* fix 405 errata cpu_210 */ 55 STWCCC R8,(R3) 56 BNE fail1 57 MOVW $1,R3 58 RETURN 59fail: 60 DCBT (R3) /* fix 405 errata cpu_210 */ 61 STWCCC R5,(R3) /* give up exclusive access */ 62fail1: 63 MOVW R0,R3 64 RETURN 65 END 66