1units 2 branch 3 integer 4 floating point 5on 601 6 issue at most one per unit per cycle 7 eight entry instruction queue 8 can fill queue from cache in one clock cycle 9 loads from requested address to end of cache block 10pipeline 11 prefetch 12 includes ins. cache access cycles 13 decode 14 execute 15 writeback 16 17fpu 18 IQ[3210] → fpu buffer/decode [≥1 cycle] → execute 1 → execute 2 → writeback 19iu 20 IQ0/decode → buffer [if exec busy] → execute [hold for dependency] → 21 circulate in load/store 22 writeback 23bpu 24 IQ[3210] → decode/execute → writeback 25 26notes 27 address calculation must complete before stored value enters write buffer 28