1 /*
2 * Realtek RTL8110/8168/8169 Gigabit Ethernet Controllers.
3 * There are some magic register values used which are not described in
4 * any datasheet or driver but seem to be necessary.
5 * There are slight differences between the chips in the series so some
6 * tweaks may be needed.
7 *
8 * we use l1 and l2 cache ops; data must reach ram for dma.
9 */
10 #include "u.h"
11 #include "../port/lib.h"
12 #include "mem.h"
13 #include "dat.h"
14 #include "fns.h"
15 #include "io.h"
16 #include "../port/error.h"
17 #include "../port/netif.h"
18
19 #include "etherif.h"
20 #include "ethermii.h"
21
22 typedef struct Ctlr Ctlr;
23 typedef struct D D; /* Transmit/Receive Descriptor */
24 typedef struct Dtcc Dtcc;
25
26 enum {
27 Debug = 0, /* beware: > 1 interferes with correct operation */
28 };
29
30 enum { /* registers */
31 Idr0 = 0x00, /* MAC address */
32 Mar0 = 0x08, /* Multicast address */
33 Dtccr = 0x10, /* Dump Tally Counter Command */
34 Tnpds = 0x20, /* Transmit Normal Priority Descriptors */
35 Thpds = 0x28, /* Transmit High Priority Descriptors */
36 Flash = 0x30, /* Flash Memory Read/Write */
37 Erbcr = 0x34, /* Early Receive Byte Count */
38 Ersr = 0x36, /* Early Receive Status */
39 Cr = 0x37, /* Command Register */
40 Tppoll = 0x38, /* Transmit Priority Polling */
41 Imr = 0x3C, /* Interrupt Mask */
42 Isr = 0x3E, /* Interrupt Status */
43 Tcr = 0x40, /* Transmit Configuration */
44 Rcr = 0x44, /* Receive Configuration */
45 Tctr = 0x48, /* Timer Count */
46 Mpc = 0x4C, /* Missed Packet Counter */
47 Cr9346 = 0x50, /* 9346 Command Register */
48 Config0 = 0x51, /* Configuration Register 0 */
49 Config1 = 0x52, /* Configuration Register 1 */
50 Config2 = 0x53, /* Configuration Register 2 */
51 Config3 = 0x54, /* Configuration Register 3 */
52 Config4 = 0x55, /* Configuration Register 4 */
53 Config5 = 0x56, /* Configuration Register 5 */
54 Timerint = 0x58, /* Timer Interrupt */
55 Mulint = 0x5C, /* Multiple Interrupt Select */
56 Phyar = 0x60, /* PHY Access */
57 Tbicsr0 = 0x64, /* TBI Control and Status */
58 Tbianar = 0x68, /* TBI Auto-Negotiation Advertisment */
59 Tbilpar = 0x6A, /* TBI Auto-Negotiation Link Partner */
60 Phystatus = 0x6C, /* PHY Status */
61
62 Rms = 0xDA, /* Receive Packet Maximum Size */
63 Cplusc = 0xE0, /* C+ Command */
64 Coal = 0xE2, /* Interrupt Mitigation (Coalesce) */
65 Rdsar = 0xE4, /* Receive Descriptor Start Address */
66 Etx = 0xEC, /* 8169: Early Tx Threshold; 32-byte units */
67 Mtps = 0xEC, /* 8168: Maximum Transmit Packet Size */
68 };
69
70 enum { /* Dtccr */
71 Cmd = 0x00000008, /* Command */
72 };
73
74 enum { /* Cr */
75 Te = 0x04, /* Transmitter Enable */
76 Re = 0x08, /* Receiver Enable */
77 Rst = 0x10, /* Software Reset */
78 };
79
80 enum { /* Tppoll */
81 Fswint = 0x01, /* Forced Software Interrupt */
82 Npq = 0x40, /* Normal Priority Queue polling */
83 Hpq = 0x80, /* High Priority Queue polling */
84 };
85
86 enum { /* Imr/Isr */
87 Rok = 0x0001, /* Receive OK */
88 Rer = 0x0002, /* Receive Error */
89 Tok = 0x0004, /* Transmit OK */
90 Ter = 0x0008, /* Transmit Error */
91 Rdu = 0x0010, /* Receive Descriptor Unavailable */
92 Punlc = 0x0020, /* Packet Underrun or Link Change */
93 Fovw = 0x0040, /* Receive FIFO Overflow */
94 Tdu = 0x0080, /* Transmit Descriptor Unavailable */
95 Swint = 0x0100, /* Software Interrupt */
96 Timeout = 0x4000, /* Timer */
97 Serr = 0x8000, /* System Error */
98 };
99
100 enum { /* Tcr */
101 MtxdmaSHIFT = 8, /* Max. DMA Burst Size */
102 MtxdmaMASK = 0x00000700,
103 Mtxdmaunlimited = 0x00000700,
104 Acrc = 0x00010000, /* Append CRC (not) */
105 Lbk0 = 0x00020000, /* Loopback Test 0 */
106 Lbk1 = 0x00040000, /* Loopback Test 1 */
107 Ifg2 = 0x00080000, /* Interframe Gap 2 */
108 HwveridSHIFT = 23, /* Hardware Version ID */
109 HwveridMASK = 0x7C800000,
110 Macv01 = 0x00000000, /* RTL8169 */
111 Macv02 = 0x00800000, /* RTL8169S/8110S */
112 Macv03 = 0x04000000, /* RTL8169S/8110S */
113 Macv04 = 0x10000000, /* RTL8169SB/8110SB */
114 Macv05 = 0x18000000, /* RTL8169SC/8110SC */
115 Macv07 = 0x24800000, /* RTL8102e */
116 // Macv8103e = 0x24C00000,
117 Macv25 = 0x28000000, /* RTL8168D */
118 // Macv8168dp = 0x28800000,
119 // Macv8168e = 0x2C000000,
120 Macv11 = 0x30000000, /* RTL8168B/8111B */
121 Macv14 = 0x30800000, /* RTL8100E */
122 Macv13 = 0x34000000, /* RTL8101E */
123 Macv07a = 0x34800000, /* RTL8102e */
124 Macv12 = 0x38000000, /* RTL8169B/8111B */
125 // Macv8168spin3 = 0x38400000,
126 Macv15 = 0x38800000, /* RTL8100E */
127 Macv12a = 0x3c000000, /* RTL8169C/8111C */
128 // Macv19 = 0x3c000000, /* dup Macv12a: RTL8111c-gr */
129 // Macv8168cspin2 = 0x3c400000,
130 // Macv8168cp = 0x3c800000,
131 // Macv8139 = 0x60000000,
132 // Macv8139a = 0x70000000,
133 // Macv8139ag = 0x70800000,
134 // Macv8139b = 0x78000000,
135 // Macv8130 = 0x7C000000,
136 // Macv8139c = 0x74000000,
137 // Macv8139d = 0x74400000,
138 // Macv8139cplus = 0x74800000,
139 // Macv8101 = 0x74c00000,
140 // Macv8100 = 0x78800000,
141 // Macv8169_8110sbl= 0x7cc00000,
142 // Macv8169_8110sce= 0x98000000,
143 Ifg0 = 0x01000000, /* Interframe Gap 0 */
144 Ifg1 = 0x02000000, /* Interframe Gap 1 */
145 };
146
147 enum { /* Rcr */
148 Aap = 0x00000001, /* Accept All Packets */
149 Apm = 0x00000002, /* Accept Physical Match */
150 Am = 0x00000004, /* Accept Multicast */
151 Ab = 0x00000008, /* Accept Broadcast */
152 Ar = 0x00000010, /* Accept Runt */
153 Aer = 0x00000020, /* Accept Error */
154 Sel9356 = 0x00000040, /* 9356 EEPROM used */
155 MrxdmaSHIFT = 8, /* Max. DMA Burst Size */
156 MrxdmaMASK = 0x00000700,
157 Mrxdmaunlimited = 0x00000700,
158 RxfthSHIFT = 13, /* Receive Buffer Length */
159 RxfthMASK = 0x0000E000,
160 Rxfth256 = 0x00008000,
161 Rxfthnone = 0x0000E000,
162 Rer8 = 0x00010000, /* Accept Error Packets > 8 bytes */
163 MulERINT = 0x01000000, /* Multiple Early Interrupt Select */
164 };
165
166 enum { /* Cr9346 */
167 Eedo = 0x01, /* */
168 Eedi = 0x02, /* */
169 Eesk = 0x04, /* */
170 Eecs = 0x08, /* */
171 Eem0 = 0x40, /* Operating Mode */
172 Eem1 = 0x80,
173 };
174
175 enum { /* Phyar */
176 DataMASK = 0x0000FFFF, /* 16-bit GMII/MII Register Data */
177 DataSHIFT = 0,
178 RegaddrMASK = 0x001F0000, /* 5-bit GMII/MII Register Address */
179 RegaddrSHIFT = 16,
180 Flag = 0x80000000, /* */
181 };
182
183 enum { /* Phystatus */
184 Fd = 0x01, /* Full Duplex */
185 Linksts = 0x02, /* Link Status */
186 Speed10 = 0x04, /* */
187 Speed100 = 0x08, /* */
188 Speed1000 = 0x10, /* */
189 Rxflow = 0x20, /* */
190 Txflow = 0x40, /* */
191 Entbi = 0x80, /* */
192 };
193
194 enum { /* Cplusc */
195 Init1 = 0x0001, /* 8168 */
196 Mulrw = 0x0008, /* PCI Multiple R/W Enable */
197 Dac = 0x0010, /* PCI Dual Address Cycle Enable */
198 Rxchksum = 0x0020, /* Receive Checksum Offload Enable */
199 Rxvlan = 0x0040, /* Receive VLAN De-tagging Enable */
200 Pktcntoff = 0x0080, /* 8168, 8101 */
201 Endian = 0x0200, /* Endian Mode */
202 };
203
204 struct D {
205 u32int control;
206 u32int vlan;
207 u32int addrlo;
208 u32int addrhi;
209 };
210
211 enum { /* Transmit Descriptor control */
212 TxflMASK = 0x0000FFFF, /* Transmit Frame Length */
213 TxflSHIFT = 0,
214 Tcps = 0x00010000, /* TCP Checksum Offload */
215 Udpcs = 0x00020000, /* UDP Checksum Offload */
216 Ipcs = 0x00040000, /* IP Checksum Offload */
217 Lgsen = 0x08000000, /* TSO; WARNING: contains lark's vomit */
218 };
219
220 enum { /* Receive Descriptor control */
221 RxflMASK = 0x00001FFF, /* Receive Frame Length */
222 Tcpf = 0x00004000, /* TCP Checksum Failure */
223 Udpf = 0x00008000, /* UDP Checksum Failure */
224 Ipf = 0x00010000, /* IP Checksum Failure */
225 Pid0 = 0x00020000, /* Protocol ID0 */
226 Pid1 = 0x00040000, /* Protocol ID1 */
227 Crce = 0x00080000, /* CRC Error */
228 Runt = 0x00100000, /* Runt Packet */
229 Res = 0x00200000, /* Receive Error Summary */
230 Rwt = 0x00400000, /* Receive Watchdog Timer Expired */
231 Fovf = 0x00800000, /* FIFO Overflow */
232 Bovf = 0x01000000, /* Buffer Overflow */
233 Bar = 0x02000000, /* Broadcast Address Received */
234 Pam = 0x04000000, /* Physical Address Matched */
235 Mar = 0x08000000, /* Multicast Address Received */
236 };
237
238 enum { /* General Descriptor control */
239 Ls = 0x10000000, /* Last Segment Descriptor */
240 Fs = 0x20000000, /* First Segment Descriptor */
241 Eor = 0x40000000, /* End of Descriptor Ring */
242 Own = 0x80000000, /* Ownership: belongs to hw */
243 };
244
245 /*
246 */
247 enum { /* Ring sizes (<= 1024) */
248 Ntd = 1024, /* Transmit Ring */
249 /* at 1Gb/s, it only takes 12 ms. to fill a 1024-buffer ring */
250 Nrd = 1024, /* Receive Ring */
251 Nrb = 4096,
252
253 Mtu = ETHERMAXTU,
254 Mps = ROUNDUP(ETHERMAXTU+4, 128),
255 // Mps = Mtu + 8 + 14, /* if(mtu>ETHERMAXTU) */
256 };
257
258 struct Dtcc {
259 u64int txok;
260 u64int rxok;
261 u64int txer;
262 u32int rxer;
263 u16int misspkt;
264 u16int fae;
265 u32int tx1col;
266 u32int txmcol;
267 u64int rxokph;
268 u64int rxokbrd;
269 u32int rxokmu;
270 u16int txabt;
271 u16int txundrn;
272 };
273
274 enum { /* Variants */
275 Rtl8100e = (0x8136<<16)|0x10EC, /* RTL810[01]E: pci -e */
276 Rtl8169c = (0x0116<<16)|0x16EC, /* RTL8169C+ (USR997902) */
277 Rtl8169sc = (0x8167<<16)|0x10EC, /* RTL8169SC */
278 Rtl8168b = (0x8168<<16)|0x10EC, /* RTL8168B: pci-e */
279 Rtl8169 = (0x8169<<16)|0x10EC, /* RTL8169 */
280 /*
281 * trimslice is 10ec/8168 (8168b) Macv25 (8168D) but
282 * compulab says 8111dl.
283 * oui 0x732 (aaeon) phyno 1, macv = 0x28000000 phyv = 0x0002
284 */
285 };
286
287 struct Ctlr {
288 void* nic;
289 int port;
290 Pcidev* pcidev;
291 Ctlr* next;
292 Ether* ether; /* point back */
293 int active;
294
295 QLock alock; /* attach */
296 Lock ilock; /* init */
297 int init; /* */
298
299 int pciv; /* */
300 int macv; /* MAC version */
301 int phyv; /* PHY version */
302 int pcie; /* flag: pci-express device? */
303
304 uvlong mchash; /* multicast hash */
305
306 Mii* mii;
307
308 // Lock tlock; /* transmit */
309 Rendez trendez;
310 D* td; /* descriptor ring */
311 Block** tb; /* transmit buffers */
312 int ntd;
313
314 int tdh; /* head - producer index (host) */
315 int tdt; /* tail - consumer index (NIC) */
316 int ntdfree;
317 int ntq;
318
319 int nrb;
320
321 // Lock rlock; /* receive */
322 Rendez rrendez;
323 D* rd; /* descriptor ring */
324 Block** rb; /* receive buffers */
325 int nrd;
326
327 int rdh; /* head - producer index (NIC) */
328 int rdt; /* tail - consumer index (host) */
329 int nrdfree;
330
331 Lock reglock;
332 int tcr; /* transmit configuration register */
333 int rcr; /* receive configuration register */
334 int imr;
335 int isr; /* sw copy for kprocs */
336
337 QLock slock; /* statistics */
338 Dtcc* dtcc;
339 uint txdu;
340 uint tcpf;
341 uint udpf;
342 uint ipf;
343 uint fovf;
344 uint ierrs;
345 uint rer;
346 uint rdu;
347 uint punlc;
348 uint fovw;
349 uint mcast;
350 uint frag; /* partial packets; rb was too small */
351 };
352
353 static Ctlr* rtl8169ctlrhead;
354 static Ctlr* rtl8169ctlrtail;
355
356 static Lock rblock; /* free receive Blocks */
357 static Block* rbpool;
358
359 #define csr8r(c, r) (*((uchar *) ((c)->nic)+(r)))
360 #define csr16r(c, r) (*((u16int *)((c)->nic)+((r)/2)))
361 #define csr32p(c, r) ((u32int *) ((c)->nic)+((r)/4))
362 #define csr32r(c, r) (*csr32p(c, r))
363
364 #define csr8w(c, r, b) (*((uchar *) ((c)->nic)+(r)) = (b), coherence())
365 #define csr16w(c, r, w) (*((u16int *)((c)->nic)+((r)/2)) = (w), coherence())
366 #define csr32w(c, r, v) (*csr32p(c, r) = (v), coherence())
367
368 static int
rtl8169miimir(Mii * mii,int pa,int ra)369 rtl8169miimir(Mii* mii, int pa, int ra)
370 {
371 uint r;
372 int timeo;
373 Ctlr *ctlr;
374
375 if(pa != 1)
376 return -1;
377 ctlr = mii->ctlr;
378 r = (ra<<16) & RegaddrMASK;
379 csr32w(ctlr, Phyar, r);
380 delay(1);
381 for(timeo = 0; timeo < 2000; timeo++){
382 if((r = csr32r(ctlr, Phyar)) & Flag)
383 break;
384 microdelay(100);
385 }
386 if(!(r & Flag))
387 return -1;
388
389 return (r & DataMASK)>>DataSHIFT;
390 }
391
392 static int
rtl8169miimiw(Mii * mii,int pa,int ra,int data)393 rtl8169miimiw(Mii* mii, int pa, int ra, int data)
394 {
395 uint r;
396 int timeo;
397 Ctlr *ctlr;
398
399 if(pa != 1)
400 return -1;
401 ctlr = mii->ctlr;
402 r = Flag|((ra<<16) & RegaddrMASK)|((data<<DataSHIFT) & DataMASK);
403 csr32w(ctlr, Phyar, r);
404 delay(1);
405 for(timeo = 0; timeo < 2000; timeo++){
406 if(!((r = csr32r(ctlr, Phyar)) & Flag))
407 break;
408 microdelay(100);
409 }
410 if(r & Flag)
411 return -1;
412
413 return 0;
414 }
415
416 static int
rtl8169mii(Ctlr * ctlr)417 rtl8169mii(Ctlr* ctlr)
418 {
419 MiiPhy *phy;
420
421 /*
422 * Link management.
423 */
424 if((ctlr->mii = malloc(sizeof(Mii))) == nil)
425 return -1;
426 ctlr->mii->mir = rtl8169miimir;
427 ctlr->mii->miw = rtl8169miimiw;
428 ctlr->mii->ctlr = ctlr;
429
430 /*
431 * Get rev number out of Phyidr2 so can config properly.
432 * There's probably more special stuff for Macv0[234] needed here.
433 */
434 ilock(&ctlr->reglock);
435 ctlr->phyv = rtl8169miimir(ctlr->mii, 1, Phyidr2) & 0x0F;
436 if(ctlr->macv == Macv02){
437 csr8w(ctlr, 0x82, 1); /* magic */
438 rtl8169miimiw(ctlr->mii, 1, 0x0B, 0x0000); /* magic */
439 }
440
441 if(mii(ctlr->mii, (1<<1)) == 0 || (phy = ctlr->mii->curphy) == nil){
442 iunlock(&ctlr->reglock);
443 free(ctlr->mii);
444 ctlr->mii = nil;
445 return -1;
446 }
447 print("rtl8169: oui %#ux phyno %d, macv = %#8.8ux phyv = %#4.4ux\n",
448 phy->oui, phy->phyno, ctlr->macv, ctlr->phyv);
449
450 miiane(ctlr->mii, ~0, ~0, ~0);
451 iunlock(&ctlr->reglock);
452
453 return 0;
454 }
455
456 static Block*
rballoc(void)457 rballoc(void)
458 {
459 Block *bp;
460
461 ilock(&rblock);
462 if((bp = rbpool) != nil){
463 rbpool = bp->next;
464 bp->next = nil;
465 _xinc(&bp->ref); /* prevent bp from being freed */
466 }
467 iunlock(&rblock);
468 return bp;
469 }
470
471 static void
rbfree(Block * bp)472 rbfree(Block *bp)
473 {
474 bp->wp = bp->rp = bp->lim - Mps;
475 bp->flag &= ~(Bipck | Budpck | Btcpck | Bpktck);
476
477 ilock(&rblock);
478 bp->next = rbpool;
479 rbpool = bp;
480 iunlock(&rblock);
481 }
482
483 static void
rtl8169promiscuous(void * arg,int on)484 rtl8169promiscuous(void* arg, int on)
485 {
486 Ether *edev;
487 Ctlr * ctlr;
488
489 edev = arg;
490 ctlr = edev->ctlr;
491 ilock(&ctlr->ilock);
492 ilock(&ctlr->reglock);
493
494 if(on)
495 ctlr->rcr |= Aap;
496 else
497 ctlr->rcr &= ~Aap;
498 csr32w(ctlr, Rcr, ctlr->rcr);
499 iunlock(&ctlr->reglock);
500 iunlock(&ctlr->ilock);
501 }
502
503 enum {
504 /* everyone else uses 0x04c11db7, but they both produce the same crc */
505 Etherpolybe = 0x04c11db6,
506 Bytemask = (1<<8) - 1,
507 };
508
509 static ulong
ethercrcbe(uchar * addr,long len)510 ethercrcbe(uchar *addr, long len)
511 {
512 int i, j;
513 ulong c, crc, carry;
514
515 crc = ~0UL;
516 for (i = 0; i < len; i++) {
517 c = addr[i];
518 for (j = 0; j < 8; j++) {
519 carry = ((crc & (1UL << 31))? 1: 0) ^ (c & 1);
520 crc <<= 1;
521 c >>= 1;
522 if (carry)
523 crc = (crc ^ Etherpolybe) | carry;
524 }
525 }
526 return crc;
527 }
528
529 static ulong
swabl(ulong l)530 swabl(ulong l)
531 {
532 return l>>24 | (l>>8) & (Bytemask<<8) |
533 (l<<8) & (Bytemask<<16) | l<<24;
534 }
535
536 static void
rtl8169multicast(void * ether,uchar * eaddr,int add)537 rtl8169multicast(void* ether, uchar *eaddr, int add)
538 {
539 Ether *edev;
540 Ctlr *ctlr;
541
542 if (!add)
543 return; /* ok to keep receiving on old mcast addrs */
544
545 edev = ether;
546 ctlr = edev->ctlr;
547 ilock(&ctlr->ilock);
548 ilock(&ctlr->reglock);
549
550 ctlr->mchash |= 1ULL << (ethercrcbe(eaddr, Eaddrlen) >> 26);
551
552 ctlr->rcr |= Am;
553 csr32w(ctlr, Rcr, ctlr->rcr);
554
555 /* pci-e variants reverse the order of the hash byte registers */
556 if (ctlr->pcie) {
557 csr32w(ctlr, Mar0, swabl(ctlr->mchash>>32));
558 csr32w(ctlr, Mar0+4, swabl(ctlr->mchash));
559 } else {
560 csr32w(ctlr, Mar0, ctlr->mchash);
561 csr32w(ctlr, Mar0+4, ctlr->mchash>>32);
562 }
563
564 iunlock(&ctlr->reglock);
565 iunlock(&ctlr->ilock);
566 }
567
568 static long
rtl8169ifstat(Ether * edev,void * a,long n,ulong offset)569 rtl8169ifstat(Ether* edev, void* a, long n, ulong offset)
570 {
571 char *p;
572 Ctlr *ctlr;
573 Dtcc *dtcc;
574 int i, l, r, timeo;
575
576 ctlr = edev->ctlr;
577 qlock(&ctlr->slock);
578
579 p = nil;
580 if(waserror()){
581 qunlock(&ctlr->slock);
582 free(p);
583 nexterror();
584 }
585
586 /* copy hw statistics into ctlr->dtcc */
587 dtcc = ctlr->dtcc;
588 allcache->invse(dtcc, sizeof *dtcc);
589 ilock(&ctlr->reglock);
590 csr32w(ctlr, Dtccr+4, 0);
591 csr32w(ctlr, Dtccr, PCIWADDR(dtcc)|Cmd); /* initiate dma? */
592 for(timeo = 0; timeo < 1000; timeo++){
593 if(!(csr32r(ctlr, Dtccr) & Cmd))
594 break;
595 delay(1);
596 }
597 iunlock(&ctlr->reglock);
598 if(csr32r(ctlr, Dtccr) & Cmd)
599 error(Eio);
600
601 edev->oerrs = dtcc->txer;
602 edev->crcs = dtcc->rxer;
603 edev->frames = dtcc->fae;
604 edev->buffs = dtcc->misspkt;
605 edev->overflows = ctlr->txdu + ctlr->rdu;
606
607 if(n == 0){
608 qunlock(&ctlr->slock);
609 poperror();
610 return 0;
611 }
612
613 if((p = malloc(READSTR)) == nil)
614 error(Enomem);
615
616 l = snprint(p, READSTR, "TxOk: %llud\n", dtcc->txok);
617 l += snprint(p+l, READSTR-l, "RxOk: %llud\n", dtcc->rxok);
618 l += snprint(p+l, READSTR-l, "TxEr: %llud\n", dtcc->txer);
619 l += snprint(p+l, READSTR-l, "RxEr: %ud\n", dtcc->rxer);
620 l += snprint(p+l, READSTR-l, "MissPkt: %ud\n", dtcc->misspkt);
621 l += snprint(p+l, READSTR-l, "FAE: %ud\n", dtcc->fae);
622 l += snprint(p+l, READSTR-l, "Tx1Col: %ud\n", dtcc->tx1col);
623 l += snprint(p+l, READSTR-l, "TxMCol: %ud\n", dtcc->txmcol);
624 l += snprint(p+l, READSTR-l, "RxOkPh: %llud\n", dtcc->rxokph);
625 l += snprint(p+l, READSTR-l, "RxOkBrd: %llud\n", dtcc->rxokbrd);
626 l += snprint(p+l, READSTR-l, "RxOkMu: %ud\n", dtcc->rxokmu);
627 l += snprint(p+l, READSTR-l, "TxAbt: %ud\n", dtcc->txabt);
628 l += snprint(p+l, READSTR-l, "TxUndrn: %ud\n", dtcc->txundrn);
629
630 l += snprint(p+l, READSTR-l, "txdu: %ud\n", ctlr->txdu);
631 l += snprint(p+l, READSTR-l, "tcpf: %ud\n", ctlr->tcpf);
632 l += snprint(p+l, READSTR-l, "udpf: %ud\n", ctlr->udpf);
633 l += snprint(p+l, READSTR-l, "ipf: %ud\n", ctlr->ipf);
634 l += snprint(p+l, READSTR-l, "fovf: %ud\n", ctlr->fovf);
635 l += snprint(p+l, READSTR-l, "ierrs: %ud\n", ctlr->ierrs);
636 l += snprint(p+l, READSTR-l, "rer: %ud\n", ctlr->rer);
637 l += snprint(p+l, READSTR-l, "rdu: %ud\n", ctlr->rdu);
638 l += snprint(p+l, READSTR-l, "punlc: %ud\n", ctlr->punlc);
639 l += snprint(p+l, READSTR-l, "fovw: %ud\n", ctlr->fovw);
640
641 l += snprint(p+l, READSTR-l, "tcr: %#8.8ux\n", ctlr->tcr);
642 l += snprint(p+l, READSTR-l, "rcr: %#8.8ux\n", ctlr->rcr);
643 l += snprint(p+l, READSTR-l, "multicast: %ud\n", ctlr->mcast);
644
645 if(ctlr->mii != nil && ctlr->mii->curphy != nil){
646 l += snprint(p+l, READSTR, "phy: ");
647 for(i = 0; i < NMiiPhyr; i++){
648 if(i && ((i & 0x07) == 0))
649 l += snprint(p+l, READSTR-l, "\n ");
650 r = miimir(ctlr->mii, i);
651 l += snprint(p+l, READSTR-l, " %4.4ux", r);
652 }
653 snprint(p+l, READSTR-l, "\n");
654 }
655
656 n = readstr(offset, a, n, p);
657
658 qunlock(&ctlr->slock);
659 poperror();
660 free(p);
661
662 return n;
663 }
664
665 static void
rtl8169halt(Ctlr * ctlr)666 rtl8169halt(Ctlr* ctlr)
667 {
668 ilock(&ctlr->reglock);
669 csr32w(ctlr, Timerint, 0);
670 csr8w(ctlr, Cr, 0);
671 csr16w(ctlr, Imr, 0);
672 csr16w(ctlr, Isr, ~0);
673 iunlock(&ctlr->reglock);
674 }
675
676 static int
rtl8169reset(Ctlr * ctlr)677 rtl8169reset(Ctlr* ctlr)
678 {
679 u32int r;
680 int timeo;
681
682 /*
683 * Soft reset the controller.
684 */
685 ilock(&ctlr->reglock);
686 csr8w(ctlr, Cr, Rst);
687 for(r = timeo = 0; timeo < 1000; timeo++){
688 r = csr8r(ctlr, Cr);
689 if(!(r & Rst))
690 break;
691 delay(1);
692 }
693 iunlock(&ctlr->reglock);
694
695 rtl8169halt(ctlr);
696
697 if(r & Rst)
698 return -1;
699 return 0;
700 }
701
702 static void
rtl8169shutdown(Ether * ether)703 rtl8169shutdown(Ether *ether)
704 {
705 rtl8169reset(ether->ctlr);
706 }
707
708 static int
rtl8169replenish(Ether * edev)709 rtl8169replenish(Ether *edev)
710 {
711 int rdt;
712 Block *bp;
713 Ctlr *ctlr;
714 D *d;
715
716 ctlr = edev->ctlr;
717 if (ctlr->nrd == 0) {
718 iprint("rtl8169replenish: not yet initialised\n");
719 return -1;
720 }
721 rdt = ctlr->rdt;
722 assert(ctlr->rb);
723 assert(ctlr->rd);
724 while(NEXT(rdt, ctlr->nrd) != ctlr->rdh){
725 d = &ctlr->rd[rdt];
726 if (d == nil)
727 panic("rtl8169replenish: nil ctlr->rd[%d]", rdt);
728 if (d->control & Own) { /* ctlr owns it? shouldn't happen */
729 iprint("replenish: descriptor owned by hw\n");
730 break;
731 }
732 if(ctlr->rb[rdt] == nil){
733 bp = rballoc();
734 if(bp == nil){
735 iprint("rtl8169: no available buffers\n");
736 break;
737 }
738 ctlr->rb[rdt] = bp;
739 d->addrhi = 0;
740 coherence();
741 d->addrlo = PCIWADDR(bp->rp);
742 coherence();
743 } else
744 iprint("8169: replenish: rx overrun\n");
745 d->control = (d->control & ~RxflMASK) | Mps | Own;
746 coherence();
747
748 rdt = NEXT(rdt, ctlr->nrd);
749 ctlr->nrdfree++;
750 }
751 ctlr->rdt = rdt;
752 coherence();
753 return 0;
754 }
755
756 static void
ckrderrs(Ctlr * ctlr,Block * bp,ulong control)757 ckrderrs(Ctlr *ctlr, Block *bp, ulong control)
758 {
759 if(control & Fovf)
760 ctlr->fovf++;
761 if(control & Mar)
762 ctlr->mcast++;
763
764 switch(control & (Pid1|Pid0)){
765 case Pid0:
766 if(control & Tcpf){
767 iprint("8169: bad tcp checksum\n");
768 ctlr->tcpf++;
769 break;
770 }
771 bp->flag |= Btcpck;
772 break;
773 case Pid1:
774 if(control & Udpf){
775 iprint("8169: bad udp checksum\n");
776 ctlr->udpf++;
777 break;
778 }
779 bp->flag |= Budpck;
780 break;
781 case Pid1|Pid0:
782 if(control & Ipf){
783 iprint("8169: bad ip checksum\n");
784 ctlr->ipf++;
785 break;
786 }
787 bp->flag |= Bipck;
788 break;
789 }
790 }
791
792 static void
badpkt(Ether * edev,int rdh,ulong control)793 badpkt(Ether *edev, int rdh, ulong control)
794 {
795 Ctlr *ctlr;
796
797 ctlr = edev->ctlr;
798 /* Res is only valid if Fs is set */
799 if(control & Res)
800 iprint("8169: rcv error; d->control %#.8lux\n", control);
801 else if (control == 0) { /* buggered? */
802 if (edev->link)
803 iprint("8169: rcv: d->control==0 (wtf?)\n");
804 } else {
805 ctlr->frag++;
806 iprint("8169: rcv'd frag; d->control %#.8lux\n", control);
807 }
808 if (ctlr->rb[rdh])
809 freeb(ctlr->rb[rdh]);
810 }
811
812 void
qpkt(Ether * edev,int rdh,ulong control)813 qpkt(Ether *edev, int rdh, ulong control)
814 {
815 int len;
816 Block *bp;
817 Ctlr *ctlr;
818
819 ctlr = edev->ctlr;
820 len = (control & RxflMASK) - 4;
821 if ((uint)len > Mps)
822 if (len < 0)
823 panic("8169: received pkt non-existent");
824 else if (len > Mps)
825 panic("8169: received pkt too big");
826 bp = ctlr->rb[rdh];
827 bp->wp = bp->rp + len;
828 bp->next = nil;
829
830 allcache->invse(bp->rp, len); /* clear any stale cached packet */
831 ckrderrs(ctlr, bp, control);
832 etheriq(edev, bp, 1);
833
834 if(Debug > 1)
835 iprint("R%d ", len);
836 }
837
838 static int
pktstoread(void * v)839 pktstoread(void* v)
840 {
841 Ctlr *ctlr = v;
842
843 return ctlr->isr & (Fovw|Rdu|Rer|Rok) &&
844 !(ctlr->rd[ctlr->rdh].control & Own);
845 }
846
847 static void
rproc(void * arg)848 rproc(void* arg)
849 {
850 int rdh;
851 ulong control;
852 Ctlr *ctlr;
853 D *rd;
854 Ether *edev;
855
856 edev = arg;
857 ctlr = edev->ctlr;
858 for(;;){
859 /* wait for next interrupt */
860 ilock(&ctlr->reglock);
861 ctlr->imr |= Fovw|Rdu|Rer|Rok;
862 csr16w(ctlr, Imr, ctlr->imr);
863 iunlock(&ctlr->reglock);
864
865 sleep(&ctlr->rrendez, pktstoread, ctlr);
866
867 /* clear saved isr bits */
868 ilock(&ctlr->reglock);
869 ctlr->isr &= ~(Fovw|Rdu|Rer|Rok);
870 iunlock(&ctlr->reglock);
871
872 rdh = ctlr->rdh;
873 for (rd = &ctlr->rd[rdh]; !(rd->control & Own);
874 rd = &ctlr->rd[rdh]){
875 control = rd->control;
876 if((control & (Fs|Ls|Res)) == (Fs|Ls))
877 qpkt(edev, rdh, control);
878 else
879 badpkt(edev, rdh, control);
880 ctlr->rb[rdh] = nil;
881 coherence();
882 rd->control &= Eor;
883 coherence();
884
885 ctlr->nrdfree--;
886 rdh = NEXT(rdh, ctlr->nrd);
887 if(ctlr->nrdfree < ctlr->nrd/2) {
888 /* replenish reads ctlr->rdh */
889 ctlr->rdh = rdh;
890 rtl8169replenish(edev);
891 /* if replenish called restart, rdh is reset */
892 rdh = ctlr->rdh;
893 }
894 }
895 ctlr->rdh = rdh;
896 }
897 }
898
899 static int
pktstosend(void * v)900 pktstosend(void* v)
901 {
902 Ether *edev = v;
903 Ctlr *ctlr = edev->ctlr;
904
905 return ctlr->isr & (Ter|Tok) &&
906 !(ctlr->td[ctlr->tdh].control & Own) && edev->link;
907 }
908
909 static void
tproc(void * arg)910 tproc(void* arg)
911 {
912 int x, len;
913 Block *bp;
914 Ctlr *ctlr;
915 D *d;
916 Ether *edev;
917
918 edev = arg;
919 ctlr = edev->ctlr;
920 for(;;){
921 /* wait for next interrupt */
922 ilock(&ctlr->reglock);
923 ctlr->imr |= Ter|Tok;
924 csr16w(ctlr, Imr, ctlr->imr);
925 iunlock(&ctlr->reglock);
926
927 sleep(&ctlr->trendez, pktstosend, edev);
928
929 /* clear saved isr bits */
930 ilock(&ctlr->reglock);
931 ctlr->isr &= ~(Ter|Tok);
932 iunlock(&ctlr->reglock);
933
934 /* reclaim transmitted Blocks */
935 for(x = ctlr->tdh; ctlr->ntq > 0; x = NEXT(x, ctlr->ntd)){
936 d = &ctlr->td[x];
937 if(d == nil || d->control & Own)
938 break;
939
940 /*
941 * Free it up.
942 * Need to clean the descriptor here? Not really.
943 * Simple freeb for now (no chain and freeblist).
944 * Use ntq count for now.
945 */
946 freeb(ctlr->tb[x]);
947 ctlr->tb[x] = nil;
948 d->control &= Eor;
949 coherence();
950
951 ctlr->ntq--;
952 }
953 ctlr->tdh = x;
954
955 if (ctlr->ntq > 0)
956 csr8w(ctlr, Tppoll, Npq); /* kick xmiter to keep it going */
957 /* copy as much of my output q as possible into output ring */
958 x = ctlr->tdt;
959 while(ctlr->ntq < (ctlr->ntd-1)){
960 if((bp = qget(edev->oq)) == nil)
961 break;
962
963 /* make sure the whole packet is in ram */
964 len = BLEN(bp);
965 allcache->wbse(bp->rp, len);
966
967 d = &ctlr->td[x];
968 assert(d);
969 assert(!(d->control & Own));
970 d->addrhi = 0;
971 d->addrlo = PCIWADDR(bp->rp);
972 ctlr->tb[x] = bp;
973 coherence();
974 d->control = (d->control & ~TxflMASK) |
975 Own | Fs | Ls | len;
976 coherence();
977
978 if(Debug > 1)
979 iprint("T%d ", len);
980
981 x = NEXT(x, ctlr->ntd);
982 ctlr->ntq++;
983
984 ctlr->tdt = x;
985 coherence();
986 csr8w(ctlr, Tppoll, Npq); /* kick xmiter again */
987 }
988 if(x != ctlr->tdt){ /* added new packet(s)? */
989 ctlr->tdt = x;
990 coherence();
991 csr8w(ctlr, Tppoll, Npq);
992 }
993 else if(ctlr->ntq >= (ctlr->ntd-1))
994 ctlr->txdu++;
995 }
996 }
997
998 static int
rtl8169init(Ether * edev)999 rtl8169init(Ether* edev)
1000 {
1001 u32int r;
1002 Ctlr *ctlr;
1003 ushort cplusc;
1004
1005 ctlr = edev->ctlr;
1006 ilock(&ctlr->ilock);
1007 rtl8169reset(ctlr);
1008
1009 ilock(&ctlr->reglock);
1010 switch(ctlr->pciv){
1011 case Rtl8169sc:
1012 csr8w(ctlr, Cr, 0);
1013 break;
1014 case Rtl8168b:
1015 case Rtl8169c:
1016 /* 8168b manual says set c+ reg first, then command */
1017 csr16w(ctlr, Cplusc, 0x2000); /* magic */
1018 csr8w(ctlr, Cr, 0);
1019 break;
1020 }
1021
1022 /*
1023 * MAC Address is not settable on some (all?) chips.
1024 * Must put chip into config register write enable mode.
1025 */
1026 csr8w(ctlr, Cr9346, Eem1|Eem0);
1027
1028 /*
1029 * Transmitter.
1030 */
1031 memset(ctlr->td, 0, sizeof(D)*ctlr->ntd);
1032 ctlr->tdh = ctlr->tdt = 0;
1033 ctlr->ntq = 0;
1034 ctlr->td[ctlr->ntd-1].control = Eor;
1035
1036 /*
1037 * Receiver.
1038 * Need to do something here about the multicast filter.
1039 */
1040 memset(ctlr->rd, 0, sizeof(D)*ctlr->nrd);
1041 ctlr->nrdfree = ctlr->rdh = ctlr->rdt = 0;
1042 ctlr->rd[ctlr->nrd-1].control = Eor;
1043
1044 rtl8169replenish(edev);
1045
1046 switch(ctlr->pciv){
1047 default:
1048 ctlr->rcr = Rxfthnone|Mrxdmaunlimited|Ab|Apm;
1049 break;
1050 case Rtl8168b:
1051 case Rtl8169c:
1052 ctlr->rcr = Rxfthnone|6<<MrxdmaSHIFT|Ab|Apm; /* DMA max 1024 */
1053 break;
1054 }
1055
1056 /*
1057 * Setting Mulrw in Cplusc disables the Tx/Rx DMA burst
1058 * settings in Tcr/Rcr; the (1<<14) is magic.
1059 */
1060 cplusc = csr16r(ctlr, Cplusc) & ~(1<<14);
1061 switch(ctlr->pciv){
1062 case Rtl8168b:
1063 case Rtl8169c:
1064 cplusc |= Pktcntoff | Init1;
1065 break;
1066 }
1067 cplusc |= /*Rxchksum|*/Mulrw;
1068 switch(ctlr->macv){
1069 default:
1070 panic("ether8169: unknown macv %#08ux for vid %#ux did %#ux",
1071 ctlr->macv, ctlr->pcidev->vid, ctlr->pcidev->did);
1072 case Macv01:
1073 break;
1074 case Macv02:
1075 case Macv03:
1076 cplusc |= 1<<14; /* magic */
1077 break;
1078 case Macv05:
1079 /*
1080 * This is interpreted from clearly bogus code
1081 * in the manufacturer-supplied driver, it could
1082 * be wrong. Untested.
1083 */
1084 r = csr8r(ctlr, Config2) & 0x07;
1085 if(r == 0x01) /* 66MHz PCI */
1086 csr32w(ctlr, 0x7C, 0x0007FFFF); /* magic */
1087 else
1088 csr32w(ctlr, 0x7C, 0x0007FF00); /* magic */
1089 pciclrmwi(ctlr->pcidev);
1090 break;
1091 case Macv13:
1092 /*
1093 * This is interpreted from clearly bogus code
1094 * in the manufacturer-supplied driver, it could
1095 * be wrong. Untested.
1096 */
1097 pcicfgw8(ctlr->pcidev, 0x68, 0x00); /* magic */
1098 pcicfgw8(ctlr->pcidev, 0x69, 0x08); /* magic */
1099 break;
1100 case Macv04:
1101 case Macv07:
1102 case Macv07a:
1103 case Macv11:
1104 case Macv12:
1105 case Macv12a:
1106 case Macv14:
1107 case Macv15:
1108 case Macv25:
1109 break;
1110 }
1111
1112 /*
1113 * Enable receiver/transmitter.
1114 * Need to do this first or some of the settings below
1115 * won't take.
1116 */
1117 switch(ctlr->pciv){
1118 default:
1119 csr8w(ctlr, Cr, Te|Re);
1120 csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited);
1121 csr32w(ctlr, Rcr, ctlr->rcr);
1122 break;
1123 case Rtl8169sc:
1124 case Rtl8168b:
1125 break;
1126 }
1127 ctlr->mchash = 0;
1128 csr32w(ctlr, Mar0, 0);
1129 csr32w(ctlr, Mar0+4, 0);
1130
1131 /*
1132 * Interrupts.
1133 * Disable Tdu for now, the transmit routine will tidy.
1134 * Tdu means the NIC ran out of descriptors to send (i.e., the
1135 * output ring is empty), so it doesn't really need to ever be on.
1136 *
1137 * The timer runs at the PCI(-E) clock frequency, 125MHz for PCI-E,
1138 * presumably 66MHz for PCI. Thus the units for PCI-E controllers
1139 * (e.g., 8168) are 8ns, and only the buggy 8168 seems to need to use
1140 * timeouts to keep from stalling.
1141 */
1142 csr32w(ctlr, Tctr, 0);
1143 /* Tok makes the whole system run faster */
1144 ctlr->imr = Serr|Fovw|Punlc|Rdu|Ter|Tok|Rer|Rok;
1145 switch(ctlr->pciv){
1146 case Rtl8169sc:
1147 case Rtl8168b:
1148 /* alleged workaround for rx fifo overflow on 8168[bd] */
1149 ctlr->imr &= ~Rdu;
1150 break;
1151 }
1152 csr16w(ctlr, Imr, ctlr->imr);
1153
1154 /*
1155 * Clear missed-packet counter;
1156 * clear early transmit threshold value;
1157 * set the descriptor ring base addresses;
1158 * set the maximum receive packet size;
1159 * no early-receive interrupts.
1160 *
1161 * note: the maximum rx size is a filter. the size of the buffer
1162 * in the descriptor ring is still honored. we will toss >Mtu
1163 * packets because they've been fragmented into multiple
1164 * rx buffers.
1165 */
1166 csr32w(ctlr, Mpc, 0);
1167 if (ctlr->pcie)
1168 csr8w(ctlr, Mtps, Mps / 128);
1169 else
1170 csr8w(ctlr, Etx, 0x3f); /* max; no early transmission */
1171 csr32w(ctlr, Tnpds+4, 0);
1172 csr32w(ctlr, Tnpds, PCIWADDR(ctlr->td));
1173 csr32w(ctlr, Rdsar+4, 0);
1174 csr32w(ctlr, Rdsar, PCIWADDR(ctlr->rd));
1175 csr16w(ctlr, Rms, 2048); /* was Mps; see above comment */
1176 r = csr16r(ctlr, Mulint) & 0xF000; /* no early rx interrupts */
1177 csr16w(ctlr, Mulint, r);
1178 csr16w(ctlr, Cplusc, cplusc);
1179 csr16w(ctlr, Coal, 0);
1180
1181 /*
1182 * Set configuration.
1183 */
1184 switch(ctlr->pciv){
1185 case Rtl8169sc:
1186 csr8w(ctlr, Cr, Te|Re);
1187 csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited);
1188 csr32w(ctlr, Rcr, ctlr->rcr);
1189 break;
1190 case Rtl8168b:
1191 case Rtl8169c:
1192 csr16w(ctlr, Cplusc, 0x2000); /* magic */
1193 csr8w(ctlr, Cr, Te|Re);
1194 csr32w(ctlr, Tcr, Ifg1|Ifg0|6<<MtxdmaSHIFT); /* DMA max 1024 */
1195 csr32w(ctlr, Rcr, ctlr->rcr);
1196 break;
1197 }
1198 ctlr->tcr = csr32r(ctlr, Tcr);
1199 csr8w(ctlr, Cr9346, 0);
1200
1201 iunlock(&ctlr->reglock);
1202 iunlock(&ctlr->ilock);
1203
1204 // rtl8169mii(ctlr);
1205
1206 return 0;
1207 }
1208
1209 static void
rtl8169attach(Ether * edev)1210 rtl8169attach(Ether* edev)
1211 {
1212 int timeo, s, i;
1213 char name[KNAMELEN];
1214 Block *bp;
1215 Ctlr *ctlr;
1216
1217 ctlr = edev->ctlr;
1218 s = splhi();
1219 qlock(&ctlr->alock);
1220 if(ctlr->init || waserror()) {
1221 qunlock(&ctlr->alock);
1222 splx(s);
1223 return;
1224 }
1225 ctlr->td = ucallocalign(sizeof(D)*Ntd, 256, 0);
1226 ctlr->tb = malloc(Ntd*sizeof(Block*));
1227 ctlr->ntd = Ntd;
1228
1229 ctlr->rd = ucallocalign(sizeof(D)*Nrd, 256, 0);
1230 ctlr->rb = malloc(Nrd*sizeof(Block*));
1231 ctlr->nrd = Nrd;
1232
1233 ctlr->dtcc = mallocalign(sizeof(Dtcc), 64, 0, 0);
1234 if(waserror()){
1235 free(ctlr->td);
1236 free(ctlr->tb);
1237 free(ctlr->rd);
1238 free(ctlr->rb);
1239 free(ctlr->dtcc);
1240 nexterror();
1241 }
1242 if(ctlr->td == nil || ctlr->tb == nil || ctlr->rd == nil ||
1243 ctlr->rb == nil || ctlr->dtcc == nil)
1244 error(Enomem);
1245
1246 /* allocate private receive-buffer pool */
1247 ctlr->nrb = Nrb;
1248 for(i = 0; i < Nrb; i++){
1249 if((bp = allocb(Mps)) == nil)
1250 error(Enomem);
1251 bp->free = rbfree;
1252 freeb(bp);
1253 }
1254
1255 rtl8169init(edev);
1256 ctlr->init = 1;
1257 qunlock(&ctlr->alock);
1258 splx(s);
1259 poperror(); /* free */
1260 poperror(); /* qunlock */
1261
1262 /* signal secondary cpus that l1 ptes are stable */
1263 l1ptstable.word = 1;
1264 allcache->wbse(&l1ptstable, sizeof l1ptstable);
1265
1266 s = spllo();
1267 /* Don't wait long for link to be ready. */
1268 for(timeo = 0; timeo < 50 && miistatus(ctlr->mii) != 0; timeo++)
1269 // tsleep(&up->sleep, return0, 0, 100); /* fewer miistatus msgs */
1270 delay(100);
1271
1272 while (!edev->link)
1273 tsleep(&up->sleep, return0, 0, 10);
1274 splx(s);
1275
1276 snprint(name, KNAMELEN, "#l%drproc", edev->ctlrno);
1277 kproc(name, rproc, edev);
1278
1279 snprint(name, KNAMELEN, "#l%dtproc", edev->ctlrno);
1280 kproc(name, tproc, edev);
1281 }
1282
1283 /* call with ctlr->reglock held */
1284 static void
rtl8169link(Ether * edev)1285 rtl8169link(Ether* edev)
1286 {
1287 uint r;
1288 int limit;
1289 Ctlr *ctlr;
1290
1291 ctlr = edev->ctlr;
1292
1293 if(!((r = csr8r(ctlr, Phystatus)) & Linksts)){
1294 if (edev->link) {
1295 edev->link = 0;
1296 csr8w(ctlr, Cr, Re);
1297 iprint("#l%d: link down\n", edev->ctlrno);
1298 }
1299 return;
1300 }
1301 if (edev->link == 0) {
1302 edev->link = 1;
1303 csr8w(ctlr, Cr, Te|Re);
1304 iprint("#l%d: link up\n", edev->ctlrno);
1305 }
1306 limit = 256*1024;
1307 if(r & Speed10){
1308 edev->mbps = 10;
1309 limit = 65*1024;
1310 } else if(r & Speed100)
1311 edev->mbps = 100;
1312 else if(r & Speed1000)
1313 edev->mbps = 1000;
1314
1315 if(edev->oq != nil)
1316 qsetlimit(edev->oq, limit);
1317 }
1318
1319 static void
rtl8169transmit(Ether * edev)1320 rtl8169transmit(Ether* edev)
1321 {
1322 Ctlr *ctlr;
1323
1324 ctlr = edev->ctlr;
1325 if (ctlr == nil || ctlr->ntd == 0) {
1326 iprint("rtl8169transmit: not yet initialised\n");
1327 return;
1328 }
1329 wakeup(&ctlr->trendez);
1330 }
1331
1332 /*
1333 * the controller has lost its mind, so reset it.
1334 * call with ctlr->reglock held.
1335 */
1336 static void
restart(Ether * edev,char * why)1337 restart(Ether *edev, char *why)
1338 {
1339 int i, s, del;
1340 Ctlr *ctlr;
1341 static int inrestart;
1342 static Lock rstrtlck;
1343
1344 /* keep other cpus out */
1345 s = splhi();
1346 if (inrestart) {
1347 splx(s);
1348 return;
1349 }
1350 ilock(&rstrtlck);
1351
1352 ctlr = edev->ctlr;
1353 if (ctlr == nil || !ctlr->init) {
1354 iunlock(&rstrtlck);
1355 splx(s);
1356 return;
1357 }
1358
1359 if (Debug)
1360 iprint("#l%d: restart due to %s\n", edev->ctlrno, why);
1361 inrestart = 1;
1362
1363 /* process any pkts in the rings */
1364 wakeup(&ctlr->rrendez);
1365 coherence();
1366 rtl8169transmit(edev);
1367 /* allow time to drain 1024-buffer ring */
1368 for (del = 0; del < 13 && ctlr->ntq > 0; del++)
1369 delay(1);
1370
1371 iunlock(&ctlr->reglock);
1372 rtl8169reset(ctlr);
1373 /* free any remaining unprocessed input buffers */
1374 for (i = 0; i < ctlr->nrd; i++) {
1375 freeb(ctlr->rb[i]);
1376 ctlr->rb[i] = nil;
1377 }
1378 rtl8169init(edev);
1379 ilock(&ctlr->reglock);
1380
1381 rtl8169link(edev);
1382 rtl8169transmit(edev); /* drain any output queue */
1383 wakeup(&ctlr->rrendez);
1384
1385 inrestart = 0;
1386
1387 iunlock(&rstrtlck);
1388 splx(s);
1389 }
1390
1391 static ulong
rcvdiag(Ether * edev,ulong isr)1392 rcvdiag(Ether *edev, ulong isr)
1393 {
1394 Ctlr *ctlr;
1395
1396 ctlr = edev->ctlr;
1397 if(!(isr & (Punlc|Rok)))
1398 ctlr->ierrs++;
1399 if(isr & Rer)
1400 ctlr->rer++;
1401 if(isr & Rdu)
1402 ctlr->rdu++;
1403 if(isr & Punlc)
1404 ctlr->punlc++;
1405 if(isr & Fovw)
1406 ctlr->fovw++;
1407 if (isr & (Fovw|Rdu|Rer)) {
1408 if (isr & ~(Tdu|Tok|Rok)) /* harmless */
1409 iprint("#l%d: isr %8.8#lux\n", edev->ctlrno, isr);
1410 restart(edev, "rcv error");
1411 isr = ~0;
1412 }
1413 return isr;
1414 }
1415
1416 void
rtl8169interrupt(Ureg *,void * arg)1417 rtl8169interrupt(Ureg*, void* arg)
1418 {
1419 Ctlr *ctlr;
1420 Ether *edev;
1421 u32int isr;
1422
1423 edev = arg;
1424 ctlr = edev->ctlr;
1425 ilock(&ctlr->reglock);
1426
1427 while((isr = csr16r(ctlr, Isr)) != 0 && isr != 0xFFFF){
1428 ctlr->isr |= isr; /* merge bits for [rt]proc */
1429 csr16w(ctlr, Isr, isr); /* dismiss? */
1430 if((isr & ctlr->imr) == 0)
1431 break;
1432 if(isr & Fovw && ctlr->pciv == Rtl8168b) {
1433 /*
1434 * Fovw means we got behind; relatively common on 8168.
1435 * this is a big hammer, but it gets things going again.
1436 */
1437 ctlr->fovw++;
1438 restart(edev, "rx fifo overrun");
1439 break;
1440 }
1441 if(isr & (Fovw|Punlc|Rdu|Rer|Rok)) {
1442 ctlr->imr &= ~(Fovw|Rdu|Rer|Rok);
1443 csr16w(ctlr, Imr, ctlr->imr);
1444 wakeup(&ctlr->rrendez);
1445
1446 if (isr & (Fovw|Punlc|Rdu|Rer)) {
1447 isr = rcvdiag(edev, isr);
1448 if (isr == ~0)
1449 break; /* restarted */
1450 }
1451 isr &= ~(Fovw|Rdu|Rer|Rok);
1452 }
1453 if(isr & (Ter|Tok)){
1454 ctlr->imr &= ~(Ter|Tok);
1455 csr16w(ctlr, Imr, ctlr->imr);
1456 wakeup(&ctlr->trendez);
1457
1458 if (isr & Ter)
1459 iprint("xmit err; isr %8.8#ux\n", isr);
1460 isr &= ~(Ter|Tok);
1461 }
1462
1463 if(isr & Punlc){
1464 rtl8169link(edev);
1465 isr &= ~Punlc;
1466 }
1467
1468 /*
1469 * Some of the reserved bits get set sometimes...
1470 */
1471 if(isr & (Serr|Fovw|Punlc|Rdu|Ter|Tok|Rer|Rok))
1472 panic("rtl8169interrupt: imr %#4.4ux isr %#4.4ux",
1473 csr16r(ctlr, Imr), isr);
1474 }
1475 if (edev->link && ctlr->ntq > 0)
1476 csr8w(ctlr, Tppoll, Npq); /* kick xmiter to keep it going */
1477 iunlock(&ctlr->reglock);
1478 /*
1479 * extinguish pci-e controller interrupt source.
1480 * should be done more cleanly.
1481 */
1482 if (ctlr->pcie)
1483 pcieintrdone();
1484 }
1485
1486 int
vetmacv(Ctlr * ctlr,uint * macv)1487 vetmacv(Ctlr *ctlr, uint *macv)
1488 {
1489 *macv = csr32r(ctlr, Tcr) & HwveridMASK;
1490 switch(*macv){
1491 default:
1492 return -1;
1493 case Macv01:
1494 case Macv02:
1495 case Macv03:
1496 case Macv04:
1497 case Macv05:
1498 case Macv07:
1499 case Macv07a:
1500 case Macv11:
1501 case Macv12:
1502 case Macv12a:
1503 case Macv13:
1504 case Macv14:
1505 case Macv15:
1506 case Macv25:
1507 break;
1508 }
1509 return 0;
1510 }
1511
1512 static void
rtl8169pci(void)1513 rtl8169pci(void)
1514 {
1515 Pcidev *p;
1516 Ctlr *ctlr;
1517 int i, pcie;
1518 uint macv, bar;
1519 void *mem;
1520
1521 p = nil;
1522 while(p = pcimatch(p, 0, 0)){
1523 if(p->ccrb != 0x02 || p->ccru != 0)
1524 continue;
1525
1526 pcie = 0;
1527 switch(i = ((p->did<<16)|p->vid)){
1528 default:
1529 continue;
1530 case Rtl8100e: /* RTL810[01]E ? */
1531 case Rtl8168b: /* RTL8168B */
1532 pcie = 1;
1533 break;
1534 case Rtl8169c: /* RTL8169C */
1535 case Rtl8169sc: /* RTL8169SC */
1536 case Rtl8169: /* RTL8169 */
1537 break;
1538 case (0xC107<<16)|0x1259: /* Corega CG-LAPCIGT */
1539 i = Rtl8169;
1540 break;
1541 }
1542
1543 bar = p->mem[2].bar & ~0x0F;
1544 assert(bar != 0);
1545 assert(!(p->mem[2].bar & Barioaddr));
1546 if(0) iprint("rtl8169: %d-bit register accesses\n",
1547 ((p->mem[2].bar >> Barwidthshift) & Barwidthmask) ==
1548 Barwidth32? 32: 64);
1549 mem = (void *)bar; /* don't need to vmap on trimslice */
1550 if(mem == 0){
1551 print("rtl8169: can't map %#ux\n", bar);
1552 continue;
1553 }
1554 ctlr = malloc(sizeof(Ctlr));
1555 if(ctlr == nil)
1556 error(Enomem);
1557 ctlr->nic = mem;
1558 ctlr->port = bar;
1559 ctlr->pcidev = p;
1560 ctlr->pciv = i;
1561 ctlr->pcie = pcie;
1562
1563 if(vetmacv(ctlr, &macv) == -1){
1564 free(ctlr);
1565 print("rtl8169: unknown mac %.4ux %.8ux\n", p->did, macv);
1566 continue;
1567 }
1568
1569 if(pcigetpms(p) > 0){
1570 pcisetpms(p, 0);
1571
1572 for(i = 0; i < 6; i++)
1573 pcicfgw32(p, PciBAR0+i*4, p->mem[i].bar);
1574 pcicfgw8(p, PciINTL, p->intl);
1575 pcicfgw8(p, PciLTR, p->ltr);
1576 pcicfgw8(p, PciCLS, p->cls);
1577 pcicfgw16(p, PciPCR, p->pcr);
1578 }
1579
1580 if(rtl8169reset(ctlr)){
1581 free(ctlr);
1582 continue;
1583 }
1584
1585 /*
1586 * Extract the chip hardware version,
1587 * needed to configure each properly.
1588 */
1589 ctlr->macv = macv;
1590
1591 rtl8169mii(ctlr);
1592 pcisetbme(p);
1593
1594 if(rtl8169ctlrhead != nil)
1595 rtl8169ctlrtail->next = ctlr;
1596 else
1597 rtl8169ctlrhead = ctlr;
1598 rtl8169ctlrtail = ctlr;
1599 }
1600 }
1601
1602 static int
rtl8169pnp(Ether * edev)1603 rtl8169pnp(Ether* edev)
1604 {
1605 u32int r;
1606 Ctlr *ctlr;
1607 uchar ea[Eaddrlen];
1608 static int once;
1609
1610 if(once == 0){
1611 once = 1;
1612 rtl8169pci();
1613 }
1614
1615 /*
1616 * Any adapter matches if no edev->port is supplied,
1617 * otherwise the ports must match.
1618 */
1619 for(ctlr = rtl8169ctlrhead; ctlr != nil; ctlr = ctlr->next){
1620 if(ctlr->active)
1621 continue;
1622 if(edev->port == 0 || edev->port == ctlr->port){
1623 ctlr->active = 1;
1624 break;
1625 }
1626 }
1627 if(ctlr == nil)
1628 return -1;
1629
1630 edev->ctlr = ctlr;
1631 ctlr->ether = edev;
1632 edev->port = ctlr->port;
1633 // edev->irq = ctlr->pcidev->intl; /* incorrect on trimslice */
1634 edev->irq = Pcieirq; /* trimslice: non-msi pci-e intr */
1635 edev->tbdf = ctlr->pcidev->tbdf;
1636 edev->mbps = 1000;
1637 edev->maxmtu = Mtu;
1638
1639 /*
1640 * Check if the adapter's station address is to be overridden.
1641 * If not, read it from the device and set in edev->ea.
1642 */
1643 memset(ea, 0, Eaddrlen);
1644 if(memcmp(ea, edev->ea, Eaddrlen) == 0){
1645 r = csr32r(ctlr, Idr0);
1646 edev->ea[0] = r;
1647 edev->ea[1] = r>>8;
1648 edev->ea[2] = r>>16;
1649 edev->ea[3] = r>>24;
1650 r = csr32r(ctlr, Idr0+4);
1651 edev->ea[4] = r;
1652 edev->ea[5] = r>>8;
1653 }
1654
1655 edev->attach = rtl8169attach;
1656 edev->transmit = rtl8169transmit;
1657 edev->interrupt = rtl8169interrupt;
1658 edev->ifstat = rtl8169ifstat;
1659
1660 edev->arg = edev;
1661 edev->promiscuous = rtl8169promiscuous;
1662 edev->multicast = rtl8169multicast;
1663 edev->shutdown = rtl8169shutdown;
1664
1665 ilock(&ctlr->reglock);
1666 rtl8169link(edev);
1667 iunlock(&ctlr->reglock);
1668 return 0;
1669 }
1670
1671 void
ether8169link(void)1672 ether8169link(void)
1673 {
1674 addethercard("rtl8169", rtl8169pnp);
1675 }
1676