1 /* 2 * ECHI portable hardware definitions 3 */ 4 5 typedef struct Ecapio Ecapio; 6 typedef struct Edbgio Edbgio; 7 8 #pragma incomplete Ecapio; 9 #pragma incomplete Edbgio; 10 11 /* 12 * EHCI interface registers and bits 13 */ 14 enum 15 { 16 /* Ecapio->parms reg. */ 17 Cnports = 0xF, /* nport bits */ 18 Cdbgportshift = 20, /* debug port */ 19 Cdbgportmask = 0xF, 20 21 /* Ecapio->capparms bits */ 22 C64 = 1<<0, /* 64-bits */ 23 Cpfl = 1<<1, /* program'ble frame list: can be <1024 */ 24 Casp = 1<<2, /* asynch. sched. park */ 25 Ceecpshift = 8, /* extended capabilities ptr. */ 26 Ceecpmask = (1<<8) - 1, 27 28 Clegacy = 1, /* legacy support cap. id */ 29 CLbiossem = 2, /* legacy cap. bios sem. */ 30 CLossem = 3, /* legacy cap. os sem */ 31 CLcontrol = 4, /* legacy support control & status */ 32 33 /* typed links */ 34 Lterm = 1, 35 Litd = 0<<1, 36 Lqh = 1<<1, 37 Lsitd = 2<<1, 38 Lfstn = 3<<1, /* we don't use these */ 39 40 /* Cmd reg. */ 41 Cstop = 0x00000, /* stop running */ 42 Crun = 0x00001, /* start operation */ 43 Chcreset = 0x00002, /* host controller reset */ 44 Cflsmask = 0x0000C, /* frame list size bits */ 45 Cfls1024 = 0x00000, /* frame list size 1024 */ 46 Cfls512 = 0x00004, /* frame list size 512 frames */ 47 Cfls256 = 0x00008, /* frame list size 256 frames */ 48 Cpse = 0x00010, /* periodic sched. enable */ 49 Case = 0x00020, /* async sched. enable */ 50 Ciasync = 0x00040, /* interrupt on async advance doorbell */ 51 /* interrupt threshold ctl. in µframes (1-32 in powers of 2) */ 52 Citcshift = 16, 53 Citcmask = 0xff << Citcshift, 54 55 /* Sts reg. */ 56 Sasyncss = 0x08000, /* aync schedule status */ 57 Speriodss = 0x04000, /* periodic schedule status */ 58 Srecl = 0x02000, /* reclamnation (empty async sched.) */ 59 Shalted = 0x01000, /* h.c. is halted */ 60 Sasync = 0x00020, /* interrupt on async advance */ 61 Sherr = 0x00010, /* host system error */ 62 Sfrroll = 0x00008, /* frame list roll over */ 63 Sportchg = 0x00004, /* port change detect */ 64 Serrintr = 0x00002, /* error interrupt */ 65 Sintr = 0x00001, /* interrupt */ 66 Sintrs = 0x0003F, /* interrupts status */ 67 68 /* Intr reg. */ 69 Iusb = 0x01, /* intr. on usb */ 70 Ierr = 0x02, /* intr. on usb error */ 71 Iportchg = 0x04, /* intr. on port change */ 72 Ifrroll = 0x08, /* intr. on frlist roll over */ 73 Ihcerr = 0x10, /* intr. on host error */ 74 Iasync = 0x20, /* intr. on async advance enable */ 75 Iall = 0x3F, /* all interrupts */ 76 77 /* Config reg. */ 78 Callmine = 1, /* route all ports to us */ 79 80 /* Portsc reg. */ 81 Pspresent = 0x00000001, /* device present */ 82 Psstatuschg = 0x00000002, /* Pspresent changed */ 83 Psenable = 0x00000004, /* device enabled */ 84 Pschange = 0x00000008, /* Psenable changed */ 85 Psresume = 0x00000040, /* resume detected */ 86 Pssuspend = 0x00000080, /* port suspended */ 87 Psreset = 0x00000100, /* port reset */ 88 Pspower = 0x00001000, /* port power on */ 89 Psowner = 0x00002000, /* port owned by companion */ 90 Pslinemask = 0x00000C00, /* line status bits */ 91 Pslow = 0x00000400, /* low speed device */ 92 93 /* Debug port csw reg. */ 94 Cowner = 0x40000000, /* port owned by ehci */ 95 Cenable = 0x10000000, /* debug port enabled */ 96 Cdone = 0x00010000, /* request is done */ 97 Cbusy = 0x00000400, /* port in use by a driver */ 98 Cerrmask= 0x00000380, /* error code bits */ 99 Chwerr = 0x00000100, /* hardware error */ 100 Cterr = 0x00000080, /* transaction error */ 101 Cfailed = 0x00000040, /* transaction did fail */ 102 Cgo = 0x00000020, /* execute the transaction */ 103 Cwrite = 0x00000010, /* request is a write */ 104 Clen = 0x0000000F, /* data len */ 105 106 /* Debug port pid reg. */ 107 Prpidshift = 16, /* received pid */ 108 Prpidmask = 0xFF, 109 Pspidshift = 8, /* sent pid */ 110 Pspidmask = 0xFF, 111 Ptokshift = 0, /* token pid */ 112 Ptokmask = 0xFF, 113 114 Ptoggle = 0x00008800, /* to update toggles */ 115 Ptogglemask = 0x0000FF00, 116 117 /* Debug port addr reg. */ 118 Adevshift = 8, /* device address */ 119 Adevmask = 0x7F, 120 Aepshift = 0, /* endpoint number */ 121 Aepmask = 0xF, 122 }; 123 124 /* 125 * Capability registers (hw) 126 */ 127 struct Ecapio 128 { 129 ulong cap; /* 00 controller capability register */ 130 ulong parms; /* 04 structural parameters register */ 131 ulong capparms; /* 08 capability parameters */ 132 ulong portroute; /* 0c not on the CS5536 */ 133 }; 134 135 /* 136 * Debug port registers (hw) 137 */ 138 struct Edbgio 139 { 140 ulong csw; /* control and status */ 141 ulong pid; /* USB pid */ 142 uchar data[8]; /* data buffer */ 143 ulong addr; /* device and endpoint addresses */ 144 }; 145