1 /*
2 * Intel 8254[340]NN Gigabit Ethernet PCI Controllers
3 * as found on the Intel PRO/1000 series of adapters:
4 * 82543GC Intel PRO/1000 T
5 * 82544EI Intel PRO/1000 XT
6 * 82540EM Intel PRO/1000 MT
7 * 82541[GP]I
8 * 82547GI
9 * 82546GB
10 * 82546EB
11 * To Do:
12 * finish autonegotiation code;
13 * integrate fiber stuff back in (this ONLY handles
14 * the CAT5 cards at the moment);
15 * add tuning control via ctl file;
16 * this driver is little-endian specific.
17 */
18 #include "u.h"
19 #include "../port/lib.h"
20 #include "mem.h"
21 #include "dat.h"
22 #include "fns.h"
23 #include "io.h"
24 #include "../port/error.h"
25 #include "../port/netif.h"
26
27 #include "etherif.h"
28 #include "ethermii.h"
29
30 enum {
31 i82542 = (0x1000<<16)|0x8086,
32 i82543gc = (0x1004<<16)|0x8086,
33 i82544ei = (0x1008<<16)|0x8086,
34 i82544eif = (0x1009<<16)|0x8086,
35 i82544gc = (0x100d<<16)|0x8086,
36 i82540em = (0x100E<<16)|0x8086,
37 i82540eplp = (0x101E<<16)|0x8086,
38 i82545em = (0x100F<<16)|0x8086,
39 i82545gmc = (0x1026<<16)|0x8086,
40 i82547ei = (0x1019<<16)|0x8086,
41 i82547gi = (0x1075<<16)|0x8086,
42 i82541ei = (0x1013<<16)|0x8086,
43 i82541gi = (0x1076<<16)|0x8086,
44 i82541gi2 = (0x1077<<16)|0x8086,
45 i82541pi = (0x107c<<16)|0x8086,
46 i82546gb = (0x1079<<16)|0x8086,
47 i82546eb = (0x1010<<16)|0x8086,
48 };
49
50 enum {
51 Ctrl = 0x00000000, /* Device Control */
52 Ctrldup = 0x00000004, /* Device Control Duplicate */
53 Status = 0x00000008, /* Device Status */
54 Eecd = 0x00000010, /* EEPROM/Flash Control/Data */
55 Ctrlext = 0x00000018, /* Extended Device Control */
56 Mdic = 0x00000020, /* MDI Control */
57 Fcal = 0x00000028, /* Flow Control Address Low */
58 Fcah = 0x0000002C, /* Flow Control Address High */
59 Fct = 0x00000030, /* Flow Control Type */
60 Icr = 0x000000C0, /* Interrupt Cause Read */
61 Ics = 0x000000C8, /* Interrupt Cause Set */
62 Ims = 0x000000D0, /* Interrupt Mask Set/Read */
63 Imc = 0x000000D8, /* Interrupt mask Clear */
64 Rctl = 0x00000100, /* Receive Control */
65 Fcttv = 0x00000170, /* Flow Control Transmit Timer Value */
66 Txcw = 0x00000178, /* Transmit Configuration Word */
67 Rxcw = 0x00000180, /* Receive Configuration Word */
68 /* on the oldest cards (8254[23]), the Mta register is at 0x200 */
69 Tctl = 0x00000400, /* Transmit Control */
70 Tipg = 0x00000410, /* Transmit IPG */
71 Tbt = 0x00000448, /* Transmit Burst Timer */
72 Ait = 0x00000458, /* Adaptive IFS Throttle */
73 Fcrtl = 0x00002160, /* Flow Control RX Threshold Low */
74 Fcrth = 0x00002168, /* Flow Control Rx Threshold High */
75 Rdfh = 0x00002410, /* Receive data fifo head */
76 Rdft = 0x00002418, /* Receive data fifo tail */
77 Rdfhs = 0x00002420, /* Receive data fifo head saved */
78 Rdfts = 0x00002428, /* Receive data fifo tail saved */
79 Rdfpc = 0x00002430, /* Receive data fifo packet count */
80 Rdbal = 0x00002800, /* Rd Base Address Low */
81 Rdbah = 0x00002804, /* Rd Base Address High */
82 Rdlen = 0x00002808, /* Receive Descriptor Length */
83 Rdh = 0x00002810, /* Receive Descriptor Head */
84 Rdt = 0x00002818, /* Receive Descriptor Tail */
85 Rdtr = 0x00002820, /* Receive Descriptor Timer Ring */
86 Rxdctl = 0x00002828, /* Receive Descriptor Control */
87 Radv = 0x0000282C, /* Receive Interrupt Absolute Delay Timer */
88 Txdmac = 0x00003000, /* Transfer DMA Control */
89 Ett = 0x00003008, /* Early Transmit Control */
90 Tdfh = 0x00003410, /* Transmit data fifo head */
91 Tdft = 0x00003418, /* Transmit data fifo tail */
92 Tdfhs = 0x00003420, /* Transmit data Fifo Head saved */
93 Tdfts = 0x00003428, /* Transmit data fifo tail saved */
94 Tdfpc = 0x00003430, /* Trasnmit data Fifo packet count */
95 Tdbal = 0x00003800, /* Td Base Address Low */
96 Tdbah = 0x00003804, /* Td Base Address High */
97 Tdlen = 0x00003808, /* Transmit Descriptor Length */
98 Tdh = 0x00003810, /* Transmit Descriptor Head */
99 Tdt = 0x00003818, /* Transmit Descriptor Tail */
100 Tidv = 0x00003820, /* Transmit Interrupt Delay Value */
101 Txdctl = 0x00003828, /* Transmit Descriptor Control */
102 Tadv = 0x0000382C, /* Transmit Interrupt Absolute Delay Timer */
103
104 Statistics = 0x00004000, /* Start of Statistics Area */
105 Gorcl = 0x88/4, /* Good Octets Received Count */
106 Gotcl = 0x90/4, /* Good Octets Transmitted Count */
107 Torl = 0xC0/4, /* Total Octets Received */
108 Totl = 0xC8/4, /* Total Octets Transmitted */
109 Nstatistics = 64,
110
111 Rxcsum = 0x00005000, /* Receive Checksum Control */
112 Mta = 0x00005200, /* Multicast Table Array */
113 Ral = 0x00005400, /* Receive Address Low */
114 Rah = 0x00005404, /* Receive Address High */
115 Manc = 0x00005820, /* Management Control */
116 };
117
118 enum { /* Ctrl */
119 Bem = 0x00000002, /* Big Endian Mode */
120 Prior = 0x00000004, /* Priority on the PCI bus */
121 Lrst = 0x00000008, /* Link Reset */
122 Asde = 0x00000020, /* Auto-Speed Detection Enable */
123 Slu = 0x00000040, /* Set Link Up */
124 Ilos = 0x00000080, /* Invert Loss of Signal (LOS) */
125 SspeedMASK = 0x00000300, /* Speed Selection */
126 SspeedSHIFT = 8,
127 Sspeed10 = 0x00000000, /* 10Mb/s */
128 Sspeed100 = 0x00000100, /* 100Mb/s */
129 Sspeed1000 = 0x00000200, /* 1000Mb/s */
130 Frcspd = 0x00000800, /* Force Speed */
131 Frcdplx = 0x00001000, /* Force Duplex */
132 SwdpinsloMASK = 0x003C0000, /* Software Defined Pins - lo nibble */
133 SwdpinsloSHIFT = 18,
134 SwdpioloMASK = 0x03C00000, /* Software Defined Pins - I or O */
135 SwdpioloSHIFT = 22,
136 Devrst = 0x04000000, /* Device Reset */
137 Rfce = 0x08000000, /* Receive Flow Control Enable */
138 Tfce = 0x10000000, /* Transmit Flow Control Enable */
139 Vme = 0x40000000, /* VLAN Mode Enable */
140 };
141
142 /*
143 * can't find Tckok nor Rbcok in any Intel docs,
144 * but even 82543gc docs define Lanid.
145 */
146 enum { /* Status */
147 Lu = 0x00000002, /* Link Up */
148 Lanid = 0x0000000C, /* mask for Lan ID. (function id) */
149 // Tckok = 0x00000004, /* Transmit clock is running */
150 // Rbcok = 0x00000008, /* Receive clock is running */
151 Txoff = 0x00000010, /* Transmission Paused */
152 Tbimode = 0x00000020, /* TBI Mode Indication */
153 LspeedMASK = 0x000000C0, /* Link Speed Setting */
154 LspeedSHIFT = 6,
155 Lspeed10 = 0x00000000, /* 10Mb/s */
156 Lspeed100 = 0x00000040, /* 100Mb/s */
157 Lspeed1000 = 0x00000080, /* 1000Mb/s */
158 Mtxckok = 0x00000400, /* MTX clock is running */
159 Pci66 = 0x00000800, /* PCI Bus speed indication */
160 Bus64 = 0x00001000, /* PCI Bus width indication */
161 Pcixmode = 0x00002000, /* PCI-X mode */
162 PcixspeedMASK = 0x0000C000, /* PCI-X bus speed */
163 PcixspeedSHIFT = 14,
164 Pcix66 = 0x00000000, /* 50-66MHz */
165 Pcix100 = 0x00004000, /* 66-100MHz */
166 Pcix133 = 0x00008000, /* 100-133MHz */
167 };
168
169 enum { /* Ctrl and Status */
170 Fd = 0x00000001, /* Full-Duplex */
171 AsdvMASK = 0x00000300,
172 AsdvSHIFT = 8,
173 Asdv10 = 0x00000000, /* 10Mb/s */
174 Asdv100 = 0x00000100, /* 100Mb/s */
175 Asdv1000 = 0x00000200, /* 1000Mb/s */
176 };
177
178 enum { /* Eecd */
179 Sk = 0x00000001, /* Clock input to the EEPROM */
180 Cs = 0x00000002, /* Chip Select */
181 Di = 0x00000004, /* Data Input to the EEPROM */
182 Do = 0x00000008, /* Data Output from the EEPROM */
183 Areq = 0x00000040, /* EEPROM Access Request */
184 Agnt = 0x00000080, /* EEPROM Access Grant */
185 Eepresent = 0x00000100, /* EEPROM Present */
186 Eesz256 = 0x00000200, /* EEPROM is 256 words not 64 */
187 Eeszaddr = 0x00000400, /* EEPROM size for 8254[17] */
188 Spi = 0x00002000, /* EEPROM is SPI not Microwire */
189 };
190
191 enum { /* Ctrlext */
192 Gpien = 0x0000000F, /* General Purpose Interrupt Enables */
193 SwdpinshiMASK = 0x000000F0, /* Software Defined Pins - hi nibble */
194 SwdpinshiSHIFT = 4,
195 SwdpiohiMASK = 0x00000F00, /* Software Defined Pins - I or O */
196 SwdpiohiSHIFT = 8,
197 Asdchk = 0x00001000, /* ASD Check */
198 Eerst = 0x00002000, /* EEPROM Reset */
199 Ips = 0x00004000, /* Invert Power State */
200 Spdbyps = 0x00008000, /* Speed Select Bypass */
201 };
202
203 enum { /* EEPROM content offsets */
204 Ea = 0x00, /* Ethernet Address */
205 Cf = 0x03, /* Compatibility Field */
206 Pba = 0x08, /* Printed Board Assembly number */
207 Icw1 = 0x0A, /* Initialization Control Word 1 */
208 Sid = 0x0B, /* Subsystem ID */
209 Svid = 0x0C, /* Subsystem Vendor ID */
210 Did = 0x0D, /* Device ID */
211 Vid = 0x0E, /* Vendor ID */
212 Icw2 = 0x0F, /* Initialization Control Word 2 */
213 };
214
215 enum { /* Mdic */
216 MDIdMASK = 0x0000FFFF, /* Data */
217 MDIdSHIFT = 0,
218 MDIrMASK = 0x001F0000, /* PHY Register Address */
219 MDIrSHIFT = 16,
220 MDIpMASK = 0x03E00000, /* PHY Address */
221 MDIpSHIFT = 21,
222 MDIwop = 0x04000000, /* Write Operation */
223 MDIrop = 0x08000000, /* Read Operation */
224 MDIready = 0x10000000, /* End of Transaction */
225 MDIie = 0x20000000, /* Interrupt Enable */
226 MDIe = 0x40000000, /* Error */
227 };
228
229 enum { /* Icr, Ics, Ims, Imc */
230 Txdw = 0x00000001, /* Transmit Descriptor Written Back */
231 Txqe = 0x00000002, /* Transmit Queue Empty */
232 Lsc = 0x00000004, /* Link Status Change */
233 Rxseq = 0x00000008, /* Receive Sequence Error */
234 Rxdmt0 = 0x00000010, /* Rd Minimum Threshold Reached */
235 Rxo = 0x00000040, /* Receiver Overrun */
236 Rxt0 = 0x00000080, /* Receiver Timer Interrupt */
237 Mdac = 0x00000200, /* MDIO Access Completed */
238 Rxcfg = 0x00000400, /* Receiving /C/ ordered sets */
239 Gpi0 = 0x00000800, /* General Purpose Interrupts */
240 Gpi1 = 0x00001000,
241 Gpi2 = 0x00002000,
242 Gpi3 = 0x00004000,
243 };
244
245 /*
246 * The Mdic register isn't implemented on the 82543GC,
247 * the software defined pins are used instead.
248 * These definitions work for the Intel PRO/1000 T Server Adapter.
249 * The direction pin bits are read from the EEPROM.
250 */
251 enum {
252 Mdd = ((1<<2)<<SwdpinsloSHIFT), /* data */
253 Mddo = ((1<<2)<<SwdpioloSHIFT), /* pin direction */
254 Mdc = ((1<<3)<<SwdpinsloSHIFT), /* clock */
255 Mdco = ((1<<3)<<SwdpioloSHIFT), /* pin direction */
256 Mdr = ((1<<0)<<SwdpinshiSHIFT), /* reset */
257 Mdro = ((1<<0)<<SwdpiohiSHIFT), /* pin direction */
258 };
259
260 enum { /* Txcw */
261 TxcwFd = 0x00000020, /* Full Duplex */
262 TxcwHd = 0x00000040, /* Half Duplex */
263 TxcwPauseMASK = 0x00000180, /* Pause */
264 TxcwPauseSHIFT = 7,
265 TxcwPs = (1<<TxcwPauseSHIFT), /* Pause Supported */
266 TxcwAs = (2<<TxcwPauseSHIFT), /* Asymmetric FC desired */
267 TxcwRfiMASK = 0x00003000, /* Remote Fault Indication */
268 TxcwRfiSHIFT = 12,
269 TxcwNpr = 0x00008000, /* Next Page Request */
270 TxcwConfig = 0x40000000, /* Transmit COnfig Control */
271 TxcwAne = 0x80000000, /* Auto-Negotiation Enable */
272 };
273
274 enum { /* Rxcw */
275 Rxword = 0x0000FFFF, /* Data from auto-negotiation process */
276 Rxnocarrier = 0x04000000, /* Carrier Sense indication */
277 Rxinvalid = 0x08000000, /* Invalid Symbol during configuration */
278 Rxchange = 0x10000000, /* Change to the Rxword indication */
279 Rxconfig = 0x20000000, /* /C/ order set reception indication */
280 Rxsync = 0x40000000, /* Lost bit synchronization indication */
281 Anc = 0x80000000, /* Auto Negotiation Complete */
282 };
283
284 enum { /* Rctl */
285 Rrst = 0x00000001, /* Receiver Software Reset */
286 Ren = 0x00000002, /* Receiver Enable */
287 Sbp = 0x00000004, /* Store Bad Packets */
288 Upe = 0x00000008, /* Unicast Promiscuous Enable */
289 Mpe = 0x00000010, /* Multicast Promiscuous Enable */
290 Lpe = 0x00000020, /* Long Packet Reception Enable */
291 LbmMASK = 0x000000C0, /* Loopback Mode */
292 LbmOFF = 0x00000000, /* No Loopback */
293 LbmTBI = 0x00000040, /* TBI Loopback */
294 LbmMII = 0x00000080, /* GMII/MII Loopback */
295 LbmXCVR = 0x000000C0, /* Transceiver Loopback */
296 RdtmsMASK = 0x00000300, /* Rd Minimum Threshold Size */
297 RdtmsHALF = 0x00000000, /* Threshold is 1/2 Rdlen */
298 RdtmsQUARTER = 0x00000100, /* Threshold is 1/4 Rdlen */
299 RdtmsEIGHTH = 0x00000200, /* Threshold is 1/8 Rdlen */
300 MoMASK = 0x00003000, /* Multicast Offset */
301 Mo47b36 = 0x00000000, /* bits [47:36] of received address */
302 Mo46b35 = 0x00001000, /* bits [46:35] of received address */
303 Mo45b34 = 0x00002000, /* bits [45:34] of received address */
304 Mo43b32 = 0x00003000, /* bits [43:32] of received address */
305 Bam = 0x00008000, /* Broadcast Accept Mode */
306 BsizeMASK = 0x00030000, /* Receive Buffer Size */
307 Bsize2048 = 0x00000000, /* Bsex = 0 */
308 Bsize1024 = 0x00010000, /* Bsex = 0 */
309 Bsize512 = 0x00020000, /* Bsex = 0 */
310 Bsize256 = 0x00030000, /* Bsex = 0 */
311 Bsize16384 = 0x00010000, /* Bsex = 1 */
312 Vfe = 0x00040000, /* VLAN Filter Enable */
313 Cfien = 0x00080000, /* Canonical Form Indicator Enable */
314 Cfi = 0x00100000, /* Canonical Form Indicator value */
315 Dpf = 0x00400000, /* Discard Pause Frames */
316 Pmcf = 0x00800000, /* Pass MAC Control Frames */
317 Bsex = 0x02000000, /* Buffer Size Extension */
318 Secrc = 0x04000000, /* Strip CRC from incoming packet */
319 };
320
321 enum { /* Tctl */
322 Trst = 0x00000001, /* Transmitter Software Reset */
323 Ten = 0x00000002, /* Transmit Enable */
324 Psp = 0x00000008, /* Pad Short Packets */
325 CtMASK = 0x00000FF0, /* Collision Threshold */
326 CtSHIFT = 4,
327 ColdMASK = 0x003FF000, /* Collision Distance */
328 ColdSHIFT = 12,
329 Swxoff = 0x00400000, /* Sofware XOFF Transmission */
330 Pbe = 0x00800000, /* Packet Burst Enable */
331 Rtlc = 0x01000000, /* Re-transmit on Late Collision */
332 Nrtu = 0x02000000, /* No Re-transmit on Underrrun */
333 };
334
335 enum { /* [RT]xdctl */
336 PthreshMASK = 0x0000003F, /* Prefetch Threshold */
337 PthreshSHIFT = 0,
338 HthreshMASK = 0x00003F00, /* Host Threshold */
339 HthreshSHIFT = 8,
340 WthreshMASK = 0x003F0000, /* Writeback Threshold */
341 WthreshSHIFT = 16,
342 Gran = 0x01000000, /* Granularity */
343 LthreshMASK = 0xFE000000, /* Low Threshold */
344 LthreshSHIFT = 25,
345 };
346
347 enum { /* Rxcsum */
348 PcssMASK = 0x000000FF, /* Packet Checksum Start */
349 PcssSHIFT = 0,
350 Ipofl = 0x00000100, /* IP Checksum Off-load Enable */
351 Tuofl = 0x00000200, /* TCP/UDP Checksum Off-load Enable */
352 };
353
354 enum { /* Manc */
355 Arpen = 0x00002000, /* Enable ARP Request Filtering */
356 };
357
358 enum { /* Receive Delay Timer Ring */
359 DelayMASK = 0x0000FFFF, /* delay timer in 1.024nS increments */
360 DelaySHIFT = 0,
361 Fpd = 0x80000000, /* Flush partial Descriptor Block */
362 };
363
364 typedef struct Rd { /* Receive Descriptor */
365 uint addr[2];
366 ushort length;
367 ushort checksum;
368 uchar status;
369 uchar errors;
370 ushort special;
371 } Rd;
372
373 enum { /* Rd status */
374 Rdd = 0x01, /* Descriptor Done */
375 Reop = 0x02, /* End of Packet */
376 Ixsm = 0x04, /* Ignore Checksum Indication */
377 Vp = 0x08, /* Packet is 802.1Q (matched VET) */
378 Tcpcs = 0x20, /* TCP Checksum Calculated on Packet */
379 Ipcs = 0x40, /* IP Checksum Calculated on Packet */
380 Pif = 0x80, /* Passed in-exact filter */
381 };
382
383 enum { /* Rd errors */
384 Ce = 0x01, /* CRC Error or Alignment Error */
385 Se = 0x02, /* Symbol Error */
386 Seq = 0x04, /* Sequence Error */
387 Cxe = 0x10, /* Carrier Extension Error */
388 Tcpe = 0x20, /* TCP/UDP Checksum Error */
389 Ipe = 0x40, /* IP Checksum Error */
390 Rxe = 0x80, /* RX Data Error */
391 };
392
393 typedef struct Td Td;
394 struct Td { /* Transmit Descriptor */
395 union {
396 uint addr[2]; /* Data */
397 struct { /* Context */
398 uchar ipcss;
399 uchar ipcso;
400 ushort ipcse;
401 uchar tucss;
402 uchar tucso;
403 ushort tucse;
404 };
405 };
406 uint control;
407 uint status;
408 };
409
410 enum { /* Td control */
411 LenMASK = 0x000FFFFF, /* Data/Packet Length Field */
412 LenSHIFT = 0,
413 DtypeCD = 0x00000000, /* Data Type 'Context Descriptor' */
414 DtypeDD = 0x00100000, /* Data Type 'Data Descriptor' */
415 PtypeTCP = 0x01000000, /* TCP/UDP Packet Type (CD) */
416 Teop = 0x01000000, /* End of Packet (DD) */
417 PtypeIP = 0x02000000, /* IP Packet Type (CD) */
418 Ifcs = 0x02000000, /* Insert FCS (DD) */
419 Tse = 0x04000000, /* TCP Segmentation Enable */
420 Rs = 0x08000000, /* Report Status */
421 Rps = 0x10000000, /* Report Status Sent */
422 Dext = 0x20000000, /* Descriptor Extension */
423 Vle = 0x40000000, /* VLAN Packet Enable */
424 Ide = 0x80000000, /* Interrupt Delay Enable */
425 };
426
427 enum { /* Td status */
428 Tdd = 0x00000001, /* Descriptor Done */
429 Ec = 0x00000002, /* Excess Collisions */
430 Lc = 0x00000004, /* Late Collision */
431 Tu = 0x00000008, /* Transmit Underrun */
432 Iixsm = 0x00000100, /* Insert IP Checksum */
433 Itxsm = 0x00000200, /* Insert TCP/UDP Checksum */
434 HdrlenMASK = 0x0000FF00, /* Header Length (Tse) */
435 HdrlenSHIFT = 8,
436 VlanMASK = 0x0FFF0000, /* VLAN Identifier */
437 VlanSHIFT = 16,
438 Tcfi = 0x10000000, /* Canonical Form Indicator */
439 PriMASK = 0xE0000000, /* User Priority */
440 PriSHIFT = 29,
441 MssMASK = 0xFFFF0000, /* Maximum Segment Size (Tse) */
442 MssSHIFT = 16,
443 };
444
445 enum {
446 Rbsz = 2048,
447 /* were 256, 1024 & 64, but 52, 253 and 9 are ample. */
448 Nrd = 128, /* multiple of 8 */
449 Nrb = 512, /* private receive buffers per Ctlr */
450 Ntd = 32, /* multiple of 8 */
451 };
452
453 typedef struct Ctlr Ctlr;
454 struct Ctlr {
455 int port;
456 Pcidev* pcidev;
457 Ctlr* next;
458 Ether* edev;
459 int active;
460 int started;
461 int id;
462 int cls;
463 ushort eeprom[0x40];
464
465 QLock alock; /* attach */
466 void* alloc; /* receive/transmit descriptors */
467 int nrd;
468 int ntd;
469 int nrb; /* # bufs this Ctlr has in the pool */
470
471 int* nic;
472 Lock imlock;
473 int im; /* interrupt mask */
474
475 Mii* mii;
476 Rendez lrendez;
477 int lim;
478
479 int link;
480
481 Watermark wmrb;
482 Watermark wmrd;
483 Watermark wmtd;
484
485 QLock slock;
486 uint statistics[Nstatistics];
487 uint lsleep;
488 uint lintr;
489 uint rsleep;
490 uint rintr;
491 uint txdw;
492 uint tintr;
493 uint ixsm;
494 uint ipcs;
495 uint tcpcs;
496
497 uchar ra[Eaddrlen]; /* receive address */
498 ulong mta[128]; /* multicast table array */
499
500 Rendez rrendez;
501 int rim;
502 int rdfree; /* rx descriptors awaiting packets */
503 Rd* rdba; /* receive descriptor base address */
504 Block** rb; /* receive buffers */
505 int rdh; /* receive descriptor head */
506 int rdt; /* receive descriptor tail */
507 int rdtr; /* receive delay timer ring value */
508
509 Lock tlock;
510 int tdfree;
511 Td* tdba; /* transmit descriptor base address */
512 Block** tb; /* transmit buffers */
513 int tdh; /* transmit descriptor head */
514 int tdt; /* transmit descriptor tail */
515
516 int txcw;
517 int fcrtl;
518 int fcrth;
519 };
520
521 #define csr32r(c, r) (*((c)->nic+((r)/4)))
522 #define csr32w(c, r, v) (*((c)->nic+((r)/4)) = (v))
523
524 static Ctlr* igbectlrhead;
525 static Ctlr* igbectlrtail;
526
527 static Lock igberblock; /* free receive Blocks */
528 static Block* igberbpool; /* receive Blocks for all igbe controllers */
529 static int nrbfull; /* # of rcv Blocks with data awaiting processing */
530
531 static char* statistics[Nstatistics] = {
532 "CRC Error",
533 "Alignment Error",
534 "Symbol Error",
535 "RX Error",
536 "Missed Packets",
537 "Single Collision",
538 "Excessive Collisions",
539 "Multiple Collision",
540 "Late Collisions",
541 nil,
542 "Collision",
543 "Transmit Underrun",
544 "Defer",
545 "Transmit - No CRS",
546 "Sequence Error",
547 "Carrier Extension Error",
548 "Receive Error Length",
549 nil,
550 "XON Received",
551 "XON Transmitted",
552 "XOFF Received",
553 "XOFF Transmitted",
554 "FC Received Unsupported",
555 "Packets Received (64 Bytes)",
556 "Packets Received (65-127 Bytes)",
557 "Packets Received (128-255 Bytes)",
558 "Packets Received (256-511 Bytes)",
559 "Packets Received (512-1023 Bytes)",
560 "Packets Received (1024-1522 Bytes)",
561 "Good Packets Received",
562 "Broadcast Packets Received",
563 "Multicast Packets Received",
564 "Good Packets Transmitted",
565 nil,
566 "Good Octets Received",
567 nil,
568 "Good Octets Transmitted",
569 nil,
570 nil,
571 nil,
572 "Receive No Buffers",
573 "Receive Undersize",
574 "Receive Fragment",
575 "Receive Oversize",
576 "Receive Jabber",
577 nil,
578 nil,
579 nil,
580 "Total Octets Received",
581 nil,
582 "Total Octets Transmitted",
583 nil,
584 "Total Packets Received",
585 "Total Packets Transmitted",
586 "Packets Transmitted (64 Bytes)",
587 "Packets Transmitted (65-127 Bytes)",
588 "Packets Transmitted (128-255 Bytes)",
589 "Packets Transmitted (256-511 Bytes)",
590 "Packets Transmitted (512-1023 Bytes)",
591 "Packets Transmitted (1024-1522 Bytes)",
592 "Multicast Packets Transmitted",
593 "Broadcast Packets Transmitted",
594 "TCP Segmentation Context Transmitted",
595 "TCP Segmentation Context Fail",
596 };
597
598 static long
igbeifstat(Ether * edev,void * a,long n,ulong offset)599 igbeifstat(Ether* edev, void* a, long n, ulong offset)
600 {
601 Ctlr *ctlr;
602 char *p, *s, *e;
603 int i, l, r;
604 uvlong tuvl, ruvl;
605
606 ctlr = edev->ctlr;
607 qlock(&ctlr->slock);
608 p = malloc(READSTR);
609 if(p == nil) {
610 qunlock(&ctlr->slock);
611 error(Enomem);
612 }
613 l = 0;
614 for(i = 0; i < Nstatistics; i++){
615 r = csr32r(ctlr, Statistics+i*4);
616 if((s = statistics[i]) == nil)
617 continue;
618 switch(i){
619 case Gorcl:
620 case Gotcl:
621 case Torl:
622 case Totl:
623 ruvl = r;
624 ruvl += ((uvlong)csr32r(ctlr, Statistics+(i+1)*4))<<32;
625 tuvl = ruvl;
626 tuvl += ctlr->statistics[i];
627 tuvl += ((uvlong)ctlr->statistics[i+1])<<32;
628 if(tuvl == 0)
629 continue;
630 ctlr->statistics[i] = tuvl;
631 ctlr->statistics[i+1] = tuvl>>32;
632 l += snprint(p+l, READSTR-l, "%s: %llud %llud\n",
633 s, tuvl, ruvl);
634 i++;
635 break;
636
637 default:
638 ctlr->statistics[i] += r;
639 if(ctlr->statistics[i] == 0)
640 continue;
641 l += snprint(p+l, READSTR-l, "%s: %ud %ud\n",
642 s, ctlr->statistics[i], r);
643 break;
644 }
645 }
646
647 l += snprint(p+l, READSTR-l, "lintr: %ud %ud\n",
648 ctlr->lintr, ctlr->lsleep);
649 l += snprint(p+l, READSTR-l, "rintr: %ud %ud\n",
650 ctlr->rintr, ctlr->rsleep);
651 l += snprint(p+l, READSTR-l, "tintr: %ud %ud\n",
652 ctlr->tintr, ctlr->txdw);
653 l += snprint(p+l, READSTR-l, "ixcs: %ud %ud %ud\n",
654 ctlr->ixsm, ctlr->ipcs, ctlr->tcpcs);
655 l += snprint(p+l, READSTR-l, "rdtr: %ud\n", ctlr->rdtr);
656 l += snprint(p+l, READSTR-l, "Ctrlext: %08x\n", csr32r(ctlr, Ctrlext));
657
658 l += snprint(p+l, READSTR-l, "eeprom:");
659 for(i = 0; i < 0x40; i++){
660 if(i && ((i & 0x07) == 0))
661 l += snprint(p+l, READSTR-l, "\n ");
662 l += snprint(p+l, READSTR-l, " %4.4uX", ctlr->eeprom[i]);
663 }
664 l += snprint(p+l, READSTR-l, "\n");
665
666 if(ctlr->mii != nil && ctlr->mii->curphy != nil){
667 l += snprint(p+l, READSTR-l, "phy: ");
668 for(i = 0; i < NMiiPhyr; i++){
669 if(i && ((i & 0x07) == 0))
670 l += snprint(p+l, READSTR-l, "\n ");
671 r = miimir(ctlr->mii, i);
672 l += snprint(p+l, READSTR-l, " %4.4uX", r);
673 }
674 snprint(p+l, READSTR-l, "\n");
675 }
676 e = p + READSTR;
677 s = p + l + 1;
678 s = seprintmark(s, e, &ctlr->wmrb);
679 s = seprintmark(s, e, &ctlr->wmrd);
680 s = seprintmark(s, e, &ctlr->wmtd);
681 USED(s);
682
683 n = readstr(offset, a, n, p);
684 free(p);
685 qunlock(&ctlr->slock);
686
687 return n;
688 }
689
690 enum {
691 CMrdtr,
692 };
693
694 static Cmdtab igbectlmsg[] = {
695 CMrdtr, "rdtr", 2,
696 };
697
698 static long
igbectl(Ether * edev,void * buf,long n)699 igbectl(Ether* edev, void* buf, long n)
700 {
701 int v;
702 char *p;
703 Ctlr *ctlr;
704 Cmdbuf *cb;
705 Cmdtab *ct;
706
707 if((ctlr = edev->ctlr) == nil)
708 error(Enonexist);
709
710 cb = parsecmd(buf, n);
711 if(waserror()){
712 free(cb);
713 nexterror();
714 }
715
716 ct = lookupcmd(cb, igbectlmsg, nelem(igbectlmsg));
717 switch(ct->index){
718 case CMrdtr:
719 v = strtol(cb->f[1], &p, 0);
720 if(v < 0 || p == cb->f[1] || v > 0xFFFF)
721 error(Ebadarg);
722 ctlr->rdtr = v;
723 csr32w(ctlr, Rdtr, Fpd|v);
724 break;
725 }
726 free(cb);
727 poperror();
728
729 return n;
730 }
731
732 static void
igbepromiscuous(void * arg,int on)733 igbepromiscuous(void* arg, int on)
734 {
735 int rctl;
736 Ctlr *ctlr;
737 Ether *edev;
738
739 edev = arg;
740 ctlr = edev->ctlr;
741
742 rctl = csr32r(ctlr, Rctl);
743 rctl &= ~MoMASK;
744 rctl |= Mo47b36;
745 if(on)
746 rctl |= Upe|Mpe;
747 else
748 rctl &= ~(Upe|Mpe);
749 csr32w(ctlr, Rctl, rctl|Mpe); /* temporarily keep Mpe on */
750 }
751
752 static void
igbemulticast(void * arg,uchar * addr,int add)753 igbemulticast(void* arg, uchar* addr, int add)
754 {
755 int bit, x;
756 Ctlr *ctlr;
757 Ether *edev;
758
759 edev = arg;
760 ctlr = edev->ctlr;
761
762 x = addr[5]>>1;
763 bit = ((addr[5] & 1)<<4)|(addr[4]>>4);
764 /*
765 * multiple ether addresses can hash to the same filter bit,
766 * so it's never safe to clear a filter bit.
767 * if we want to clear filter bits, we need to keep track of
768 * all the multicast addresses in use, clear all the filter bits,
769 * then set the ones corresponding to in-use addresses.
770 */
771 if(add)
772 ctlr->mta[x] |= 1<<bit;
773 // else
774 // ctlr->mta[x] &= ~(1<<bit);
775
776 csr32w(ctlr, Mta+x*4, ctlr->mta[x]);
777 }
778
779 static Block*
igberballoc(void)780 igberballoc(void)
781 {
782 Block *bp;
783
784 ilock(&igberblock);
785 if((bp = igberbpool) != nil){
786 igberbpool = bp->next;
787 bp->next = nil;
788 _xinc(&bp->ref); /* prevent bp from being freed */
789 }
790 iunlock(&igberblock);
791
792 return bp;
793 }
794
795 static void
igberbfree(Block * bp)796 igberbfree(Block* bp)
797 {
798 bp->rp = bp->lim - Rbsz;
799 bp->wp = bp->rp;
800 bp->flag &= ~(Bipck | Budpck | Btcpck | Bpktck);
801
802 ilock(&igberblock);
803 bp->next = igberbpool;
804 igberbpool = bp;
805 nrbfull--;
806 iunlock(&igberblock);
807 }
808
809 static void
igbeim(Ctlr * ctlr,int im)810 igbeim(Ctlr* ctlr, int im)
811 {
812 ilock(&ctlr->imlock);
813 ctlr->im |= im;
814 csr32w(ctlr, Ims, ctlr->im);
815 iunlock(&ctlr->imlock);
816 }
817
818 static int
igbelim(void * ctlr)819 igbelim(void* ctlr)
820 {
821 return ((Ctlr*)ctlr)->lim != 0;
822 }
823
824 static void
igbelproc(void * arg)825 igbelproc(void* arg)
826 {
827 Ctlr *ctlr;
828 Ether *edev;
829 MiiPhy *phy;
830 int ctrl, r;
831
832 edev = arg;
833 ctlr = edev->ctlr;
834 for(;;){
835 if(ctlr->mii == nil || ctlr->mii->curphy == nil) {
836 sched();
837 continue;
838 }
839
840 /*
841 * To do:
842 * logic to manage status change,
843 * this is incomplete but should work
844 * one time to set up the hardware.
845 *
846 * MiiPhy.speed, etc. should be in Mii.
847 */
848 if(miistatus(ctlr->mii) < 0)
849 //continue;
850 goto enable;
851
852 phy = ctlr->mii->curphy;
853 ctrl = csr32r(ctlr, Ctrl);
854
855 switch(ctlr->id){
856 case i82543gc:
857 case i82544ei:
858 case i82544eif:
859 default:
860 if(!(ctrl & Asde)){
861 ctrl &= ~(SspeedMASK|Ilos|Fd);
862 ctrl |= Frcdplx|Frcspd;
863 if(phy->speed == 1000)
864 ctrl |= Sspeed1000;
865 else if(phy->speed == 100)
866 ctrl |= Sspeed100;
867 if(phy->fd)
868 ctrl |= Fd;
869 }
870 break;
871
872 case i82540em:
873 case i82540eplp:
874 case i82547gi:
875 case i82541gi:
876 case i82541gi2:
877 case i82541pi:
878 break;
879 }
880
881 /*
882 * Collision Distance.
883 */
884 r = csr32r(ctlr, Tctl);
885 r &= ~ColdMASK;
886 if(phy->fd)
887 r |= 64<<ColdSHIFT;
888 else
889 r |= 512<<ColdSHIFT;
890 csr32w(ctlr, Tctl, r);
891
892 /*
893 * Flow control.
894 */
895 if(phy->rfc)
896 ctrl |= Rfce;
897 if(phy->tfc)
898 ctrl |= Tfce;
899 csr32w(ctlr, Ctrl, ctrl);
900
901 enable:
902 ctlr->lim = 0;
903 igbeim(ctlr, Lsc);
904
905 ctlr->lsleep++;
906 sleep(&ctlr->lrendez, igbelim, ctlr);
907 }
908 }
909
910 static void
igbetxinit(Ctlr * ctlr)911 igbetxinit(Ctlr* ctlr)
912 {
913 int i, r;
914 Block *bp;
915
916 csr32w(ctlr, Tctl, (0x0F<<CtSHIFT)|Psp|(66<<ColdSHIFT));
917 switch(ctlr->id){
918 default:
919 r = 6;
920 break;
921 case i82543gc:
922 case i82544ei:
923 case i82544eif:
924 case i82544gc:
925 case i82540em:
926 case i82540eplp:
927 case i82541ei:
928 case i82541gi:
929 case i82541gi2:
930 case i82541pi:
931 case i82545em:
932 case i82545gmc:
933 case i82546gb:
934 case i82546eb:
935 case i82547ei:
936 case i82547gi:
937 r = 8;
938 break;
939 }
940 csr32w(ctlr, Tipg, (6<<20)|(8<<10)|r);
941 csr32w(ctlr, Ait, 0);
942 csr32w(ctlr, Txdmac, 0);
943
944 csr32w(ctlr, Tdbal, PCIWADDR(ctlr->tdba));
945 csr32w(ctlr, Tdbah, 0);
946 csr32w(ctlr, Tdlen, ctlr->ntd*sizeof(Td));
947 ctlr->tdh = PREV(0, ctlr->ntd);
948 csr32w(ctlr, Tdh, 0);
949 ctlr->tdt = 0;
950 csr32w(ctlr, Tdt, 0);
951
952 for(i = 0; i < ctlr->ntd; i++){
953 if((bp = ctlr->tb[i]) != nil){
954 ctlr->tb[i] = nil;
955 freeb(bp);
956 }
957 memset(&ctlr->tdba[i], 0, sizeof(Td));
958 }
959 ctlr->tdfree = ctlr->ntd;
960
961 csr32w(ctlr, Tidv, 128);
962 r = (4<<WthreshSHIFT)|(4<<HthreshSHIFT)|(8<<PthreshSHIFT);
963
964 switch(ctlr->id){
965 default:
966 break;
967 case i82540em:
968 case i82540eplp:
969 case i82547gi:
970 case i82545em:
971 case i82545gmc:
972 case i82546gb:
973 case i82546eb:
974 case i82541gi:
975 case i82541gi2:
976 case i82541pi:
977 r = csr32r(ctlr, Txdctl);
978 r &= ~WthreshMASK;
979 r |= Gran|(4<<WthreshSHIFT);
980
981 csr32w(ctlr, Tadv, 64);
982 break;
983 }
984
985 csr32w(ctlr, Txdctl, r);
986
987 r = csr32r(ctlr, Tctl);
988 r |= Ten;
989 csr32w(ctlr, Tctl, r);
990 }
991
992 static void
igbetransmit(Ether * edev)993 igbetransmit(Ether* edev)
994 {
995 Td *td;
996 Block *bp;
997 Ctlr *ctlr;
998 int tdh, tdt;
999
1000 ctlr = edev->ctlr;
1001
1002 ilock(&ctlr->tlock);
1003
1004 /*
1005 * Free any completed packets
1006 */
1007 tdh = ctlr->tdh;
1008 while(NEXT(tdh, ctlr->ntd) != csr32r(ctlr, Tdh)){
1009 if((bp = ctlr->tb[tdh]) != nil){
1010 ctlr->tb[tdh] = nil;
1011 freeb(bp);
1012 }
1013 memset(&ctlr->tdba[tdh], 0, sizeof(Td));
1014 tdh = NEXT(tdh, ctlr->ntd);
1015 }
1016 ctlr->tdh = tdh;
1017
1018 /*
1019 * Try to fill the ring back up.
1020 */
1021 tdt = ctlr->tdt;
1022 while(NEXT(tdt, ctlr->ntd) != tdh){
1023 if((bp = qget(edev->oq)) == nil)
1024 break;
1025 td = &ctlr->tdba[tdt];
1026 td->addr[0] = PCIWADDR(bp->rp);
1027 td->control = ((BLEN(bp) & LenMASK)<<LenSHIFT);
1028 td->control |= Dext|Ifcs|Teop|DtypeDD;
1029 ctlr->tb[tdt] = bp;
1030 /* note size of queue of tds awaiting transmission */
1031 notemark(&ctlr->wmtd, (tdt + Ntd - tdh) % Ntd);
1032 tdt = NEXT(tdt, ctlr->ntd);
1033 if(NEXT(tdt, ctlr->ntd) == tdh){
1034 td->control |= Rs;
1035 ctlr->txdw++;
1036 ctlr->tdt = tdt;
1037 csr32w(ctlr, Tdt, tdt);
1038 igbeim(ctlr, Txdw);
1039 break;
1040 }
1041 ctlr->tdt = tdt;
1042 csr32w(ctlr, Tdt, tdt);
1043 }
1044
1045 iunlock(&ctlr->tlock);
1046 }
1047
1048 static void
igbereplenish(Ctlr * ctlr)1049 igbereplenish(Ctlr* ctlr)
1050 {
1051 Rd *rd;
1052 int rdt;
1053 Block *bp;
1054
1055 rdt = ctlr->rdt;
1056 while(NEXT(rdt, ctlr->nrd) != ctlr->rdh){
1057 rd = &ctlr->rdba[rdt];
1058 if(ctlr->rb[rdt] == nil){
1059 bp = igberballoc();
1060 if(bp == nil){
1061 iprint("#l%d: igbereplenish: no available buffers\n",
1062 ctlr->edev->ctlrno);
1063 break;
1064 }
1065 ctlr->rb[rdt] = bp;
1066 rd->addr[0] = PCIWADDR(bp->rp);
1067 rd->addr[1] = 0;
1068 }
1069 coherence();
1070 rd->status = 0;
1071 rdt = NEXT(rdt, ctlr->nrd);
1072 ctlr->rdfree++;
1073 }
1074 ctlr->rdt = rdt;
1075 csr32w(ctlr, Rdt, rdt);
1076 }
1077
1078 static void
igberxinit(Ctlr * ctlr)1079 igberxinit(Ctlr* ctlr)
1080 {
1081 int i;
1082 Block *bp;
1083
1084 /* temporarily keep Mpe on */
1085 csr32w(ctlr, Rctl, Dpf|Bsize2048|Bam|RdtmsHALF|Mpe);
1086
1087 csr32w(ctlr, Rdbal, PCIWADDR(ctlr->rdba));
1088 csr32w(ctlr, Rdbah, 0);
1089 csr32w(ctlr, Rdlen, ctlr->nrd*sizeof(Rd));
1090 ctlr->rdh = 0;
1091 csr32w(ctlr, Rdh, 0);
1092 ctlr->rdt = 0;
1093 csr32w(ctlr, Rdt, 0);
1094 ctlr->rdtr = 0;
1095 csr32w(ctlr, Rdtr, Fpd|0);
1096
1097 for(i = 0; i < ctlr->nrd; i++){
1098 if((bp = ctlr->rb[i]) != nil){
1099 ctlr->rb[i] = nil;
1100 freeb(bp);
1101 }
1102 }
1103 igbereplenish(ctlr);
1104 nrbfull = 0;
1105
1106 switch(ctlr->id){
1107 case i82540em:
1108 case i82540eplp:
1109 case i82541gi:
1110 case i82541gi2:
1111 case i82541pi:
1112 case i82545em:
1113 case i82545gmc:
1114 case i82546gb:
1115 case i82546eb:
1116 case i82547gi:
1117 csr32w(ctlr, Radv, 64);
1118 break;
1119 }
1120 csr32w(ctlr, Rxdctl, (8<<WthreshSHIFT)|(8<<HthreshSHIFT)|4);
1121
1122 /*
1123 * Disable checksum offload as it has known bugs.
1124 */
1125 csr32w(ctlr, Rxcsum, ETHERHDRSIZE<<PcssSHIFT);
1126 }
1127
1128 static int
igberim(void * ctlr)1129 igberim(void* ctlr)
1130 {
1131 return ((Ctlr*)ctlr)->rim != 0;
1132 }
1133
1134 static void
igberproc(void * arg)1135 igberproc(void* arg)
1136 {
1137 Rd *rd;
1138 Block *bp;
1139 Ctlr *ctlr;
1140 int r, rdh, passed;
1141 Ether *edev;
1142
1143 edev = arg;
1144 ctlr = edev->ctlr;
1145
1146 igberxinit(ctlr);
1147 r = csr32r(ctlr, Rctl);
1148 r |= Ren;
1149 csr32w(ctlr, Rctl, r);
1150 for(;;){
1151 ctlr->rim = 0;
1152 igbeim(ctlr, Rxt0|Rxo|Rxdmt0|Rxseq);
1153 ctlr->rsleep++;
1154 sleep(&ctlr->rrendez, igberim, ctlr);
1155
1156 rdh = ctlr->rdh;
1157 passed = 0;
1158 for(;;){
1159 rd = &ctlr->rdba[rdh];
1160
1161 if(!(rd->status & Rdd))
1162 break;
1163
1164 /*
1165 * Accept eop packets with no errors.
1166 * With no errors and the Ixsm bit set,
1167 * the descriptor status Tpcs and Ipcs bits give
1168 * an indication of whether the checksums were
1169 * calculated and valid.
1170 */
1171 /* ignore checksum offload as it has known bugs. */
1172 rd->errors &= ~(Ipe | Tcpe);
1173 if((rd->status & Reop) && rd->errors == 0){
1174 bp = ctlr->rb[rdh];
1175 ctlr->rb[rdh] = nil;
1176 bp->wp += rd->length;
1177 bp->next = nil;
1178 /* ignore checksum offload as it has known bugs. */
1179 if(0 && !(rd->status & Ixsm)){
1180 ctlr->ixsm++;
1181 if(rd->status & Ipcs){
1182 /*
1183 * IP checksum calculated
1184 * (and valid as errors == 0).
1185 */
1186 ctlr->ipcs++;
1187 bp->flag |= Bipck;
1188 }
1189 if(rd->status & Tcpcs){
1190 /*
1191 * TCP/UDP checksum calculated
1192 * (and valid as errors == 0).
1193 */
1194 ctlr->tcpcs++;
1195 bp->flag |= Btcpck|Budpck;
1196 }
1197 bp->checksum = rd->checksum;
1198 bp->flag |= Bpktck;
1199 }
1200 ilock(&igberblock);
1201 nrbfull++;
1202 iunlock(&igberblock);
1203 notemark(&ctlr->wmrb, nrbfull);
1204 etheriq(edev, bp, 1);
1205 passed++;
1206 }
1207 else if(ctlr->rb[rdh] != nil){
1208 freeb(ctlr->rb[rdh]);
1209 ctlr->rb[rdh] = nil;
1210 }
1211
1212 memset(rd, 0, sizeof(Rd));
1213 coherence();
1214 ctlr->rdfree--;
1215 rdh = NEXT(rdh, ctlr->nrd);
1216 }
1217 ctlr->rdh = rdh;
1218
1219 if(ctlr->rdfree < ctlr->nrd/2 || (ctlr->rim & Rxdmt0))
1220 igbereplenish(ctlr);
1221 /* note how many rds had full buffers */
1222 notemark(&ctlr->wmrd, passed);
1223 }
1224 }
1225
1226 static void
igbeattach(Ether * edev)1227 igbeattach(Ether* edev)
1228 {
1229 Block *bp;
1230 Ctlr *ctlr;
1231 char name[KNAMELEN];
1232
1233 ctlr = edev->ctlr;
1234 ctlr->edev = edev; /* point back to Ether* */
1235 qlock(&ctlr->alock);
1236 if(ctlr->alloc != nil){ /* already allocated? */
1237 qunlock(&ctlr->alock);
1238 return;
1239 }
1240
1241 ctlr->tb = nil;
1242 ctlr->rb = nil;
1243 ctlr->alloc = nil;
1244 ctlr->nrb = 0;
1245 if(waserror()){
1246 while(ctlr->nrb > 0){
1247 bp = igberballoc();
1248 bp->free = nil;
1249 freeb(bp);
1250 ctlr->nrb--;
1251 }
1252 free(ctlr->tb);
1253 ctlr->tb = nil;
1254 free(ctlr->rb);
1255 ctlr->rb = nil;
1256 free(ctlr->alloc);
1257 ctlr->alloc = nil;
1258 qunlock(&ctlr->alock);
1259 nexterror();
1260 }
1261
1262 ctlr->nrd = ROUND(Nrd, 8);
1263 ctlr->ntd = ROUND(Ntd, 8);
1264 ctlr->alloc = malloc(ctlr->nrd*sizeof(Rd)+ctlr->ntd*sizeof(Td) + 127);
1265 if(ctlr->alloc == nil) {
1266 print("igbe: can't allocate ctlr->alloc\n");
1267 error(Enomem);
1268 }
1269 ctlr->rdba = (Rd*)ROUNDUP((uintptr)ctlr->alloc, 128);
1270 ctlr->tdba = (Td*)(ctlr->rdba+ctlr->nrd);
1271
1272 ctlr->rb = malloc(ctlr->nrd*sizeof(Block*));
1273 ctlr->tb = malloc(ctlr->ntd*sizeof(Block*));
1274 if (ctlr->rb == nil || ctlr->tb == nil) {
1275 print("igbe: can't allocate ctlr->rb or ctlr->tb\n");
1276 error(Enomem);
1277 }
1278
1279 for(ctlr->nrb = 0; ctlr->nrb < Nrb; ctlr->nrb++){
1280 if((bp = allocb(Rbsz)) == nil)
1281 break;
1282 bp->free = igberbfree;
1283 freeb(bp);
1284 }
1285 initmark(&ctlr->wmrb, Nrb, "rcv bufs unprocessed");
1286 initmark(&ctlr->wmrd, Nrd-1, "rcv descrs processed at once");
1287 initmark(&ctlr->wmtd, Ntd-1, "xmit descr queue len");
1288
1289 snprint(name, KNAMELEN, "#l%dlproc", edev->ctlrno);
1290 kproc(name, igbelproc, edev);
1291
1292 snprint(name, KNAMELEN, "#l%drproc", edev->ctlrno);
1293 kproc(name, igberproc, edev);
1294
1295 igbetxinit(ctlr);
1296
1297 qunlock(&ctlr->alock);
1298 poperror();
1299 }
1300
1301 static void
igbeinterrupt(Ureg *,void * arg)1302 igbeinterrupt(Ureg*, void* arg)
1303 {
1304 Ctlr *ctlr;
1305 Ether *edev;
1306 int icr, im, txdw;
1307
1308 edev = arg;
1309 ctlr = edev->ctlr;
1310
1311 ilock(&ctlr->imlock);
1312 csr32w(ctlr, Imc, ~0);
1313 im = ctlr->im;
1314 txdw = 0;
1315
1316 while((icr = csr32r(ctlr, Icr) & ctlr->im) != 0){
1317 if(icr & Lsc){
1318 im &= ~Lsc;
1319 ctlr->lim = icr & Lsc;
1320 wakeup(&ctlr->lrendez);
1321 ctlr->lintr++;
1322 }
1323 if(icr & (Rxt0|Rxo|Rxdmt0|Rxseq)){
1324 im &= ~(Rxt0|Rxo|Rxdmt0|Rxseq);
1325 ctlr->rim = icr & (Rxt0|Rxo|Rxdmt0|Rxseq);
1326 wakeup(&ctlr->rrendez);
1327 ctlr->rintr++;
1328 }
1329 if(icr & Txdw){
1330 im &= ~Txdw;
1331 txdw++;
1332 ctlr->tintr++;
1333 }
1334 }
1335
1336 ctlr->im = im;
1337 csr32w(ctlr, Ims, im);
1338 iunlock(&ctlr->imlock);
1339
1340 if(txdw)
1341 igbetransmit(edev);
1342 }
1343
1344 static int
i82543mdior(Ctlr * ctlr,int n)1345 i82543mdior(Ctlr* ctlr, int n)
1346 {
1347 int ctrl, data, i, r;
1348
1349 /*
1350 * Read n bits from the Management Data I/O Interface.
1351 */
1352 ctrl = csr32r(ctlr, Ctrl);
1353 r = (ctrl & ~Mddo)|Mdco;
1354 data = 0;
1355 for(i = n-1; i >= 0; i--){
1356 if(csr32r(ctlr, Ctrl) & Mdd)
1357 data |= (1<<i);
1358 csr32w(ctlr, Ctrl, Mdc|r);
1359 csr32w(ctlr, Ctrl, r);
1360 }
1361 csr32w(ctlr, Ctrl, ctrl);
1362
1363 return data;
1364 }
1365
1366 static int
i82543mdiow(Ctlr * ctlr,int bits,int n)1367 i82543mdiow(Ctlr* ctlr, int bits, int n)
1368 {
1369 int ctrl, i, r;
1370
1371 /*
1372 * Write n bits to the Management Data I/O Interface.
1373 */
1374 ctrl = csr32r(ctlr, Ctrl);
1375 r = Mdco|Mddo|ctrl;
1376 for(i = n-1; i >= 0; i--){
1377 if(bits & (1<<i))
1378 r |= Mdd;
1379 else
1380 r &= ~Mdd;
1381 csr32w(ctlr, Ctrl, Mdc|r);
1382 csr32w(ctlr, Ctrl, r);
1383 }
1384 csr32w(ctlr, Ctrl, ctrl);
1385
1386 return 0;
1387 }
1388
1389 static int
i82543miimir(Mii * mii,int pa,int ra)1390 i82543miimir(Mii* mii, int pa, int ra)
1391 {
1392 int data;
1393 Ctlr *ctlr;
1394
1395 ctlr = mii->ctlr;
1396
1397 /*
1398 * MII Management Interface Read.
1399 *
1400 * Preamble;
1401 * ST+OP+PHYAD+REGAD;
1402 * TA + 16 data bits.
1403 */
1404 i82543mdiow(ctlr, 0xFFFFFFFF, 32);
1405 i82543mdiow(ctlr, 0x1800|(pa<<5)|ra, 14);
1406 data = i82543mdior(ctlr, 18);
1407
1408 if(data & 0x10000)
1409 return -1;
1410
1411 return data & 0xFFFF;
1412 }
1413
1414 static int
i82543miimiw(Mii * mii,int pa,int ra,int data)1415 i82543miimiw(Mii* mii, int pa, int ra, int data)
1416 {
1417 Ctlr *ctlr;
1418
1419 ctlr = mii->ctlr;
1420
1421 /*
1422 * MII Management Interface Write.
1423 *
1424 * Preamble;
1425 * ST+OP+PHYAD+REGAD+TA + 16 data bits;
1426 * Z.
1427 */
1428 i82543mdiow(ctlr, 0xFFFFFFFF, 32);
1429 data &= 0xFFFF;
1430 data |= (0x05<<(5+5+2+16))|(pa<<(5+2+16))|(ra<<(2+16))|(0x02<<16);
1431 i82543mdiow(ctlr, data, 32);
1432
1433 return 0;
1434 }
1435
1436 static int
igbemiimir(Mii * mii,int pa,int ra)1437 igbemiimir(Mii* mii, int pa, int ra)
1438 {
1439 Ctlr *ctlr;
1440 int mdic, timo;
1441
1442 ctlr = mii->ctlr;
1443
1444 csr32w(ctlr, Mdic, MDIrop|(pa<<MDIpSHIFT)|(ra<<MDIrSHIFT));
1445 mdic = 0;
1446 for(timo = 64; timo; timo--){
1447 mdic = csr32r(ctlr, Mdic);
1448 if(mdic & (MDIe|MDIready))
1449 break;
1450 microdelay(1);
1451 }
1452
1453 if((mdic & (MDIe|MDIready)) == MDIready)
1454 return mdic & 0xFFFF;
1455 return -1;
1456 }
1457
1458 static int
igbemiimiw(Mii * mii,int pa,int ra,int data)1459 igbemiimiw(Mii* mii, int pa, int ra, int data)
1460 {
1461 Ctlr *ctlr;
1462 int mdic, timo;
1463
1464 ctlr = mii->ctlr;
1465
1466 data &= MDIdMASK;
1467 csr32w(ctlr, Mdic, MDIwop|(pa<<MDIpSHIFT)|(ra<<MDIrSHIFT)|data);
1468 mdic = 0;
1469 for(timo = 64; timo; timo--){
1470 mdic = csr32r(ctlr, Mdic);
1471 if(mdic & (MDIe|MDIready))
1472 break;
1473 microdelay(1);
1474 }
1475 if((mdic & (MDIe|MDIready)) == MDIready)
1476 return 0;
1477 return -1;
1478 }
1479
1480 static int
igbemii(Ctlr * ctlr)1481 igbemii(Ctlr* ctlr)
1482 {
1483 MiiPhy *phy;
1484 int ctrl, p, r;
1485
1486 r = csr32r(ctlr, Status);
1487 if(r & Tbimode)
1488 return -1;
1489 if((ctlr->mii = malloc(sizeof(Mii))) == nil)
1490 return -1;
1491 ctlr->mii->ctlr = ctlr;
1492
1493 ctrl = csr32r(ctlr, Ctrl);
1494 ctrl |= Slu;
1495
1496 switch(ctlr->id){
1497 case i82543gc:
1498 ctrl |= Frcdplx|Frcspd;
1499 csr32w(ctlr, Ctrl, ctrl);
1500
1501 /*
1502 * The reset pin direction (Mdro) should already
1503 * be set from the EEPROM load.
1504 * If it's not set this configuration is unexpected
1505 * so bail.
1506 */
1507 r = csr32r(ctlr, Ctrlext);
1508 if(!(r & Mdro)) {
1509 print("igbe: 82543gc Mdro not set\n");
1510 return -1;
1511 }
1512 csr32w(ctlr, Ctrlext, r);
1513 delay(20);
1514 r = csr32r(ctlr, Ctrlext);
1515 r &= ~Mdr;
1516 csr32w(ctlr, Ctrlext, r);
1517 delay(20);
1518 r = csr32r(ctlr, Ctrlext);
1519 r |= Mdr;
1520 csr32w(ctlr, Ctrlext, r);
1521 delay(20);
1522
1523 ctlr->mii->mir = i82543miimir;
1524 ctlr->mii->miw = i82543miimiw;
1525 break;
1526 case i82544ei:
1527 case i82544eif:
1528 case i82544gc:
1529 case i82540em:
1530 case i82540eplp:
1531 case i82547ei:
1532 case i82547gi:
1533 case i82541ei:
1534 case i82541gi:
1535 case i82541gi2:
1536 case i82541pi:
1537 case i82545em:
1538 case i82545gmc:
1539 case i82546gb:
1540 case i82546eb:
1541 ctrl &= ~(Frcdplx|Frcspd);
1542 csr32w(ctlr, Ctrl, ctrl);
1543 ctlr->mii->mir = igbemiimir;
1544 ctlr->mii->miw = igbemiimiw;
1545 break;
1546 default:
1547 free(ctlr->mii);
1548 ctlr->mii = nil;
1549 return -1;
1550 }
1551
1552 if(mii(ctlr->mii, ~0) == 0 || (phy = ctlr->mii->curphy) == nil){
1553 free(ctlr->mii);
1554 ctlr->mii = nil;
1555 return -1;
1556 }
1557 USED(phy);
1558 // print("oui %X phyno %d\n", phy->oui, phy->phyno);
1559
1560 /*
1561 * 8254X-specific PHY registers not in 802.3:
1562 * 0x10 PHY specific control
1563 * 0x14 extended PHY specific control
1564 * Set appropriate values then reset the PHY to have
1565 * changes noted.
1566 */
1567 switch(ctlr->id){
1568 case i82547gi:
1569 case i82541gi:
1570 case i82541gi2:
1571 case i82541pi:
1572 case i82545em:
1573 case i82545gmc:
1574 case i82546gb:
1575 case i82546eb:
1576 break;
1577 default:
1578 r = miimir(ctlr->mii, 16);
1579 r |= 0x0800; /* assert CRS on Tx */
1580 r |= 0x0060; /* auto-crossover all speeds */
1581 r |= 0x0002; /* polarity reversal enabled */
1582 miimiw(ctlr->mii, 16, r);
1583
1584 r = miimir(ctlr->mii, 20);
1585 r |= 0x0070; /* +25MHz clock */
1586 r &= ~0x0F00;
1587 r |= 0x0100; /* 1x downshift */
1588 miimiw(ctlr->mii, 20, r);
1589
1590 miireset(ctlr->mii);
1591 p = 0;
1592 if(ctlr->txcw & TxcwPs)
1593 p |= AnaP;
1594 if(ctlr->txcw & TxcwAs)
1595 p |= AnaAP;
1596 miiane(ctlr->mii, ~0, p, ~0);
1597 break;
1598 }
1599 return 0;
1600 }
1601
1602 static int
at93c46io(Ctlr * ctlr,char * op,int data)1603 at93c46io(Ctlr* ctlr, char* op, int data)
1604 {
1605 char *lp, *p;
1606 int i, loop, eecd, r;
1607
1608 eecd = csr32r(ctlr, Eecd);
1609
1610 r = 0;
1611 loop = -1;
1612 lp = nil;
1613 for(p = op; *p != '\0'; p++){
1614 switch(*p){
1615 default:
1616 return -1;
1617 case ' ':
1618 continue;
1619 case ':': /* start of loop */
1620 loop = strtol(p+1, &lp, 0)-1;
1621 lp--;
1622 if(p == lp)
1623 loop = 7;
1624 p = lp;
1625 continue;
1626 case ';': /* end of loop */
1627 if(lp == nil)
1628 return -1;
1629 loop--;
1630 if(loop >= 0)
1631 p = lp;
1632 else
1633 lp = nil;
1634 continue;
1635 case 'C': /* assert clock */
1636 eecd |= Sk;
1637 break;
1638 case 'c': /* deassert clock */
1639 eecd &= ~Sk;
1640 break;
1641 case 'D': /* next bit in 'data' byte */
1642 if(loop < 0)
1643 return -1;
1644 if(data & (1<<loop))
1645 eecd |= Di;
1646 else
1647 eecd &= ~Di;
1648 break;
1649 case 'O': /* collect data output */
1650 i = (csr32r(ctlr, Eecd) & Do) != 0;
1651 if(loop >= 0)
1652 r |= (i<<loop);
1653 else
1654 r = i;
1655 continue;
1656 case 'I': /* assert data input */
1657 eecd |= Di;
1658 break;
1659 case 'i': /* deassert data input */
1660 eecd &= ~Di;
1661 break;
1662 case 'S': /* enable chip select */
1663 eecd |= Cs;
1664 break;
1665 case 's': /* disable chip select */
1666 eecd &= ~Cs;
1667 break;
1668 }
1669 csr32w(ctlr, Eecd, eecd);
1670 microdelay(50);
1671 }
1672 if(loop >= 0)
1673 return -1;
1674 return r;
1675 }
1676
1677 static int
at93c46r(Ctlr * ctlr)1678 at93c46r(Ctlr* ctlr)
1679 {
1680 ushort sum;
1681 char rop[20];
1682 int addr, areq, bits, data, eecd, i;
1683
1684 eecd = csr32r(ctlr, Eecd);
1685 if(eecd & Spi){
1686 print("igbe: SPI EEPROM access not implemented\n");
1687 return 0;
1688 }
1689 if(eecd & (Eeszaddr|Eesz256))
1690 bits = 8;
1691 else
1692 bits = 6;
1693
1694 sum = 0;
1695
1696 switch(ctlr->id){
1697 default:
1698 areq = 0;
1699 break;
1700 case i82540em:
1701 case i82540eplp:
1702 case i82541ei:
1703 case i82541gi:
1704 case i82541gi2:
1705 case i82541pi:
1706 case i82545em:
1707 case i82545gmc:
1708 case i82546gb:
1709 case i82546eb:
1710 case i82547ei:
1711 case i82547gi:
1712 areq = 1;
1713 csr32w(ctlr, Eecd, eecd|Areq);
1714 for(i = 0; i < 1000; i++){
1715 if((eecd = csr32r(ctlr, Eecd)) & Agnt)
1716 break;
1717 microdelay(5);
1718 }
1719 if(!(eecd & Agnt)){
1720 print("igbe: not granted EEPROM access\n");
1721 goto release;
1722 }
1723 break;
1724 }
1725 snprint(rop, sizeof(rop), "S :%dDCc;", bits+3);
1726
1727 for(addr = 0; addr < 0x40; addr++){
1728 /*
1729 * Read a word at address 'addr' from the Atmel AT93C46
1730 * 3-Wire Serial EEPROM or compatible. The EEPROM access is
1731 * controlled by 4 bits in Eecd. See the AT93C46 datasheet
1732 * for protocol details.
1733 */
1734 if(at93c46io(ctlr, rop, (0x06<<bits)|addr) != 0){
1735 print("igbe: can't set EEPROM address 0x%2.2X\n", addr);
1736 goto release;
1737 }
1738 data = at93c46io(ctlr, ":16COc;", 0);
1739 at93c46io(ctlr, "sic", 0);
1740 ctlr->eeprom[addr] = data;
1741 sum += data;
1742 }
1743
1744 release:
1745 if(areq)
1746 csr32w(ctlr, Eecd, eecd & ~Areq);
1747 return sum;
1748 }
1749
1750 static int
igbedetach(Ctlr * ctlr)1751 igbedetach(Ctlr* ctlr)
1752 {
1753 int r, timeo;
1754
1755 /*
1756 * Perform a device reset to get the chip back to the
1757 * power-on state, followed by an EEPROM reset to read
1758 * the defaults for some internal registers.
1759 */
1760 csr32w(ctlr, Imc, ~0);
1761 csr32w(ctlr, Rctl, 0);
1762 csr32w(ctlr, Tctl, 0);
1763
1764 delay(10);
1765
1766 csr32w(ctlr, Ctrl, Devrst);
1767 delay(1);
1768 for(timeo = 0; timeo < 1000; timeo++){
1769 if(!(csr32r(ctlr, Ctrl) & Devrst))
1770 break;
1771 delay(1);
1772 }
1773 if(csr32r(ctlr, Ctrl) & Devrst)
1774 return -1;
1775 r = csr32r(ctlr, Ctrlext);
1776 csr32w(ctlr, Ctrlext, r|Eerst);
1777 delay(1);
1778 for(timeo = 0; timeo < 1000; timeo++){
1779 if(!(csr32r(ctlr, Ctrlext) & Eerst))
1780 break;
1781 delay(1);
1782 }
1783 if(csr32r(ctlr, Ctrlext) & Eerst)
1784 return -1;
1785
1786 switch(ctlr->id){
1787 default:
1788 break;
1789 case i82540em:
1790 case i82540eplp:
1791 case i82541gi:
1792 case i82541gi2:
1793 case i82541pi:
1794 case i82545em:
1795 case i82545gmc:
1796 case i82547gi:
1797 case i82546gb:
1798 case i82546eb:
1799 r = csr32r(ctlr, Manc);
1800 r &= ~Arpen;
1801 csr32w(ctlr, Manc, r);
1802 break;
1803 }
1804
1805 csr32w(ctlr, Imc, ~0);
1806 delay(1);
1807 for(timeo = 0; timeo < 1000; timeo++){
1808 if(!csr32r(ctlr, Icr))
1809 break;
1810 delay(1);
1811 }
1812 if(csr32r(ctlr, Icr))
1813 return -1;
1814
1815 return 0;
1816 }
1817
1818 static void
igbeshutdown(Ether * ether)1819 igbeshutdown(Ether* ether)
1820 {
1821 igbedetach(ether->ctlr);
1822 }
1823
1824 static int
igbereset(Ctlr * ctlr)1825 igbereset(Ctlr* ctlr)
1826 {
1827 int ctrl, i, pause, r, swdpio, txcw;
1828
1829 if(igbedetach(ctlr))
1830 return -1;
1831
1832 /*
1833 * Read the EEPROM, validate the checksum
1834 * then get the device back to a power-on state.
1835 */
1836 if((r = at93c46r(ctlr)) != 0xBABA){
1837 print("igbe: bad EEPROM checksum - 0x%4.4uX\n", r);
1838 return -1;
1839 }
1840
1841 /*
1842 * Snarf and set up the receive addresses.
1843 * There are 16 addresses. The first should be the MAC address.
1844 * The others are cleared and not marked valid (MS bit of Rah).
1845 */
1846 if ((ctlr->id == i82546gb || ctlr->id == i82546eb) &&
1847 BUSFNO(ctlr->pcidev->tbdf) == 1)
1848 ctlr->eeprom[Ea+2] += 0x100; /* second interface */
1849 if(ctlr->id == i82541gi && ctlr->eeprom[Ea] == 0xFFFF)
1850 ctlr->eeprom[Ea] = 0xD000;
1851 for(i = Ea; i < Eaddrlen/2; i++){
1852 ctlr->ra[2*i] = ctlr->eeprom[i];
1853 ctlr->ra[2*i+1] = ctlr->eeprom[i]>>8;
1854 }
1855 /* lan id seems to vary on 82543gc; don't use it */
1856 if (ctlr->id != i82543gc) {
1857 r = (csr32r(ctlr, Status) & Lanid) >> 2;
1858 ctlr->ra[5] += r; /* ea ctlr[1] = ea ctlr[0]+1 */
1859 }
1860
1861 r = (ctlr->ra[3]<<24)|(ctlr->ra[2]<<16)|(ctlr->ra[1]<<8)|ctlr->ra[0];
1862 csr32w(ctlr, Ral, r);
1863 r = 0x80000000|(ctlr->ra[5]<<8)|ctlr->ra[4];
1864 csr32w(ctlr, Rah, r);
1865 for(i = 1; i < 16; i++){
1866 csr32w(ctlr, Ral+i*8, 0);
1867 csr32w(ctlr, Rah+i*8, 0);
1868 }
1869
1870 /*
1871 * Clear the Multicast Table Array.
1872 * It's a 4096 bit vector accessed as 128 32-bit registers.
1873 */
1874 memset(ctlr->mta, 0, sizeof(ctlr->mta));
1875 for(i = 0; i < 128; i++)
1876 csr32w(ctlr, Mta+i*4, 0);
1877
1878 /*
1879 * Just in case the Eerst didn't load the defaults
1880 * (doesn't appear to fully on the 82543GC), do it manually.
1881 */
1882 if (ctlr->id == i82543gc) {
1883 txcw = csr32r(ctlr, Txcw);
1884 txcw &= ~(TxcwAne|TxcwPauseMASK|TxcwFd);
1885 ctrl = csr32r(ctlr, Ctrl);
1886 ctrl &= ~(SwdpioloMASK|Frcspd|Ilos|Lrst|Fd);
1887
1888 if(ctlr->eeprom[Icw1] & 0x0400){
1889 ctrl |= Fd;
1890 txcw |= TxcwFd;
1891 }
1892 if(ctlr->eeprom[Icw1] & 0x0200)
1893 ctrl |= Lrst;
1894 if(ctlr->eeprom[Icw1] & 0x0010)
1895 ctrl |= Ilos;
1896 if(ctlr->eeprom[Icw1] & 0x0800)
1897 ctrl |= Frcspd;
1898 swdpio = (ctlr->eeprom[Icw1] & 0x01E0)>>5;
1899 ctrl |= swdpio<<SwdpioloSHIFT;
1900 csr32w(ctlr, Ctrl, ctrl);
1901
1902 ctrl = csr32r(ctlr, Ctrlext);
1903 ctrl &= ~(Ips|SwdpiohiMASK);
1904 swdpio = (ctlr->eeprom[Icw2] & 0x00F0)>>4;
1905 if(ctlr->eeprom[Icw1] & 0x1000)
1906 ctrl |= Ips;
1907 ctrl |= swdpio<<SwdpiohiSHIFT;
1908 csr32w(ctlr, Ctrlext, ctrl);
1909
1910 if(ctlr->eeprom[Icw2] & 0x0800)
1911 txcw |= TxcwAne;
1912 pause = (ctlr->eeprom[Icw2] & 0x3000)>>12;
1913 txcw |= pause<<TxcwPauseSHIFT;
1914 switch(pause){
1915 default:
1916 ctlr->fcrtl = 0x00002000;
1917 ctlr->fcrth = 0x00004000;
1918 txcw |= TxcwAs|TxcwPs;
1919 break;
1920 case 0:
1921 ctlr->fcrtl = 0x00002000;
1922 ctlr->fcrth = 0x00004000;
1923 break;
1924 case 2:
1925 ctlr->fcrtl = 0;
1926 ctlr->fcrth = 0;
1927 txcw |= TxcwAs;
1928 break;
1929 }
1930 ctlr->txcw = txcw;
1931 csr32w(ctlr, Txcw, txcw);
1932 }
1933
1934
1935 /*
1936 * Flow control - values from the datasheet.
1937 */
1938 csr32w(ctlr, Fcal, 0x00C28001);
1939 csr32w(ctlr, Fcah, 0x00000100);
1940 csr32w(ctlr, Fct, 0x00008808);
1941 csr32w(ctlr, Fcttv, 0x00000100);
1942
1943 csr32w(ctlr, Fcrtl, ctlr->fcrtl);
1944 csr32w(ctlr, Fcrth, ctlr->fcrth);
1945
1946 if(!(csr32r(ctlr, Status) & Tbimode) && igbemii(ctlr) < 0)
1947 return -1;
1948
1949 return 0;
1950 }
1951
1952 static void
igbepci(void)1953 igbepci(void)
1954 {
1955 int cls;
1956 Pcidev *p;
1957 Ctlr *ctlr;
1958 void *mem;
1959
1960 p = nil;
1961 while(p = pcimatch(p, 0, 0)){
1962 if(p->ccrb != 0x02 || p->ccru != 0)
1963 continue;
1964
1965 switch((p->did<<16)|p->vid){
1966 default:
1967 continue;
1968 case i82543gc:
1969 case i82544ei:
1970 case i82544eif:
1971 case i82544gc:
1972 case i82547ei:
1973 case i82547gi:
1974 case i82540em:
1975 case i82540eplp:
1976 case i82541ei:
1977 case i82541gi:
1978 case i82541gi2:
1979 case i82541pi:
1980 case i82545em:
1981 case i82545gmc:
1982 case i82546gb:
1983 case i82546eb:
1984 break;
1985 }
1986
1987 mem = vmap(p->mem[0].bar & ~0x0F, p->mem[0].size);
1988 if(mem == nil){
1989 print("igbe: can't map %8.8luX\n", p->mem[0].bar);
1990 continue;
1991 }
1992 cls = pcicfgr8(p, PciCLS);
1993 switch(cls){
1994 default:
1995 print("igbe: p->cls %#ux, setting to 0x10\n", p->cls);
1996 p->cls = 0x10;
1997 pcicfgw8(p, PciCLS, p->cls);
1998 break;
1999 case 0x08:
2000 case 0x10:
2001 break;
2002 }
2003 ctlr = malloc(sizeof(Ctlr));
2004 if(ctlr == nil) {
2005 vunmap(mem, p->mem[0].size);
2006 error(Enomem);
2007 }
2008 ctlr->port = p->mem[0].bar & ~0x0F;
2009 ctlr->pcidev = p;
2010 ctlr->id = (p->did<<16)|p->vid;
2011 ctlr->cls = cls*4;
2012 ctlr->nic = mem;
2013
2014 if(igbereset(ctlr)){
2015 free(ctlr);
2016 vunmap(mem, p->mem[0].size);
2017 continue;
2018 }
2019 pcisetbme(p);
2020
2021 if(igbectlrhead != nil)
2022 igbectlrtail->next = ctlr;
2023 else
2024 igbectlrhead = ctlr;
2025 igbectlrtail = ctlr;
2026 }
2027 }
2028
2029 static int
igbepnp(Ether * edev)2030 igbepnp(Ether* edev)
2031 {
2032 Ctlr *ctlr;
2033
2034 if(igbectlrhead == nil)
2035 igbepci();
2036
2037 /*
2038 * Any adapter matches if no edev->port is supplied,
2039 * otherwise the ports must match.
2040 */
2041 for(ctlr = igbectlrhead; ctlr != nil; ctlr = ctlr->next){
2042 if(ctlr->active)
2043 continue;
2044 if(edev->port == 0 || edev->port == ctlr->port){
2045 ctlr->active = 1;
2046 break;
2047 }
2048 }
2049 if(ctlr == nil)
2050 return -1;
2051
2052 edev->ctlr = ctlr;
2053 edev->port = ctlr->port;
2054 edev->irq = ctlr->pcidev->intl;
2055 edev->tbdf = ctlr->pcidev->tbdf;
2056 edev->mbps = 1000;
2057 memmove(edev->ea, ctlr->ra, Eaddrlen);
2058
2059 /*
2060 * Linkage to the generic ethernet driver.
2061 */
2062 edev->attach = igbeattach;
2063 edev->transmit = igbetransmit;
2064 edev->interrupt = igbeinterrupt;
2065 edev->ifstat = igbeifstat;
2066 edev->ctl = igbectl;
2067
2068 edev->arg = edev;
2069 edev->promiscuous = igbepromiscuous;
2070 edev->shutdown = igbeshutdown;
2071 edev->multicast = igbemulticast;
2072
2073 return 0;
2074 }
2075
2076 void
etherigbelink(void)2077 etherigbelink(void)
2078 {
2079 addethercard("i82543", igbepnp);
2080 addethercard("igbe", igbepnp);
2081 }
2082
2083