1 /*
2 * Netgear GA620 Gigabit Ethernet Card.
3 * Specific for the Alteon Tigon 2 and Intel Pentium or later.
4 * To Do:
5 * cache alignment for PCI Write-and-Invalidate
6 * mini ring (what size)?
7 * tune coalescing values
8 * statistics formatting
9 * don't update Spi if nothing to send
10 * receive ring alignment
11 * watchdog for link management?
12 */
13 #include "u.h"
14 #include "../port/lib.h"
15 #include "mem.h"
16 #include "dat.h"
17 #include "fns.h"
18 #include "io.h"
19 #include "../port/error.h"
20 #include "../port/netif.h"
21
22 #define malign(n) xspanalloc((n), 32, 0)
23
24 #include "etherif.h"
25 #include "etherga620fw.h"
26
27 enum {
28 Mhc = 0x0040, /* Miscellaneous Host Control */
29 Mlc = 0x0044, /* Miscellaneous Local Control */
30 Mc = 0x0050, /* Miscellaneous Configuration */
31 Ps = 0x005C, /* PCI State */
32 Wba = 0x0068, /* Window Base Address */
33 Wd = 0x006C, /* Window Data */
34
35 DMAas = 0x011C, /* DMA Assist State */
36
37 CPUAstate = 0x0140, /* CPU A State */
38 CPUApc = 0x0144, /* CPU A Programme Counter */
39
40 CPUBstate = 0x0240, /* CPU B State */
41
42 Hi = 0x0504, /* Host In Interrupt Handler */
43 Cpi = 0x050C, /* Command Producer Index */
44 Spi = 0x0514, /* Send Producer Index */
45 Rspi = 0x051C, /* Receive Standard Producer Index */
46 Rjpi = 0x0524, /* Receive Jumbo Producer Index */
47 Rmpi = 0x052C, /* Receive Mini Producer Index */
48
49 Mac = 0x0600, /* MAC Address */
50 Gip = 0x0608, /* General Information Pointer */
51 Om = 0x0618, /* Operating Mode */
52 DMArc = 0x061C, /* DMA Read Configuration */
53 DMAwc = 0x0620, /* DMA Write Configuration */
54 Tbr = 0x0624, /* Transmit Buffer Ratio */
55 Eci = 0x0628, /* Event Consumer Index */
56 Cci = 0x062C, /* Command Consumer Index */
57
58 Rct = 0x0630, /* Receive Coalesced Ticks */
59 Sct = 0x0634, /* Send Coalesced Ticks */
60 St = 0x0638, /* Stat Ticks */
61 SmcBD = 0x063C, /* Send Max. Coalesced BDs */
62 RmcBD = 0x0640, /* Receive Max. Coalesced BDs */
63 Nt = 0x0644, /* NIC Tracing */
64 Gln = 0x0648, /* Gigabit Link Negotiation */
65 Fln = 0x064C, /* 10/100 Link Negotiation */
66 Ifx = 0x065C, /* Interface Index */
67 IfMTU = 0x0660, /* Interface MTU */
68 Mi = 0x0664, /* Mask Interrupts */
69 Gls = 0x0668, /* Gigabit Link State */
70 Fls = 0x066C, /* 10/100 Link State */
71
72 Cr = 0x0700, /* Command Ring */
73
74 Lmw = 0x0800, /* Local Memory Window */
75 };
76
77 enum { /* Mhc */
78 Is = 0x00000001, /* Interrupt State */
79 Ci = 0x00000002, /* Clear Interrupt */
80 Hr = 0x00000008, /* Hard Reset */
81 Eebs = 0x00000010, /* Enable Endian Byte Swap */
82 Eews = 0x00000020, /* Enable Endian Word (64-bit) swap */
83 Mpio = 0x00000040, /* Mask PCI Interrupt Output */
84 };
85
86 enum { /* Mlc */
87 SRAM512 = 0x00000200, /* SRAM Bank Size of 512KB */
88 SRAMmask = 0x00000300,
89 EEclk = 0x00100000, /* Serial EEPROM Clock Output */
90 EEdoe = 0x00200000, /* Serial EEPROM Data Out Enable */
91 EEdo = 0x00400000, /* Serial EEPROM Data Out Value */
92 EEdi = 0x00800000, /* Serial EEPROM Data Input */
93 };
94
95 enum { /* Mc */
96 SyncSRAM = 0x00100000, /* Set Synchronous SRAM Timing */
97 };
98
99 enum { /* Ps */
100 PCIwm32 = 0x000000C0, /* Write Max DMA 32 */
101 PCImrm = 0x00020000, /* Use Memory Read Multiple Command */
102 PCI66 = 0x00080000,
103 PCI32 = 0x00100000,
104 PCIrcmd = 0x06000000, /* PCI Read Command */
105 PCIwcmd = 0x70000000, /* PCI Write Command */
106 };
107
108 enum { /* CPUAstate */
109 CPUrf = 0x00000010, /* ROM Fail */
110 CPUhalt = 0x00010000, /* Halt the internal CPU */
111 CPUhie = 0x00040000, /* HALT instruction executed */
112 };
113
114 enum { /* Om */
115 BswapBD = 0x00000002, /* Byte Swap Buffer Descriptors */
116 WswapBD = 0x00000004, /* Word Swap Buffer Descriptors */
117 Warn = 0x00000008,
118 BswapDMA = 0x00000010, /* Byte Swap DMA Data */
119 Only1DMA = 0x00000040, /* Only One DMA Active at a time */
120 NoJFrag = 0x00000200, /* Don't Fragment Jumbo Frames */
121 Fatal = 0x40000000,
122 };
123
124 enum { /* Lmw */
125 Lmwsz = 2*1024, /* Local Memory Window Size */
126
127 /*
128 * legal values are 0x3800 iff Nsr is 128, 0x3000 iff Nsr is 256,
129 * or 0x2000 iff Nsr is 512.
130 */
131 Sr = 0x2000, /* Send Ring (accessed via Lmw) */
132 };
133
134 enum { /* Link */
135 Lpref = 0x00008000, /* Preferred Link */
136 L10MB = 0x00010000,
137 L100MB = 0x00020000,
138 L1000MB = 0x00040000,
139 Lfd = 0x00080000, /* Full Duplex */
140 Lhd = 0x00100000, /* Half Duplex */
141 Lefc = 0x00200000, /* Emit Flow Control Packets */
142 Lofc = 0x00800000, /* Obey Flow Control Packets */
143 Lean = 0x20000000, /* Enable Autonegotiation/Sensing */
144 Le = 0x40000000, /* Link Enable */
145 };
146
147 typedef struct Host64 {
148 uint hi;
149 uint lo;
150 } Host64;
151
152 typedef struct Ere { /* Event Ring Element */
153 int event; /* event<<24 | code<<12 | index */
154 int unused;
155 } Ere;
156
157 typedef int Cmd; /* cmd<<24 | flags<<12 | index */
158
159 typedef struct Rbd { /* Receive Buffer Descriptor */
160 Host64 addr;
161 int indexlen; /* ring-index<<16 | buffer-length */
162 int flags; /* only lower 16-bits */
163 int checksum; /* ip<<16 | tcp/udp */
164 int error; /* only upper 16-bits */
165 int reserved;
166 void* opaque; /* passed to receive return ring */
167 } Rbd;
168
169 typedef struct Sbd { /* Send Buffer Descriptor */
170 Host64 addr;
171 int lenflags; /* len<<16 | flags */
172 int reserved;
173 } Sbd;
174
175 enum { /* Buffer Descriptor Flags */
176 Fend = 0x00000004, /* Frame Ends in this Buffer */
177 Frjr = 0x00000010, /* Receive Jumbo Ring Buffer */
178 Funicast = 0x00000020, /* Unicast packet (2-bit field) */
179 Fmulticast = 0x00000040, /* Multicast packet */
180 Fbroadcast = 0x00000060, /* Broadcast packet */
181 Ferror = 0x00000400, /* Frame Has Error */
182 Frmr = 0x00001000, /* Receive Mini Ring Buffer */
183 };
184
185 enum { /* Buffer Error Flags */
186 Ecrc = 0x00010000, /* bad CRC */
187 Ecollision = 0x00020000, /* collision */
188 Elink = 0x00040000, /* link lost */
189 Ephy = 0x00080000, /* unspecified PHY frame decode error */
190 Eodd = 0x00100000, /* odd number of nibbles */
191 Emac = 0x00200000, /* unspecified MAC abort */
192 Elen64 = 0x00400000, /* short packet */
193 Eresources = 0x00800000, /* MAC out of internal resources */
194 Egiant = 0x01000000, /* packet too big */
195 };
196
197 typedef struct Rcb { /* Ring Control Block */
198 Host64 addr; /* points to the Rbd ring */
199 int control; /* max_len<<16 | flags */
200 int unused;
201 } Rcb;
202
203 enum {
204 TcpUdpCksum = 0x0001, /* Perform TCP or UDP checksum */
205 IpCksum = 0x0002, /* Perform IP checksum */
206 NoPseudoHdrCksum= 0x0008, /* Don't include the pseudo header */
207 VlanAssist = 0x0010, /* Enable VLAN tagging */
208 CoalUpdateOnly = 0x0020, /* Coalesce transmit interrupts */
209 HostRing = 0x0040, /* Sr in host memory */
210 SnapCksum = 0x0080, /* Parse + offload 802.3 SNAP frames */
211 UseExtRxBd = 0x0100, /* Extended Rbd for Jumbo frames */
212 RingDisabled = 0x0200, /* Jumbo or Mini RCB only */
213 };
214
215 typedef struct Gib { /* General Information Block */
216 int statistics[256]; /* Statistics */
217 Rcb ercb; /* Event Ring */
218 Rcb crcb; /* Command Ring */
219 Rcb srcb; /* Send Ring */
220 Rcb rsrcb; /* Receive Standard Ring */
221 Rcb rjrcb; /* Receive Jumbo Ring */
222 Rcb rmrcb; /* Receive Mini Ring */
223 Rcb rrrcb; /* Receive Return Ring */
224 Host64 epp; /* Event Producer */
225 Host64 rrrpp; /* Receive Return Ring Producer */
226 Host64 scp; /* Send Consumer */
227 Host64 rsp; /* Refresh Stats */
228 } Gib;
229
230 /*
231 * these sizes are all fixed in the card,
232 * except for Nsr, which has only 3 valid sizes.
233 */
234 enum { /* Host/NIC Interface ring sizes */
235 Ner = 256, /* event ring */
236 Ncr = 64, /* command ring */
237 Nsr = 512, /* send ring: 128, 256 or 512 */
238 Nrsr = 512, /* receive standard ring */
239 Nrjr = 256, /* receive jumbo ring */
240 Nrmr = 1024, /* receive mini ring, optional */
241 Nrrr = 2048, /* receive return ring */
242 };
243
244 enum {
245 NrsrHI = 72, /* Fill-level of Rsr (m.b. < Nrsr) */
246 NrsrLO = 54, /* Level at which to top-up ring */
247 NrjrHI = 0, /* Fill-level of Rjr (m.b. < Nrjr) */
248 NrjrLO = 0, /* Level at which to top-up ring */
249 NrmrHI = 0, /* Fill-level of Rmr (m.b. < Nrmr) */
250 NrmrLO = 0, /* Level at which to top-up ring */
251 };
252
253 typedef struct Ctlr Ctlr;
254 struct Ctlr {
255 int port;
256 Pcidev* pcidev;
257 Ctlr* next;
258 int active;
259 int id;
260
261 uchar ea[Eaddrlen];
262
263 int* nic;
264 Gib* gib;
265
266 Ere* er;
267
268 Lock srlock;
269 Sbd* sr;
270 Block** srb;
271 int nsr; /* currently in send ring */
272
273 Rbd* rsr;
274 int nrsr; /* currently in Receive Standard Ring */
275 Rbd* rjr;
276 int nrjr; /* currently in Receive Jumbo Ring */
277 Rbd* rmr;
278 int nrmr; /* currently in Receive Mini Ring */
279 Rbd* rrr;
280 int rrrci; /* Receive Return Ring Consumer Index */
281
282 int epi[2]; /* Event Producer Index */
283 int rrrpi[2]; /* Receive Return Ring Producer Index */
284 int sci[3]; /* Send Consumer Index ([2] is host) */
285
286 int interrupts; /* statistics */
287 int mi;
288 uvlong ticks;
289
290 int coalupdateonly; /* tuning */
291 int hardwarecksum;
292 int rct; /* Receive Coalesce Ticks */
293 int sct; /* Send Coalesce Ticks */
294 int st; /* Stat Ticks */
295 int smcbd; /* Send Max. Coalesced BDs */
296 int rmcbd; /* Receive Max. Coalesced BDs */
297 };
298
299 static Ctlr* ctlrhead;
300 static Ctlr* ctlrtail;
301
302 #define csr32r(c, r) (*((c)->nic+((r)/4)))
303 #define csr32w(c, r, v) (*((c)->nic+((r)/4)) = (v))
304
305 static void
sethost64(Host64 * host64,void * addr)306 sethost64(Host64* host64, void* addr)
307 {
308 uvlong uvl;
309
310 uvl = PCIWADDR(addr);
311 host64->hi = uvl>>32;
312 host64->lo = uvl & 0xFFFFFFFFL;
313 }
314
315 static void
ga620command(Ctlr * ctlr,int cmd,int flags,int index)316 ga620command(Ctlr* ctlr, int cmd, int flags, int index)
317 {
318 int cpi;
319
320 cpi = csr32r(ctlr, Cpi);
321 csr32w(ctlr, Cr+(cpi*4), cmd<<24 | flags<<12 | index);
322 cpi = NEXT(cpi, Ncr);
323 csr32w(ctlr, Cpi, cpi);
324 }
325
326 static void
ga620attach(Ether * edev)327 ga620attach(Ether* edev)
328 {
329 Ctlr *ctlr;
330
331 ctlr = edev->ctlr;
332 USED(ctlr);
333 }
334
335 static long
ga620ifstat(Ether * edev,void * a,long n,ulong offset)336 ga620ifstat(Ether* edev, void* a, long n, ulong offset)
337 {
338 char *p;
339 Ctlr *ctlr;
340 int i, l, r;
341
342 ctlr = edev->ctlr;
343
344 if(n == 0)
345 return 0;
346 p = malloc(READSTR);
347 if(p == nil)
348 error(Enomem);
349 l = 0;
350 for(i = 0; i < 256; i++){
351 if((r = ctlr->gib->statistics[i]) == 0)
352 continue;
353 l += snprint(p+l, READSTR-l, "%d: %ud\n", i, r);
354 }
355
356 l += snprint(p+l, READSTR-l, "interrupts: %ud\n", ctlr->interrupts);
357 l += snprint(p+l, READSTR-l, "mi: %ud\n", ctlr->mi);
358 l += snprint(p+l, READSTR-l, "ticks: %llud\n", ctlr->ticks);
359 l += snprint(p+l, READSTR-l, "coalupdateonly: %d\n", ctlr->coalupdateonly);
360 l += snprint(p+l, READSTR-l, "hardwarecksum: %d\n", ctlr->hardwarecksum);
361 l += snprint(p+l, READSTR-l, "rct: %d\n", ctlr->rct);
362 l += snprint(p+l, READSTR-l, "sct: %d\n", ctlr->sct);
363 l += snprint(p+l, READSTR-l, "smcbd: %d\n", ctlr->smcbd);
364 snprint(p+l, READSTR-l, "rmcbd: %d\n", ctlr->rmcbd);
365
366 n = readstr(offset, a, n, p);
367 free(p);
368
369 return n;
370 }
371
372 static long
ga620ctl(Ether * edev,void * buf,long n)373 ga620ctl(Ether* edev, void* buf, long n)
374 {
375 char *p;
376 Cmdbuf *cb;
377 Ctlr *ctlr;
378 int control, i, r;
379
380 ctlr = edev->ctlr;
381 if(ctlr == nil)
382 error(Enonexist);
383 r = 0;
384 cb = parsecmd(buf, n);
385 if(cb->nf < 2)
386 r = -1;
387 else if(cistrcmp(cb->f[0], "coalupdateonly") == 0){
388 if(cistrcmp(cb->f[1], "off") == 0){
389 control = ctlr->gib->srcb.control;
390 control &= ~CoalUpdateOnly;
391 ctlr->gib->srcb.control = control;
392 ctlr->coalupdateonly = 0;
393 }
394 else if(cistrcmp(cb->f[1], "on") == 0){
395 control = ctlr->gib->srcb.control;
396 control |= CoalUpdateOnly;
397 ctlr->gib->srcb.control = control;
398 ctlr->coalupdateonly = 1;
399 }
400 else
401 r = -1;
402 }
403 else if(cistrcmp(cb->f[0], "hardwarecksum") == 0){
404 if(cistrcmp(cb->f[1], "off") == 0){
405 control = ctlr->gib->srcb.control;
406 control &= ~(TcpUdpCksum|NoPseudoHdrCksum);
407 ctlr->gib->srcb.control = control;
408
409 control = ctlr->gib->rsrcb.control;
410 control &= ~(TcpUdpCksum|NoPseudoHdrCksum);
411 ctlr->gib->rsrcb.control = control;
412
413 ctlr->hardwarecksum = 0;
414 }
415 else if(cistrcmp(cb->f[1], "on") == 0){
416 control = ctlr->gib->srcb.control;
417 control |= (TcpUdpCksum|NoPseudoHdrCksum);
418 ctlr->gib->srcb.control = control;
419
420 control = ctlr->gib->rsrcb.control;
421 control |= (TcpUdpCksum|NoPseudoHdrCksum);
422 ctlr->gib->rsrcb.control = control;
423
424 ctlr->hardwarecksum = 1;
425 }
426 else
427 r = -1;
428 }
429 else if(cistrcmp(cb->f[0], "rct") == 0){
430 i = strtol(cb->f[1], &p, 0);
431 if(i < 0 || p == cb->f[1])
432 r = -1;
433 else{
434 ctlr->rct = i;
435 csr32w(ctlr, Rct, ctlr->rct);
436 }
437 }
438 else if(cistrcmp(cb->f[0], "sct") == 0){
439 i = strtol(cb->f[1], &p, 0);
440 if(i < 0 || p == cb->f[1])
441 r = -1;
442 else{
443 ctlr->sct = i;
444 csr32w(ctlr, Sct, ctlr->sct);
445 }
446 }
447 else if(cistrcmp(cb->f[0], "st") == 0){
448 i = strtol(cb->f[1], &p, 0);
449 if(i < 0 || p == cb->f[1])
450 r = -1;
451 else{
452 ctlr->st = i;
453 csr32w(ctlr, St, ctlr->st);
454 }
455 }
456 else if(cistrcmp(cb->f[0], "smcbd") == 0){
457 i = strtol(cb->f[1], &p, 0);
458 if(i < 0 || p == cb->f[1])
459 r = -1;
460 else{
461 ctlr->smcbd = i;
462 csr32w(ctlr, SmcBD, ctlr->smcbd);
463 }
464 }
465 else if(cistrcmp(cb->f[0], "rmcbd") == 0){
466 i = strtol(cb->f[1], &p, 0);
467 if(i < 0 || p == cb->f[1])
468 r = -1;
469 else{
470 ctlr->rmcbd = i;
471 csr32w(ctlr, RmcBD, ctlr->rmcbd);
472 }
473 }
474 else
475 r = -1;
476
477 free(cb);
478 if(r == 0)
479 return n;
480 return r;
481 }
482
483 static int
_ga620transmit(Ether * edev)484 _ga620transmit(Ether* edev)
485 {
486 Sbd *sbd;
487 Block *bp;
488 Ctlr *ctlr;
489 int sci, spi, work;
490
491 /*
492 * For now there are no smarts here, just empty the
493 * ring and try to fill it back up. Tuning comes later.
494 */
495 ctlr = edev->ctlr;
496 ilock(&ctlr->srlock);
497
498 /*
499 * Free any completed packets.
500 * Ctlr->sci[0] is where the NIC has got to consuming the ring.
501 * Ctlr->sci[2] is where the host has got to tidying up after the
502 * NIC has done with the packets.
503 */
504 work = 0;
505 for(sci = ctlr->sci[2]; sci != ctlr->sci[0]; sci = NEXT(sci, Nsr)){
506 if(ctlr->srb[sci] == nil)
507 continue;
508 freeb(ctlr->srb[sci]);
509 ctlr->srb[sci] = nil;
510 work++;
511 }
512 ctlr->sci[2] = sci;
513
514 sci = PREV(sci, Nsr);
515 for(spi = csr32r(ctlr, Spi); spi != sci; spi = NEXT(spi, Nsr)){
516 if((bp = qget(edev->oq)) == nil)
517 break;
518
519 sbd = &ctlr->sr[spi];
520 sethost64(&sbd->addr, bp->rp);
521 sbd->lenflags = BLEN(bp)<<16 | Fend;
522
523 ctlr->srb[spi] = bp;
524 work++;
525 }
526 csr32w(ctlr, Spi, spi);
527
528 iunlock(&ctlr->srlock);
529
530 return work;
531 }
532
533 static void
ga620transmit(Ether * edev)534 ga620transmit(Ether* edev)
535 {
536 _ga620transmit(edev);
537 }
538
539 static void
ga620replenish(Ctlr * ctlr)540 ga620replenish(Ctlr* ctlr)
541 {
542 Rbd *rbd;
543 int rspi;
544 Block *bp;
545
546 rspi = csr32r(ctlr, Rspi);
547 while(ctlr->nrsr < NrsrHI){
548 if((bp = iallocb(ETHERMAXTU+4)) == nil)
549 break;
550 rbd = &ctlr->rsr[rspi];
551 sethost64(&rbd->addr, bp->rp);
552 rbd->indexlen = rspi<<16 | (ETHERMAXTU+4);
553 rbd->flags = 0;
554 rbd->opaque = bp;
555
556 rspi = NEXT(rspi, Nrsr);
557 ctlr->nrsr++;
558 }
559 csr32w(ctlr, Rspi, rspi);
560 }
561
562 static void
ga620event(Ether * edev,int eci,int epi)563 ga620event(Ether *edev, int eci, int epi)
564 {
565 unsigned event, code;
566 Ctlr *ctlr;
567
568 ctlr = edev->ctlr;
569 while(eci != epi){
570 event = ctlr->er[eci].event;
571 code = (event >> 12) & ((1<<12)-1);
572 switch(event>>24){
573 case 0x01: /* firmware operational */
574 /* host stack (us) is up. 3rd arg of 2 means down. */
575 ga620command(ctlr, 0x01, 0x01, 0x00);
576 /*
577 * link negotiation: any speed is okay.
578 * 3rd arg of 1 selects gigabit only; 2 10/100 only.
579 */
580 ga620command(ctlr, 0x0B, 0x00, 0x00);
581 print("#l%d: ga620: port %8.8uX: firmware is up\n",
582 edev->ctlrno, ctlr->port);
583 break;
584 case 0x04: /* statistics updated */
585 break;
586 case 0x06: /* link state changed */
587 switch (code) {
588 case 1:
589 edev->mbps = 1000;
590 break;
591 case 2:
592 print("#l%d: link down\n", edev->ctlrno);
593 break;
594 case 3:
595 edev->mbps = 100; /* it's 10 or 100 */
596 break;
597 }
598 if (code != 2)
599 print("#l%d: %dMbps link up\n",
600 edev->ctlrno, edev->mbps);
601 break;
602 case 0x07: /* event error */
603 default:
604 print("#l%d: ga620: er[%d] = %8.8uX\n", edev->ctlrno,
605 eci, event);
606 break;
607 }
608 eci = NEXT(eci, Ner);
609 }
610 csr32w(ctlr, Eci, eci);
611 }
612
613 static void
ga620receive(Ether * edev)614 ga620receive(Ether* edev)
615 {
616 int len;
617 Rbd *rbd;
618 Block *bp;
619 Ctlr* ctlr;
620
621 ctlr = edev->ctlr;
622 while(ctlr->rrrci != ctlr->rrrpi[0]){
623 rbd = &ctlr->rrr[ctlr->rrrci];
624 /*
625 * Errors are collected in the statistics block so
626 * no need to tally them here, let ifstat do the work.
627 */
628 len = rbd->indexlen & 0xFFFF;
629 if(!(rbd->flags & Ferror) && len != 0){
630 bp = rbd->opaque;
631 bp->wp = bp->rp+len;
632 etheriq(edev, bp, 1);
633 }
634 else
635 freeb(rbd->opaque);
636 rbd->opaque = nil;
637
638 if(rbd->flags & Frjr)
639 ctlr->nrjr--;
640 else if(rbd->flags & Frmr)
641 ctlr->nrmr--;
642 else
643 ctlr->nrsr--;
644
645 ctlr->rrrci = NEXT(ctlr->rrrci, Nrrr);
646 }
647 }
648
649 static void
ga620interrupt(Ureg *,void * arg)650 ga620interrupt(Ureg*, void* arg)
651 {
652 int csr, ie, work;
653 Ctlr *ctlr;
654 Ether *edev;
655 uvlong tsc0, tsc1;
656
657 edev = arg;
658 ctlr = edev->ctlr;
659
660 if(!(csr32r(ctlr, Mhc) & Is))
661 return;
662 cycles(&tsc0);
663
664 ctlr->interrupts++;
665 csr32w(ctlr, Hi, 1);
666
667 ie = 0;
668 work = 0;
669 while(ie < 2){
670 if(ctlr->rrrci != ctlr->rrrpi[0]){
671 ga620receive(edev);
672 work = 1;
673 }
674
675 if(_ga620transmit(edev) != 0)
676 work = 1;
677
678 csr = csr32r(ctlr, Eci);
679 if(csr != ctlr->epi[0]){
680 ga620event(edev, csr, ctlr->epi[0]);
681 work = 1;
682 }
683
684 if(ctlr->nrsr <= NrsrLO)
685 ga620replenish(ctlr);
686 if(work == 0){
687 if(ie == 0)
688 csr32w(ctlr, Hi, 0);
689 ie++;
690 }
691 work = 0;
692 }
693
694 cycles(&tsc1);
695 ctlr->ticks += tsc1-tsc0;
696 }
697
698 static void
ga620lmw(Ctlr * ctlr,int addr,int * data,int len)699 ga620lmw(Ctlr* ctlr, int addr, int* data, int len)
700 {
701 int i, l, lmw, v;
702
703 /*
704 * Write to or clear ('data' == nil) 'len' bytes of the NIC
705 * local memory at address 'addr'.
706 * The destination address and count should be 32-bit aligned.
707 */
708 v = 0;
709 while(len > 0){
710 /*
711 * 1) Set the window. The (Lmwsz-1) bits are ignored
712 * in Wba when accessing through the local memory window;
713 * 2) Find the minimum of how many bytes still to
714 * transfer and how many left in this window;
715 * 3) Create the offset into the local memory window in the
716 * shared memory space then copy (or zero) the data;
717 * 4) Bump the counts.
718 */
719 csr32w(ctlr, Wba, addr);
720
721 l = ROUNDUP(addr+1, Lmwsz) - addr;
722 if(l > len)
723 l = len;
724
725 lmw = Lmw + (addr & (Lmwsz-1));
726 for(i = 0; i < l; i += 4){
727 if(data != nil)
728 v = *data++;
729 csr32w(ctlr, lmw+i, v);
730 }
731
732 len -= l;
733 addr += l;
734 }
735 }
736
737 static int
ga620init(Ether * edev)738 ga620init(Ether* edev)
739 {
740 Ctlr *ctlr;
741 Host64 host64;
742 int csr, ea, i, flags;
743
744 ctlr = edev->ctlr;
745
746 /*
747 * Load the MAC address.
748 */
749 ea = edev->ea[0]<<8 | edev->ea[1];
750 csr32w(ctlr, Mac, ea);
751 ea = edev->ea[2]<<24 | edev->ea[3]<<16 | edev->ea[4]<<8 | edev->ea[5];
752 csr32w(ctlr, Mac+4, ea);
753
754 ctlr->gib = nil;
755 ctlr->er = nil;
756 ctlr->srb = nil;
757 ctlr->sr = nil;
758 ctlr->rsr = nil;
759 if(waserror()) {
760 free(ctlr->gib);
761 free(ctlr->er);
762 free(ctlr->srb);
763 free(ctlr->sr);
764 free(ctlr->rsr);
765 ctlr->gib = nil;
766 ctlr->er = nil;
767 ctlr->srb = nil;
768 ctlr->sr = nil;
769 ctlr->rsr = nil;
770 nexterror();
771 }
772 /*
773 * General Information Block.
774 */
775 ctlr->gib = malloc(sizeof(Gib));
776 if(ctlr->gib == nil)
777 error(Enomem);
778 sethost64(&host64, ctlr->gib);
779 csr32w(ctlr, Gip, host64.hi);
780 csr32w(ctlr, Gip+4, host64.lo);
781
782 /*
783 * Event Ring.
784 * This is located in host memory. Allocate the ring,
785 * tell the NIC where it is and initialise the indices.
786 */
787 ctlr->er = malign(sizeof(Ere)*Ner);
788 if(ctlr->er == nil)
789 error(Enomem);
790 sethost64(&ctlr->gib->ercb.addr, ctlr->er);
791 sethost64(&ctlr->gib->epp, ctlr->epi);
792 csr32w(ctlr, Eci, 0);
793
794 /*
795 * Command Ring.
796 * This is located in the General Communications Region
797 * and so the value placed in the Rcb is unused, the NIC
798 * knows where it is. Stick in the value according to
799 * the datasheet anyway.
800 * Initialise the ring and indices.
801 */
802 ctlr->gib->crcb.addr.lo = Cr-0x400;
803 for(i = 0; i < Ncr*4; i += 4)
804 csr32w(ctlr, Cr+i, 0);
805 csr32w(ctlr, Cpi, 0);
806 csr32w(ctlr, Cci, 0);
807
808 /*
809 * Send Ring.
810 * This ring is either in NIC memory at a fixed location depending
811 * on how big the ring is or it is in host memory. If in NIC
812 * memory it is accessed via the Local Memory Window; with a send
813 * ring size of 128 the window covers the whole ring and then need
814 * only be set once:
815 * ctlr->sr = (uchar*)ctlr->nic+Lmw;
816 * ga620lmw(ctlr, Sr, nil, sizeof(Sbd)*Nsr);
817 * ctlr->gib->srcb.addr.lo = Sr;
818 * There is nowhere in the Sbd to hold the Block* associated
819 * with this entry so an external array must be kept.
820 */
821 ctlr->sr = malign(sizeof(Sbd)*Nsr);
822 if(ctlr->sr == nil)
823 error(Enomem);
824 sethost64(&ctlr->gib->srcb.addr, ctlr->sr);
825 if(ctlr->hardwarecksum)
826 flags = TcpUdpCksum|NoPseudoHdrCksum|HostRing;
827 else
828 flags = HostRing;
829 if(ctlr->coalupdateonly)
830 flags |= CoalUpdateOnly;
831 ctlr->gib->srcb.control = Nsr<<16 | flags;
832 sethost64(&ctlr->gib->scp, ctlr->sci);
833 csr32w(ctlr, Spi, 0);
834 ctlr->srb = malloc(sizeof(Block*)*Nsr);
835 if(ctlr->srb == nil)
836 error(Enomem);
837
838 /*
839 * Receive Standard Ring.
840 */
841 ctlr->rsr = malign(sizeof(Rbd)*Nrsr);
842 if(ctlr->rsr == nil)
843 error(Enomem);
844 sethost64(&ctlr->gib->rsrcb.addr, ctlr->rsr);
845 if(ctlr->hardwarecksum)
846 flags = TcpUdpCksum|NoPseudoHdrCksum;
847 else
848 flags = 0;
849 ctlr->gib->rsrcb.control = (ETHERMAXTU+4)<<16 | flags;
850 csr32w(ctlr, Rspi, 0);
851
852 /*
853 * Jumbo and Mini Rings. Unused for now.
854 */
855 ctlr->gib->rjrcb.control = RingDisabled;
856 ctlr->gib->rmrcb.control = RingDisabled;
857
858 /*
859 * Receive Return Ring.
860 * This is located in host memory. Allocate the ring,
861 * tell the NIC where it is and initialise the indices.
862 */
863 ctlr->rrr = malign(sizeof(Rbd)*Nrrr);
864 if(ctlr->rrr == nil)
865 error(Enomem);
866 poperror();
867 sethost64(&ctlr->gib->rrrcb.addr, ctlr->rrr);
868 ctlr->gib->rrrcb.control = Nrrr<<16 | 0;
869 sethost64(&ctlr->gib->rrrpp, ctlr->rrrpi);
870 ctlr->rrrci = 0;
871
872 /*
873 * Refresh Stats Pointer.
874 * For now just point it at the existing statistics block.
875 */
876 sethost64(&ctlr->gib->rsp, ctlr->gib->statistics);
877
878 /*
879 * DMA configuration.
880 * Use the recommended values.
881 */
882 csr32w(ctlr, DMArc, 0x80);
883 csr32w(ctlr, DMAwc, 0x80);
884
885 /*
886 * Transmit Buffer Ratio.
887 * Set to 1/3 of available buffer space (units are 1/64ths)
888 * if using Jumbo packets, ~64KB otherwise (assume 1MB on NIC).
889 */
890 if(NrjrHI > 0 || Nsr > 128)
891 csr32w(ctlr, Tbr, 64/3);
892 else
893 csr32w(ctlr, Tbr, 4);
894
895 /*
896 * Tuneable parameters.
897 * These defaults are based on the tuning hints in the Alteon
898 * Host/NIC Software Interface Definition and example software.
899 */
900 ctlr->rct = 1/*100*/;
901 csr32w(ctlr, Rct, ctlr->rct);
902 ctlr->sct = 0;
903 csr32w(ctlr, Sct, ctlr->sct);
904 ctlr->st = 1000000;
905 csr32w(ctlr, St, ctlr->st);
906 ctlr->smcbd = Nsr/4;
907 csr32w(ctlr, SmcBD, ctlr->smcbd);
908 ctlr->rmcbd = 4/*6*/;
909 csr32w(ctlr, RmcBD, ctlr->rmcbd);
910
911 /*
912 * Enable DMA Assist Logic.
913 */
914 csr = csr32r(ctlr, DMAas) & ~0x03;
915 csr32w(ctlr, DMAas, csr|0x01);
916
917 /*
918 * Link negotiation.
919 * The bits are set here but the NIC must be given a command
920 * once it is running to set negotiation in motion.
921 */
922 csr32w(ctlr, Gln, Le|Lean|Lofc|Lfd|L1000MB|Lpref);
923 csr32w(ctlr, Fln, Le|Lean|Lhd|Lfd|L100MB|L10MB);
924
925 /*
926 * A unique index for this controller and the maximum packet
927 * length expected.
928 * For now only standard packets are expected.
929 */
930 csr32w(ctlr, Ifx, 1);
931 csr32w(ctlr, IfMTU, ETHERMAXTU+4);
932
933 /*
934 * Enable Interrupts.
935 * There are 3 ways to mask interrupts - a bit in the Mhc (which
936 * is already cleared), the Mi register and the Hi mailbox.
937 * Writing to the Hi mailbox has the side-effect of clearing the
938 * PCI interrupt.
939 */
940 csr32w(ctlr, Mi, 0);
941 csr32w(ctlr, Hi, 0);
942
943 /*
944 * Start the firmware.
945 */
946 csr32w(ctlr, CPUApc, tigon2FwStartAddr);
947 csr = csr32r(ctlr, CPUAstate) & ~CPUhalt;
948 csr32w(ctlr, CPUAstate, csr);
949
950 return 0;
951 }
952
953 static int
at24c32io(Ctlr * ctlr,char * op,int data)954 at24c32io(Ctlr* ctlr, char* op, int data)
955 {
956 char *lp, *p;
957 int i, loop, mlc, r;
958
959 mlc = csr32r(ctlr, Mlc);
960
961 r = 0;
962 loop = -1;
963 lp = nil;
964 for(p = op; *p != '\0'; p++){
965 switch(*p){
966 default:
967 return -1;
968 case ' ':
969 continue;
970 case ':': /* start of 8-bit loop */
971 if(lp != nil)
972 return -1;
973 lp = p;
974 loop = 7;
975 continue;
976 case ';': /* end of 8-bit loop */
977 if(lp == nil)
978 return -1;
979 loop--;
980 if(loop >= 0)
981 p = lp;
982 else
983 lp = nil;
984 continue;
985 case 'C': /* assert clock */
986 mlc |= EEclk;
987 break;
988 case 'c': /* deassert clock */
989 mlc &= ~EEclk;
990 break;
991 case 'D': /* next bit in 'data' byte */
992 if(loop < 0)
993 return -1;
994 if(data & (1<<loop))
995 mlc |= EEdo;
996 else
997 mlc &= ~EEdo;
998 break;
999 case 'E': /* enable data output */
1000 mlc |= EEdoe;
1001 break;
1002 case 'e': /* disable data output */
1003 mlc &= ~EEdoe;
1004 break;
1005 case 'I': /* input bit */
1006 i = (csr32r(ctlr, Mlc) & EEdi) != 0;
1007 if(loop >= 0)
1008 r |= (i<<loop);
1009 else
1010 r = i;
1011 continue;
1012 case 'O': /* assert data output */
1013 mlc |= EEdo;
1014 break;
1015 case 'o': /* deassert data output */
1016 mlc &= ~EEdo;
1017 break;
1018 }
1019 csr32w(ctlr, Mlc, mlc);
1020 microdelay(1);
1021 }
1022 if(loop >= 0)
1023 return -1;
1024 return r;
1025 }
1026
1027 static int
at24c32r(Ctlr * ctlr,int addr)1028 at24c32r(Ctlr* ctlr, int addr)
1029 {
1030 int data;
1031
1032 /*
1033 * Read a byte at address 'addr' from the Atmel AT24C32
1034 * Serial EEPROM. The 2-wire EEPROM access is controlled
1035 * by 4 bits in Mlc. See the AT24C32 datasheet for
1036 * protocol details.
1037 */
1038 /*
1039 * Start condition - a high to low transition of data
1040 * with the clock high must precede any other command.
1041 */
1042 at24c32io(ctlr, "OECoc", 0);
1043
1044 /*
1045 * Perform a random read at 'addr'. A dummy byte
1046 * write sequence is performed to clock in the device
1047 * and data word addresses (0 and 'addr' respectively).
1048 */
1049 data = -1;
1050 if(at24c32io(ctlr, "oE :DCc; oeCIc", 0xA0) != 0)
1051 goto stop;
1052 if(at24c32io(ctlr, "oE :DCc; oeCIc", addr>>8) != 0)
1053 goto stop;
1054 if(at24c32io(ctlr, "oE :DCc; oeCIc", addr) != 0)
1055 goto stop;
1056
1057 /*
1058 * Now send another start condition followed by a
1059 * request to read the device. The EEPROM responds
1060 * by clocking out the data.
1061 */
1062 at24c32io(ctlr, "OECoc", 0);
1063 if(at24c32io(ctlr, "oE :DCc; oeCIc", 0xA1) != 0)
1064 goto stop;
1065 data = at24c32io(ctlr, ":CIc;", 0xA1);
1066
1067 stop:
1068 /*
1069 * Stop condition - a low to high transition of data
1070 * with the clock high is a stop condition. After a read
1071 * sequence, the stop command will place the EEPROM in
1072 * a standby power mode.
1073 */
1074 at24c32io(ctlr, "oECOc", 0);
1075
1076 return data;
1077 }
1078
1079 static int
ga620detach(Ctlr * ctlr)1080 ga620detach(Ctlr* ctlr)
1081 {
1082 int timeo;
1083
1084 /*
1085 * Hard reset (don't know which endian so catch both);
1086 * enable for little-endian mode;
1087 * wait for code to be loaded from serial EEPROM or flash;
1088 * make sure CPU A is halted.
1089 */
1090 csr32w(ctlr, Mhc, Hr<<24 | Hr);
1091 csr32w(ctlr, Mhc, (Eews|Ci)<<24 | Eews|Ci);
1092
1093 microdelay(1);
1094 for(timeo = 0; timeo < 500000; timeo++){
1095 if((csr32r(ctlr, CPUAstate) & (CPUhie|CPUrf)) == CPUhie)
1096 break;
1097 microdelay(1);
1098 }
1099 if((csr32r(ctlr, CPUAstate) & (CPUhie|CPUrf)) != CPUhie)
1100 return -1;
1101 csr32w(ctlr, CPUAstate, CPUhalt);
1102
1103 /*
1104 * After reset, CPU B seems to be stuck in 'CPUrf'.
1105 * Worry about it later.
1106 */
1107 csr32w(ctlr, CPUBstate, CPUhalt);
1108
1109 return 0;
1110 }
1111
1112 static void
ga620shutdown(Ether * ether)1113 ga620shutdown(Ether* ether)
1114 {
1115 print("ga620shutdown\n");
1116 ga620detach(ether->ctlr);
1117 }
1118
1119 static int
ga620reset(Ctlr * ctlr)1120 ga620reset(Ctlr* ctlr)
1121 {
1122 int cls, csr, i, r;
1123
1124 if(ga620detach(ctlr) < 0)
1125 return -1;
1126
1127 /*
1128 * Tigon 2 PCI NICs have 512KB SRAM per bank.
1129 * Clear out any lingering serial EEPROM state
1130 * bits.
1131 */
1132 csr = csr32r(ctlr, Mlc) & ~(EEdi|EEdo|EEdoe|EEclk|SRAMmask);
1133 csr32w(ctlr, Mlc, SRAM512|csr);
1134 csr = csr32r(ctlr, Mc);
1135 csr32w(ctlr, Mc, SyncSRAM|csr);
1136
1137 /*
1138 * Initialise PCI State register.
1139 * If PCI Write-and-Invalidate is enabled set the max write DMA
1140 * value to the host cache-line size (32 on Pentium or later).
1141 */
1142 csr = csr32r(ctlr, Ps) & (PCI32|PCI66);
1143 csr |= PCIwcmd|PCIrcmd|PCImrm;
1144 if(ctlr->pcidev->pcr & 0x0010){
1145 cls = pcicfgr8(ctlr->pcidev, PciCLS) * 4;
1146 if(cls != 32)
1147 pcicfgw8(ctlr->pcidev, PciCLS, 32/4);
1148 csr |= PCIwm32;
1149 }
1150 csr32w(ctlr, Ps, csr);
1151
1152 /*
1153 * Operating Mode.
1154 */
1155 csr32w(ctlr, Om, Fatal|NoJFrag|BswapDMA|WswapBD);
1156
1157 /*
1158 * Snarf the MAC address from the serial EEPROM.
1159 */
1160 for(i = 0; i < Eaddrlen; i++){
1161 if((r = at24c32r(ctlr, 0x8E+i)) == -1)
1162 return -1;
1163 ctlr->ea[i] = r;
1164 }
1165
1166 /*
1167 * Load the firmware.
1168 */
1169 ga620lmw(ctlr, tigon2FwTextAddr, tigon2FwText, tigon2FwTextLen);
1170 ga620lmw(ctlr, tigon2FwRodataAddr, tigon2FwRodata, tigon2FwRodataLen);
1171 ga620lmw(ctlr, tigon2FwDataAddr, tigon2FwData, tigon2FwDataLen);
1172 ga620lmw(ctlr, tigon2FwSbssAddr, nil, tigon2FwSbssLen);
1173 ga620lmw(ctlr, tigon2FwBssAddr, nil, tigon2FwBssLen);
1174
1175 return 0;
1176 }
1177
1178 static void
ga620pci(void)1179 ga620pci(void)
1180 {
1181 void *mem;
1182 Pcidev *p;
1183 Ctlr *ctlr;
1184
1185 p = nil;
1186 while(p = pcimatch(p, 0, 0)){
1187 if(p->ccrb != 0x02 || p->ccru != 0)
1188 continue;
1189
1190 switch(p->did<<16 | p->vid){
1191 default:
1192 continue;
1193 case 0x620A<<16 | 0x1385: /* Netgear GA620 fiber */
1194 case 0x630A<<16 | 0x1385: /* Netgear GA620T copper */
1195 case 0x0001<<16 | 0x12AE: /* Alteon Acenic fiber
1196 * and DEC DEGPA-SA */
1197 case 0x0002<<16 | 0x12AE: /* Alteon Acenic copper */
1198 case 0x0009<<16 | 0x10A9: /* SGI Acenic */
1199 break;
1200 }
1201
1202 mem = vmap(p->mem[0].bar & ~0x0F, p->mem[0].size);
1203 if(mem == 0){
1204 print("ga620: can't map %8.8luX\n", p->mem[0].bar);
1205 continue;
1206 }
1207
1208 ctlr = malloc(sizeof(Ctlr));
1209 if(ctlr == nil) {
1210 vunmap(mem, p->mem[0].size);
1211 error(Enomem);
1212 }
1213 ctlr->port = p->mem[0].bar & ~0x0F;
1214 ctlr->pcidev = p;
1215 ctlr->id = p->did<<16 | p->vid;
1216
1217 ctlr->nic = mem;
1218 if(ga620reset(ctlr)){
1219 free(ctlr);
1220 continue;
1221 }
1222
1223 if(ctlrhead != nil)
1224 ctlrtail->next = ctlr;
1225 else
1226 ctlrhead = ctlr;
1227 ctlrtail = ctlr;
1228 }
1229 }
1230
1231 static void
ga620promiscuous(void * arg,int on)1232 ga620promiscuous(void *arg, int on)
1233 {
1234 Ether *ether = arg;
1235
1236 /* 3rd arg: 1 enables, 2 disables */
1237 ga620command(ether->ctlr, 0xa, (on? 1: 2), 0);
1238 }
1239
1240 static void
ga620multicast(void * arg,uchar * addr,int add)1241 ga620multicast(void *arg, uchar *addr, int add)
1242 {
1243 Ether *ether = arg;
1244
1245 USED(addr);
1246 if (add)
1247 ga620command(ether->ctlr, 0xe, 1, 0); /* 1 == enable */
1248 }
1249
1250 static int
ga620pnp(Ether * edev)1251 ga620pnp(Ether* edev)
1252 {
1253 Ctlr *ctlr;
1254 uchar ea[Eaddrlen];
1255
1256 if(ctlrhead == nil)
1257 ga620pci();
1258
1259 /*
1260 * Any adapter matches if no edev->port is supplied,
1261 * otherwise the ports must match.
1262 */
1263 for(ctlr = ctlrhead; ctlr != nil; ctlr = ctlr->next){
1264 if(ctlr->active)
1265 continue;
1266 if(edev->port == 0 || edev->port == ctlr->port){
1267 ctlr->active = 1;
1268 break;
1269 }
1270 }
1271 if(ctlr == nil)
1272 return -1;
1273
1274 edev->ctlr = ctlr;
1275 edev->port = ctlr->port;
1276 edev->irq = ctlr->pcidev->intl;
1277 edev->tbdf = ctlr->pcidev->tbdf;
1278 edev->mbps = 1000; /* placeholder */
1279
1280 /*
1281 * Check if the adapter's station address is to be overridden.
1282 * If not, read it from the EEPROM and set in ether->ea prior to
1283 * loading the station address in the hardware.
1284 */
1285 memset(ea, 0, Eaddrlen);
1286 if(memcmp(ea, edev->ea, Eaddrlen) == 0)
1287 memmove(edev->ea, ctlr->ea, Eaddrlen);
1288
1289 ga620init(edev);
1290
1291 /*
1292 * Linkage to the generic ethernet driver.
1293 */
1294 edev->attach = ga620attach;
1295 edev->transmit = ga620transmit;
1296 edev->interrupt = ga620interrupt;
1297 edev->ifstat = ga620ifstat;
1298 edev->ctl = ga620ctl;
1299
1300 edev->arg = edev;
1301 edev->promiscuous = ga620promiscuous;
1302 edev->multicast = ga620multicast;
1303 edev->shutdown = ga620shutdown;
1304
1305 return 0;
1306 }
1307
1308 void
etherga620link(void)1309 etherga620link(void)
1310 {
1311 addethercard("GA620", ga620pnp);
1312 }
1313