1 /*
2 * Intel 82557 Fast Ethernet PCI Bus LAN Controller
3 * as found on the Intel EtherExpress PRO/100B. This chip is full
4 * of smarts, unfortunately they're not all in the right place.
5 * To do:
6 * the PCI scanning code could be made common to other adapters;
7 * auto-negotiation, full-duplex;
8 * optionally use memory-mapped registers;
9 * detach for PCI reset problems (also towards loadable drivers).
10 */
11 #include "u.h"
12 #include "../port/lib.h"
13 #include "mem.h"
14 #include "dat.h"
15 #include "fns.h"
16 #include "io.h"
17 #include "../port/error.h"
18 #include "../port/netif.h"
19
20 #include "etherif.h"
21
22 enum {
23 /*
24 * these were both 64. increased them to try to improve lookout's
25 * reliability as a pxe booter.
26 */
27 Nrfd = 128, /* receive frame area */
28 Ncb = 128, /* maximum control blocks queued */
29
30 NullPointer = 0xFFFFFFFF, /* 82557 NULL pointer */
31 };
32
33 enum { /* CSR */
34 Status = 0x00, /* byte or word (word includes Ack) */
35 Ack = 0x01, /* byte */
36 CommandR = 0x02, /* byte or word (word includes Interrupt) */
37 Interrupt = 0x03, /* byte */
38 General = 0x04, /* dword */
39 Port = 0x08, /* dword */
40 Fcr = 0x0C, /* Flash control register */
41 Ecr = 0x0E, /* EEPROM control register */
42 Mcr = 0x10, /* MDI control register */
43 Gstatus = 0x1D, /* General status register */
44 };
45
46 enum { /* Status */
47 RUidle = 0x0000,
48 RUsuspended = 0x0004,
49 RUnoresources = 0x0008,
50 RUready = 0x0010,
51 RUrbd = 0x0020, /* bit */
52 RUstatus = 0x003F, /* mask */
53
54 CUidle = 0x0000,
55 CUsuspended = 0x0040,
56 CUactive = 0x0080,
57 CUstatus = 0x00C0, /* mask */
58
59 StatSWI = 0x0400, /* SoftWare generated Interrupt */
60 StatMDI = 0x0800, /* MDI r/w done */
61 StatRNR = 0x1000, /* Receive unit Not Ready */
62 StatCNA = 0x2000, /* Command unit Not Active (Active->Idle) */
63 StatFR = 0x4000, /* Finished Receiving */
64 StatCX = 0x8000, /* Command eXecuted */
65 StatTNO = 0x8000, /* Transmit NOT OK */
66 };
67
68 enum { /* Command (byte) */
69 CUnop = 0x00,
70 CUstart = 0x10,
71 CUresume = 0x20,
72 LoadDCA = 0x40, /* Load Dump Counters Address */
73 DumpSC = 0x50, /* Dump Statistical Counters */
74 LoadCUB = 0x60, /* Load CU Base */
75 ResetSA = 0x70, /* Dump and Reset Statistical Counters */
76
77 RUstart = 0x01,
78 RUresume = 0x02,
79 RUabort = 0x04,
80 LoadHDS = 0x05, /* Load Header Data Size */
81 LoadRUB = 0x06, /* Load RU Base */
82 RBDresume = 0x07, /* Resume frame reception */
83 };
84
85 enum { /* Interrupt (byte) */
86 InterruptM = 0x01, /* interrupt Mask */
87 InterruptSI = 0x02, /* Software generated Interrupt */
88 };
89
90 enum { /* Ecr */
91 EEsk = 0x01, /* serial clock */
92 EEcs = 0x02, /* chip select */
93 EEdi = 0x04, /* serial data in */
94 EEdo = 0x08, /* serial data out */
95
96 EEstart = 0x04, /* start bit */
97 EEread = 0x02, /* read opcode */
98 };
99
100 enum { /* Mcr */
101 MDIread = 0x08000000, /* read opcode */
102 MDIwrite = 0x04000000, /* write opcode */
103 MDIready = 0x10000000, /* ready bit */
104 MDIie = 0x20000000, /* interrupt enable */
105 };
106
107 typedef struct Rfd {
108 int field;
109 ulong link;
110 ulong rbd;
111 ushort count;
112 ushort size;
113
114 uchar data[1700];
115 } Rfd;
116
117 enum { /* field */
118 RfdCollision = 0x00000001,
119 RfdIA = 0x00000002, /* IA match */
120 RfdRxerr = 0x00000010, /* PHY character error */
121 RfdType = 0x00000020, /* Type frame */
122 RfdRunt = 0x00000080,
123 RfdOverrun = 0x00000100,
124 RfdBuffer = 0x00000200,
125 RfdAlignment = 0x00000400,
126 RfdCRC = 0x00000800,
127
128 RfdOK = 0x00002000, /* frame received OK */
129 RfdC = 0x00008000, /* reception Complete */
130 RfdSF = 0x00080000, /* Simplified or Flexible (1) Rfd */
131 RfdH = 0x00100000, /* Header RFD */
132
133 RfdI = 0x20000000, /* Interrupt after completion */
134 RfdS = 0x40000000, /* Suspend after completion */
135 RfdEL = 0x80000000, /* End of List */
136 };
137
138 enum { /* count */
139 RfdF = 0x4000,
140 RfdEOF = 0x8000,
141 };
142
143 typedef struct Cb Cb;
144 typedef struct Cb {
145 ushort status;
146 ushort command;
147 ulong link;
148 union {
149 uchar data[24]; /* CbIAS + CbConfigure */
150 struct {
151 ulong tbd;
152 ushort count;
153 uchar threshold;
154 uchar number;
155
156 ulong tba;
157 ushort tbasz;
158 ushort pad;
159 };
160 };
161
162 Block* bp;
163 Cb* next;
164 } Cb;
165
166 enum { /* action command */
167 CbU = 0x1000, /* transmit underrun */
168 CbOK = 0x2000, /* DMA completed OK */
169 CbC = 0x8000, /* execution Complete */
170
171 CbNOP = 0x0000,
172 CbIAS = 0x0001, /* Individual Address Setup */
173 CbConfigure = 0x0002,
174 CbMAS = 0x0003, /* Multicast Address Setup */
175 CbTransmit = 0x0004,
176 CbDump = 0x0006,
177 CbDiagnose = 0x0007,
178 CbCommand = 0x0007, /* mask */
179
180 CbSF = 0x0008, /* Flexible-mode CbTransmit */
181
182 CbI = 0x2000, /* Interrupt after completion */
183 CbS = 0x4000, /* Suspend after completion */
184 CbEL = 0x8000, /* End of List */
185 };
186
187 enum { /* CbTransmit count */
188 CbEOF = 0x8000,
189 };
190
191 typedef struct Ctlr Ctlr;
192 typedef struct Ctlr {
193 Lock slock; /* attach */
194 int state;
195
196 int port;
197 Pcidev* pcidev;
198 Ctlr* next;
199 int active;
200
201 int eepromsz; /* address size in bits */
202 ushort* eeprom;
203
204 Lock miilock;
205
206 int tick;
207
208 Lock rlock; /* registers */
209 int command; /* last command issued */
210
211 Block* rfdhead; /* receive side */
212 Block* rfdtail;
213 int nrfd;
214
215 Lock cblock; /* transmit side */
216 int action;
217 int nop;
218 uchar configdata[24];
219 int threshold;
220 int ncb;
221 Cb* cbr;
222 Cb* cbhead;
223 Cb* cbtail;
224 int cbq;
225 int cbqmax;
226 int cbqmaxhw;
227
228 Lock dlock; /* dump statistical counters */
229 ulong dump[17];
230 } Ctlr;
231
232 static Ctlr* ctlrhead;
233 static Ctlr* ctlrtail;
234
235 static uchar configdata[24] = {
236 0x16, /* byte count */
237 0x08, /* Rx/Tx FIFO limit */
238 0x00, /* adaptive IFS */
239 0x00,
240 0x00, /* Rx DMA maximum byte count */
241 // 0x80, /* Tx DMA maximum byte count */
242 0x00, /* Tx DMA maximum byte count */
243 0x32, /* !late SCB, CNA interrupts */
244 0x03, /* discard short Rx frames */
245 0x00, /* 503/MII */
246
247 0x00,
248 0x2E, /* normal operation, NSAI */
249 0x00, /* linear priority */
250 0x60, /* inter-frame spacing */
251 0x00,
252 0xF2,
253 0xC8, /* 503, promiscuous mode off */
254 0x00,
255 0x40,
256 0xF3, /* transmit padding enable */
257 0x80, /* full duplex pin enable */
258 0x3F, /* no Multi IA */
259 0x05, /* no Multi Cast ALL */
260 };
261
262 #define csr8r(c, r) (inb((c)->port+(r)))
263 #define csr16r(c, r) (ins((c)->port+(r)))
264 #define csr32r(c, r) (inl((c)->port+(r)))
265 #define csr8w(c, r, b) (outb((c)->port+(r), (int)(b)))
266 #define csr16w(c, r, w) (outs((c)->port+(r), (ushort)(w)))
267 #define csr32w(c, r, l) (outl((c)->port+(r), (ulong)(l)))
268
269 static void
command(Ctlr * ctlr,int c,int v)270 command(Ctlr* ctlr, int c, int v)
271 {
272 int timeo;
273
274 ilock(&ctlr->rlock);
275
276 /*
277 * Only back-to-back CUresume can be done
278 * without waiting for any previous command to complete.
279 * This should be the common case.
280 * Unfortunately there's a chip errata where back-to-back
281 * CUresumes can be lost, the fix is to always wait.
282 if(c == CUresume && ctlr->command == CUresume){
283 csr8w(ctlr, CommandR, c);
284 iunlock(&ctlr->rlock);
285 return;
286 }
287 */
288
289 for(timeo = 0; timeo < 100; timeo++){
290 if(!csr8r(ctlr, CommandR))
291 break;
292 microdelay(1);
293 }
294 if(timeo >= 100){
295 ctlr->command = -1;
296 iunlock(&ctlr->rlock);
297 iprint("i82557: command %#ux %#ux timeout\n", c, v);
298 return;
299 }
300
301 switch(c){
302
303 case CUstart:
304 case LoadDCA:
305 case LoadCUB:
306 case RUstart:
307 case LoadHDS:
308 case LoadRUB:
309 csr32w(ctlr, General, v);
310 break;
311
312 /*
313 case CUnop:
314 case CUresume:
315 case DumpSC:
316 case ResetSA:
317 case RUresume:
318 case RUabort:
319 */
320 default:
321 break;
322 }
323 csr8w(ctlr, CommandR, c);
324 ctlr->command = c;
325
326 iunlock(&ctlr->rlock);
327 }
328
329 static Block*
rfdalloc(ulong link)330 rfdalloc(ulong link)
331 {
332 Block *bp;
333 Rfd *rfd;
334
335 if(bp = iallocb(sizeof(Rfd))){
336 rfd = (Rfd*)bp->rp;
337 rfd->field = 0;
338 rfd->link = link;
339 rfd->rbd = NullPointer;
340 rfd->count = 0;
341 rfd->size = sizeof(Etherpkt);
342 }
343
344 return bp;
345 }
346
347 static void
ethwatchdog(void * arg)348 ethwatchdog(void* arg)
349 {
350 Ether *ether;
351 Ctlr *ctlr;
352 static void txstart(Ether*);
353
354 ether = arg;
355 for(;;){
356 tsleep(&up->sleep, return0, 0, 4000);
357
358 /*
359 * Hmmm. This doesn't seem right. Currently
360 * the device can't be disabled but it may be in
361 * the future.
362 */
363 ctlr = ether->ctlr;
364 if(ctlr == nil || ctlr->state == 0){
365 print("%s: exiting\n", up->text);
366 pexit("disabled", 0);
367 }
368
369 ilock(&ctlr->cblock);
370 if(ctlr->tick++){
371 ctlr->action = CbMAS;
372 txstart(ether);
373 }
374 iunlock(&ctlr->cblock);
375 }
376 }
377
378 static void
attach(Ether * ether)379 attach(Ether* ether)
380 {
381 Ctlr *ctlr;
382 char name[KNAMELEN];
383
384 ctlr = ether->ctlr;
385 lock(&ctlr->slock);
386 if(ctlr->state == 0){
387 ilock(&ctlr->rlock);
388 csr8w(ctlr, Interrupt, 0);
389 iunlock(&ctlr->rlock);
390 command(ctlr, RUstart, PADDR(ctlr->rfdhead->rp));
391 ctlr->state = 1;
392
393 /*
394 * Start the watchdog timer for the receive lockup errata
395 * unless the EEPROM compatibility word indicates it may be
396 * omitted.
397 */
398 if((ctlr->eeprom[0x03] & 0x0003) != 0x0003){
399 snprint(name, KNAMELEN, "#l%dwatchdog", ether->ctlrno);
400 kproc(name, ethwatchdog, ether);
401 }
402 }
403 unlock(&ctlr->slock);
404 }
405
406 static long
ifstat(Ether * ether,void * a,long n,ulong offset)407 ifstat(Ether* ether, void* a, long n, ulong offset)
408 {
409 char *p;
410 int i, len, phyaddr;
411 Ctlr *ctlr;
412 ulong dump[17];
413
414 ctlr = ether->ctlr;
415 lock(&ctlr->dlock);
416
417 /*
418 * Start the command then
419 * wait for completion status,
420 * should be 0xA005.
421 */
422 ctlr->dump[16] = 0;
423 command(ctlr, DumpSC, 0);
424 while(ctlr->dump[16] == 0)
425 ;
426
427 ether->oerrs = ctlr->dump[1]+ctlr->dump[2]+ctlr->dump[3];
428 ether->crcs = ctlr->dump[10];
429 ether->frames = ctlr->dump[11];
430 ether->buffs = ctlr->dump[12]+ctlr->dump[15];
431 ether->overflows = ctlr->dump[13];
432
433 if(n == 0){
434 unlock(&ctlr->dlock);
435 return 0;
436 }
437
438 memmove(dump, ctlr->dump, sizeof(dump));
439 unlock(&ctlr->dlock);
440
441 p = malloc(READSTR);
442 if(p == nil)
443 error(Enomem);
444 len = snprint(p, READSTR, "transmit good frames: %lud\n", dump[0]);
445 len += snprint(p+len, READSTR-len, "transmit maximum collisions errors: %lud\n", dump[1]);
446 len += snprint(p+len, READSTR-len, "transmit late collisions errors: %lud\n", dump[2]);
447 len += snprint(p+len, READSTR-len, "transmit underrun errors: %lud\n", dump[3]);
448 len += snprint(p+len, READSTR-len, "transmit lost carrier sense: %lud\n", dump[4]);
449 len += snprint(p+len, READSTR-len, "transmit deferred: %lud\n", dump[5]);
450 len += snprint(p+len, READSTR-len, "transmit single collisions: %lud\n", dump[6]);
451 len += snprint(p+len, READSTR-len, "transmit multiple collisions: %lud\n", dump[7]);
452 len += snprint(p+len, READSTR-len, "transmit total collisions: %lud\n", dump[8]);
453 len += snprint(p+len, READSTR-len, "receive good frames: %lud\n", dump[9]);
454 len += snprint(p+len, READSTR-len, "receive CRC errors: %lud\n", dump[10]);
455 len += snprint(p+len, READSTR-len, "receive alignment errors: %lud\n", dump[11]);
456 len += snprint(p+len, READSTR-len, "receive resource errors: %lud\n", dump[12]);
457 len += snprint(p+len, READSTR-len, "receive overrun errors: %lud\n", dump[13]);
458 len += snprint(p+len, READSTR-len, "receive collision detect errors: %lud\n", dump[14]);
459 len += snprint(p+len, READSTR-len, "receive short frame errors: %lud\n", dump[15]);
460 len += snprint(p+len, READSTR-len, "nop: %d\n", ctlr->nop);
461 if(ctlr->cbqmax > ctlr->cbqmaxhw)
462 ctlr->cbqmaxhw = ctlr->cbqmax;
463 len += snprint(p+len, READSTR-len, "cbqmax: %d\n", ctlr->cbqmax);
464 ctlr->cbqmax = 0;
465 len += snprint(p+len, READSTR-len, "threshold: %d\n", ctlr->threshold);
466
467 len += snprint(p+len, READSTR-len, "eeprom:");
468 for(i = 0; i < (1<<ctlr->eepromsz); i++){
469 if(i && ((i & 0x07) == 0))
470 len += snprint(p+len, READSTR-len, "\n ");
471 len += snprint(p+len, READSTR-len, " %4.4ux", ctlr->eeprom[i]);
472 }
473
474 if((ctlr->eeprom[6] & 0x1F00) && !(ctlr->eeprom[6] & 0x8000)){
475 phyaddr = ctlr->eeprom[6] & 0x00FF;
476 len += snprint(p+len, READSTR-len, "\nphy %2d:", phyaddr);
477 for(i = 0; i < 6; i++){
478 static int miir(Ctlr*, int, int);
479
480 len += snprint(p+len, READSTR-len, " %4.4ux",
481 miir(ctlr, phyaddr, i));
482 }
483 }
484
485 snprint(p+len, READSTR-len, "\n");
486 n = readstr(offset, a, n, p);
487 free(p);
488
489 return n;
490 }
491
492 static void
txstart(Ether * ether)493 txstart(Ether* ether)
494 {
495 Ctlr *ctlr;
496 Block *bp;
497 Cb *cb;
498
499 ctlr = ether->ctlr;
500 while(ctlr->cbq < (ctlr->ncb-1)){
501 cb = ctlr->cbhead->next;
502 if(ctlr->action == 0){
503 bp = qget(ether->oq);
504 if(bp == nil)
505 break;
506
507 cb->command = CbS|CbSF|CbTransmit;
508 cb->tbd = PADDR(&cb->tba);
509 cb->count = 0;
510 cb->threshold = ctlr->threshold;
511 cb->number = 1;
512 cb->tba = PADDR(bp->rp);
513 cb->bp = bp;
514 cb->tbasz = BLEN(bp);
515 }
516 else if(ctlr->action == CbConfigure){
517 cb->command = CbS|CbConfigure;
518 memmove(cb->data, ctlr->configdata, sizeof(ctlr->configdata));
519 ctlr->action = 0;
520 }
521 else if(ctlr->action == CbIAS){
522 cb->command = CbS|CbIAS;
523 memmove(cb->data, ether->ea, Eaddrlen);
524 ctlr->action = 0;
525 }
526 else if(ctlr->action == CbMAS){
527 cb->command = CbS|CbMAS;
528 memset(cb->data, 0, sizeof(cb->data));
529 ctlr->action = 0;
530 }
531 else{
532 print("#l%d: action %#ux\n", ether->ctlrno, ctlr->action);
533 ctlr->action = 0;
534 break;
535 }
536 cb->status = 0;
537
538 coherence();
539 ctlr->cbhead->command &= ~CbS;
540 ctlr->cbhead = cb;
541 ctlr->cbq++;
542 }
543
544 /*
545 * Workaround for some broken HUB chips
546 * when connected at 10Mb/s half-duplex.
547 */
548 if(ctlr->nop){
549 command(ctlr, CUnop, 0);
550 microdelay(1);
551 }
552 command(ctlr, CUresume, 0);
553
554 if(ctlr->cbq > ctlr->cbqmax)
555 ctlr->cbqmax = ctlr->cbq;
556 }
557
558 static void
configure(Ether * ether,int promiscuous)559 configure(Ether* ether, int promiscuous)
560 {
561 Ctlr *ctlr;
562
563 ctlr = ether->ctlr;
564 ilock(&ctlr->cblock);
565 if(promiscuous){
566 ctlr->configdata[6] |= 0x80; /* Save Bad Frames */
567 //ctlr->configdata[6] &= ~0x40; /* !Discard Overrun Rx Frames */
568 ctlr->configdata[7] &= ~0x01; /* !Discard Short Rx Frames */
569 ctlr->configdata[15] |= 0x01; /* Promiscuous mode */
570 ctlr->configdata[18] &= ~0x01; /* (!Padding enable?), !stripping enable */
571 ctlr->configdata[21] |= 0x08; /* Multi Cast ALL */
572 }
573 else{
574 ctlr->configdata[6] &= ~0x80;
575 //ctlr->configdata[6] |= 0x40;
576 ctlr->configdata[7] |= 0x01;
577 ctlr->configdata[15] &= ~0x01;
578 ctlr->configdata[18] |= 0x01; /* 0x03? */
579 ctlr->configdata[21] &= ~0x08;
580 }
581 ctlr->action = CbConfigure;
582 txstart(ether);
583 iunlock(&ctlr->cblock);
584 }
585
586 static void
promiscuous(void * arg,int on)587 promiscuous(void* arg, int on)
588 {
589 configure(arg, on);
590 }
591
592 static void
multicast(void * ether,uchar * addr,int add)593 multicast(void* ether, uchar *addr, int add)
594 {
595 USED(addr);
596 /*
597 * TODO: if (add) add addr to list of mcast addrs in controller
598 * else remove addr from list of mcast addrs in controller
599 * enable multicast input (see CbMAS) instead of promiscuous mode.
600 */
601 if (add)
602 configure(ether, 1);
603 }
604
605 static void
transmit(Ether * ether)606 transmit(Ether* ether)
607 {
608 Ctlr *ctlr;
609
610 ctlr = ether->ctlr;
611 ilock(&ctlr->cblock);
612 txstart(ether);
613 iunlock(&ctlr->cblock);
614 }
615
616 static void
receive(Ether * ether)617 receive(Ether* ether)
618 {
619 Rfd *rfd;
620 Ctlr *ctlr;
621 int count;
622 Block *bp, *pbp, *xbp;
623
624 ctlr = ether->ctlr;
625 bp = ctlr->rfdhead;
626 for(rfd = (Rfd*)bp->rp; rfd->field & RfdC; rfd = (Rfd*)bp->rp){
627 /*
628 * If it's an OK receive frame
629 * 1) save the count
630 * 2) if it's small, try to allocate a block and copy
631 * the data, then adjust the necessary fields for reuse;
632 * 3) if it's big, try to allocate a new Rfd and if
633 * successful
634 * adjust the received buffer pointers for the
635 * actual data received;
636 * initialise the replacement buffer to point to
637 * the next in the ring;
638 * initialise bp to point to the replacement;
639 * 4) if there's a good packet, pass it on for disposal.
640 */
641 if(rfd->field & RfdOK){
642 pbp = nil;
643 count = rfd->count & 0x3FFF;
644 if((count < ETHERMAXTU/4) && (pbp = iallocb(count))){
645 memmove(pbp->rp, bp->rp+offsetof(Rfd, data[0]), count);
646 pbp->wp = pbp->rp + count;
647
648 rfd->count = 0;
649 rfd->field = 0;
650 }
651 else if(xbp = rfdalloc(rfd->link)){
652 bp->rp += offsetof(Rfd, data[0]);
653 bp->wp = bp->rp + count;
654
655 xbp->next = bp->next;
656 bp->next = 0;
657
658 pbp = bp;
659 bp = xbp;
660 }
661 if(pbp != nil)
662 etheriq(ether, pbp, 1);
663 }
664 else{
665 rfd->count = 0;
666 rfd->field = 0;
667 }
668
669 /*
670 * The ring tail pointer follows the head with with one
671 * unused buffer in between to defeat hardware prefetch;
672 * once the tail pointer has been bumped on to the next
673 * and the new tail has the Suspend bit set, it can be
674 * removed from the old tail buffer.
675 * As a replacement for the current head buffer may have
676 * been allocated above, ensure that the new tail points
677 * to it (next and link).
678 */
679 rfd = (Rfd*)ctlr->rfdtail->rp;
680 ctlr->rfdtail = ctlr->rfdtail->next;
681 ctlr->rfdtail->next = bp;
682 ((Rfd*)ctlr->rfdtail->rp)->link = PADDR(bp->rp);
683 ((Rfd*)ctlr->rfdtail->rp)->field |= RfdS;
684 coherence();
685 rfd->field &= ~RfdS;
686
687 /*
688 * Finally done with the current (possibly replaced)
689 * head, move on to the next and maintain the sentinel
690 * between tail and head.
691 */
692 ctlr->rfdhead = bp->next;
693 bp = ctlr->rfdhead;
694 }
695 }
696
697 static void
interrupt(Ureg *,void * arg)698 interrupt(Ureg*, void* arg)
699 {
700 Cb* cb;
701 Ctlr *ctlr;
702 Ether *ether;
703 int status;
704
705 ether = arg;
706 ctlr = ether->ctlr;
707
708 for(;;){
709 ilock(&ctlr->rlock);
710 status = csr16r(ctlr, Status);
711 csr8w(ctlr, Ack, (status>>8) & 0xFF);
712 iunlock(&ctlr->rlock);
713
714 if(!(status & (StatCX|StatFR|StatCNA|StatRNR|StatMDI|StatSWI)))
715 break;
716
717 /*
718 * If the watchdog timer for the receiver lockup errata is running,
719 * let it know the receiver is active.
720 */
721 if(status & (StatFR|StatRNR)){
722 ilock(&ctlr->cblock);
723 ctlr->tick = 0;
724 iunlock(&ctlr->cblock);
725 }
726
727 if(status & StatFR){
728 receive(ether);
729 status &= ~StatFR;
730 }
731
732 if(status & StatRNR){
733 command(ctlr, RUresume, 0);
734 status &= ~StatRNR;
735 }
736
737 if(status & StatCNA){
738 ilock(&ctlr->cblock);
739
740 cb = ctlr->cbtail;
741 while(ctlr->cbq){
742 if(!(cb->status & CbC))
743 break;
744 if(cb->bp){
745 freeb(cb->bp);
746 cb->bp = nil;
747 }
748 if((cb->status & CbU) && ctlr->threshold < 0xE0)
749 ctlr->threshold++;
750
751 ctlr->cbq--;
752 cb = cb->next;
753 }
754 ctlr->cbtail = cb;
755
756 txstart(ether);
757 iunlock(&ctlr->cblock);
758
759 status &= ~StatCNA;
760 }
761
762 if(status & (StatCX|StatFR|StatCNA|StatRNR|StatMDI|StatSWI))
763 panic("#l%d: status %#ux\n", ether->ctlrno, status);
764 }
765 }
766
767 static void
ctlrinit(Ctlr * ctlr)768 ctlrinit(Ctlr* ctlr)
769 {
770 int i;
771 Block *bp;
772 Rfd *rfd;
773 ulong link;
774
775 /*
776 * Create the Receive Frame Area (RFA) as a ring of allocated
777 * buffers.
778 * A sentinel buffer is maintained between the last buffer in
779 * the ring (marked with RfdS) and the head buffer to defeat the
780 * hardware prefetch of the next RFD and allow dynamic buffer
781 * allocation.
782 */
783 link = NullPointer;
784 for(i = 0; i < Nrfd; i++){
785 bp = rfdalloc(link);
786 if(ctlr->rfdhead == nil)
787 ctlr->rfdtail = bp;
788 bp->next = ctlr->rfdhead;
789 ctlr->rfdhead = bp;
790 link = PADDR(bp->rp);
791 }
792 ctlr->rfdtail->next = ctlr->rfdhead;
793 rfd = (Rfd*)ctlr->rfdtail->rp;
794 rfd->link = PADDR(ctlr->rfdhead->rp);
795 rfd->field |= RfdS;
796 ctlr->rfdhead = ctlr->rfdhead->next;
797
798 /*
799 * Create a ring of control blocks for the
800 * transmit side.
801 */
802 ilock(&ctlr->cblock);
803 ctlr->cbr = malloc(ctlr->ncb*sizeof(Cb));
804 if(ctlr->cbr == nil) {
805 iunlock(&ctlr->cblock);
806 error(Enomem);
807 }
808 for(i = 0; i < ctlr->ncb; i++){
809 ctlr->cbr[i].status = CbC|CbOK;
810 ctlr->cbr[i].command = CbS|CbNOP;
811 ctlr->cbr[i].link = PADDR(&ctlr->cbr[NEXT(i, ctlr->ncb)].status);
812 ctlr->cbr[i].next = &ctlr->cbr[NEXT(i, ctlr->ncb)];
813 }
814 ctlr->cbhead = ctlr->cbr;
815 ctlr->cbtail = ctlr->cbr;
816 ctlr->cbq = 0;
817
818 memmove(ctlr->configdata, configdata, sizeof(configdata));
819 ctlr->threshold = 80;
820 ctlr->tick = 0;
821
822 iunlock(&ctlr->cblock);
823 }
824
825 static int
miir(Ctlr * ctlr,int phyadd,int regadd)826 miir(Ctlr* ctlr, int phyadd, int regadd)
827 {
828 int mcr, timo;
829
830 lock(&ctlr->miilock);
831 csr32w(ctlr, Mcr, MDIread|(phyadd<<21)|(regadd<<16));
832 mcr = 0;
833 for(timo = 64; timo; timo--){
834 mcr = csr32r(ctlr, Mcr);
835 if(mcr & MDIready)
836 break;
837 microdelay(1);
838 }
839 unlock(&ctlr->miilock);
840
841 if(mcr & MDIready)
842 return mcr & 0xFFFF;
843
844 return -1;
845 }
846
847 static int
miiw(Ctlr * ctlr,int phyadd,int regadd,int data)848 miiw(Ctlr* ctlr, int phyadd, int regadd, int data)
849 {
850 int mcr, timo;
851
852 lock(&ctlr->miilock);
853 csr32w(ctlr, Mcr, MDIwrite|(phyadd<<21)|(regadd<<16)|(data & 0xFFFF));
854 mcr = 0;
855 for(timo = 64; timo; timo--){
856 mcr = csr32r(ctlr, Mcr);
857 if(mcr & MDIready)
858 break;
859 microdelay(1);
860 }
861 unlock(&ctlr->miilock);
862
863 if(mcr & MDIready)
864 return 0;
865
866 return -1;
867 }
868
869 static int
hy93c46r(Ctlr * ctlr,int r)870 hy93c46r(Ctlr* ctlr, int r)
871 {
872 int data, i, op, size;
873
874 /*
875 * Hyundai HY93C46 or equivalent serial EEPROM.
876 * This sequence for reading a 16-bit register 'r'
877 * in the EEPROM is taken straight from Section
878 * 3.3.4.2 of the Intel 82557 User's Guide.
879 */
880 reread:
881 csr16w(ctlr, Ecr, EEcs);
882 op = EEstart|EEread;
883 for(i = 2; i >= 0; i--){
884 data = (((op>>i) & 0x01)<<2)|EEcs;
885 csr16w(ctlr, Ecr, data);
886 csr16w(ctlr, Ecr, data|EEsk);
887 microdelay(1);
888 csr16w(ctlr, Ecr, data);
889 microdelay(1);
890 }
891
892 /*
893 * First time through must work out the EEPROM size.
894 */
895 if((size = ctlr->eepromsz) == 0)
896 size = 8;
897
898 for(size = size-1; size >= 0; size--){
899 data = (((r>>size) & 0x01)<<2)|EEcs;
900 csr16w(ctlr, Ecr, data);
901 csr16w(ctlr, Ecr, data|EEsk);
902 delay(1);
903 csr16w(ctlr, Ecr, data);
904 microdelay(1);
905 if(!(csr16r(ctlr, Ecr) & EEdo))
906 break;
907 }
908
909 data = 0;
910 for(i = 15; i >= 0; i--){
911 csr16w(ctlr, Ecr, EEcs|EEsk);
912 microdelay(1);
913 if(csr16r(ctlr, Ecr) & EEdo)
914 data |= (1<<i);
915 csr16w(ctlr, Ecr, EEcs);
916 microdelay(1);
917 }
918
919 csr16w(ctlr, Ecr, 0);
920
921 if(ctlr->eepromsz == 0){
922 ctlr->eepromsz = 8-size;
923 ctlr->eeprom = malloc((1<<ctlr->eepromsz)*sizeof(ushort));
924 if(ctlr->eeprom == nil)
925 error(Enomem);
926 goto reread;
927 }
928
929 return data;
930 }
931
932 static void
i82557pci(void)933 i82557pci(void)
934 {
935 Pcidev *p;
936 Ctlr *ctlr;
937 int i, nop, port;
938
939 p = nil;
940 nop = 0;
941 while(p = pcimatch(p, 0x8086, 0)){
942 switch(p->did){
943 default:
944 continue;
945 case 0x1031: /* Intel 82562EM */
946 case 0x103B: /* Intel 82562EM */
947 case 0x103C: /* Intel 82562EM */
948 case 0x1050: /* Intel 82562EZ */
949 case 0x1039: /* Intel 82801BD PRO/100 VE */
950 case 0x103A: /* Intel 82562 PRO/100 VE */
951 case 0x103D: /* Intel 82562 PRO/100 VE */
952 case 0x1064: /* Intel 82562 PRO/100 VE */
953 case 0x2449: /* Intel 82562ET */
954 case 0x27DC: /* Intel 82801G PRO/100 VE */
955 nop = 1;
956 /*FALLTHROUGH*/
957 case 0x1209: /* Intel 82559ER */
958 case 0x1229: /* Intel 8255[789] */
959 case 0x1030: /* Intel 82559 InBusiness 10/100 */
960 break;
961 }
962
963 if(pcigetpms(p) > 0){
964 pcisetpms(p, 0);
965
966 for(i = 0; i < 6; i++)
967 pcicfgw32(p, PciBAR0+i*4, p->mem[i].bar);
968 pcicfgw8(p, PciINTL, p->intl);
969 pcicfgw8(p, PciLTR, p->ltr);
970 pcicfgw8(p, PciCLS, p->cls);
971 pcicfgw16(p, PciPCR, p->pcr);
972 }
973
974 /*
975 * bar[0] is the memory-mapped register address (4KB),
976 * bar[1] is the I/O port register address (32 bytes) and
977 * bar[2] is for the flash ROM (1MB).
978 */
979 port = p->mem[1].bar & ~0x01;
980 if(ioalloc(port, p->mem[1].size, 0, "i82557") < 0){
981 print("i82557: port %#ux in use\n", port);
982 continue;
983 }
984
985 ctlr = malloc(sizeof(Ctlr));
986 if(ctlr == nil)
987 error(Enomem);
988 ctlr->port = port;
989 ctlr->pcidev = p;
990 ctlr->nop = nop;
991
992 if(ctlrhead != nil)
993 ctlrtail->next = ctlr;
994 else
995 ctlrhead = ctlr;
996 ctlrtail = ctlr;
997
998 pcisetbme(p);
999 }
1000 }
1001
1002 static char* mediatable[9] = {
1003 "10BASE-T", /* TP */
1004 "10BASE-2", /* BNC */
1005 "10BASE-5", /* AUI */
1006 "100BASE-TX",
1007 "10BASE-TFD",
1008 "100BASE-TXFD",
1009 "100BASE-T4",
1010 "100BASE-FX",
1011 "100BASE-FXFD",
1012 };
1013
1014 static int
scanphy(Ctlr * ctlr)1015 scanphy(Ctlr* ctlr)
1016 {
1017 int i, oui, x;
1018
1019 for(i = 0; i < 32; i++){
1020 if((oui = miir(ctlr, i, 2)) == -1 || oui == 0 || oui == 0xFFFF)
1021 continue;
1022 oui <<= 6;
1023 x = miir(ctlr, i, 3);
1024 oui |= x>>10;
1025 //print("phy%d: oui %#ux reg1 %#ux\n", i, oui, miir(ctlr, i, 1));
1026
1027 ctlr->eeprom[6] = i;
1028 if(oui == 0xAA00)
1029 ctlr->eeprom[6] |= 0x07<<8;
1030 else if(oui == 0x80017){
1031 if(x & 0x01)
1032 ctlr->eeprom[6] |= 0x0A<<8;
1033 else
1034 ctlr->eeprom[6] |= 0x04<<8;
1035 }
1036 return i;
1037 }
1038 return -1;
1039 }
1040
1041 static void
shutdown(Ether * ether)1042 shutdown(Ether* ether)
1043 {
1044 Ctlr *ctlr = ether->ctlr;
1045
1046 print("ether82557 shutting down\n");
1047 csr32w(ctlr, Port, 0);
1048 delay(1);
1049 csr8w(ctlr, Interrupt, InterruptM);
1050 }
1051
1052
1053 static int
reset(Ether * ether)1054 reset(Ether* ether)
1055 {
1056 int anar, anlpar, bmcr, bmsr, i, k, medium, phyaddr, x;
1057 unsigned short sum;
1058 uchar ea[Eaddrlen];
1059 Ctlr *ctlr;
1060
1061 if(ctlrhead == nil)
1062 i82557pci();
1063
1064 /*
1065 * Any adapter matches if no ether->port is supplied,
1066 * otherwise the ports must match.
1067 */
1068 for(ctlr = ctlrhead; ctlr != nil; ctlr = ctlr->next){
1069 if(ctlr->active)
1070 continue;
1071 if(ether->port == 0 || ether->port == ctlr->port){
1072 ctlr->active = 1;
1073 break;
1074 }
1075 }
1076 if(ctlr == nil)
1077 return -1;
1078
1079 /*
1080 * Initialise the Ctlr structure.
1081 * Perform a software reset after which should ensure busmastering
1082 * is still enabled. The EtherExpress PRO/100B appears to leave
1083 * the PCI configuration alone (see the 'To do' list above) so punt
1084 * for now.
1085 * Load the RUB and CUB registers for linear addressing (0).
1086 */
1087 ether->ctlr = ctlr;
1088 ether->port = ctlr->port;
1089 ether->irq = ctlr->pcidev->intl;
1090 ether->tbdf = ctlr->pcidev->tbdf;
1091
1092 ilock(&ctlr->rlock);
1093 csr32w(ctlr, Port, 0);
1094 delay(1);
1095 csr8w(ctlr, Interrupt, InterruptM);
1096 iunlock(&ctlr->rlock);
1097
1098 command(ctlr, LoadRUB, 0);
1099 command(ctlr, LoadCUB, 0);
1100 command(ctlr, LoadDCA, PADDR(ctlr->dump));
1101
1102 /*
1103 * Initialise the receive frame, transmit ring and configuration areas.
1104 */
1105 ctlr->ncb = Ncb;
1106 ctlrinit(ctlr);
1107
1108 /*
1109 * Read the EEPROM.
1110 * Do a dummy read first to get the size
1111 * and allocate ctlr->eeprom.
1112 */
1113 hy93c46r(ctlr, 0);
1114 sum = 0;
1115 for(i = 0; i < (1<<ctlr->eepromsz); i++){
1116 x = hy93c46r(ctlr, i);
1117 ctlr->eeprom[i] = x;
1118 sum += x;
1119 }
1120 if(sum != 0xBABA)
1121 print("#l%d: EEPROM checksum - %#4.4ux\n", ether->ctlrno, sum);
1122
1123 /*
1124 * Eeprom[6] indicates whether there is a PHY and whether
1125 * it's not 10Mb-only, in which case use the given PHY address
1126 * to set any PHY specific options and determine the speed.
1127 * Unfortunately, sometimes the EEPROM is blank except for
1128 * the ether address and checksum; in this case look at the
1129 * controller type and if it's am 82558 or 82559 it has an
1130 * embedded PHY so scan for that.
1131 * If no PHY, assume 82503 (serial) operation.
1132 */
1133 if((ctlr->eeprom[6] & 0x1F00) && !(ctlr->eeprom[6] & 0x8000))
1134 phyaddr = ctlr->eeprom[6] & 0x00FF;
1135 else
1136 switch(ctlr->pcidev->rid){
1137 case 0x01: /* 82557 A-step */
1138 case 0x02: /* 82557 B-step */
1139 case 0x03: /* 82557 C-step */
1140 default:
1141 phyaddr = -1;
1142 break;
1143 case 0x04: /* 82558 A-step */
1144 case 0x05: /* 82558 B-step */
1145 case 0x06: /* 82559 A-step */
1146 case 0x07: /* 82559 B-step */
1147 case 0x08: /* 82559 C-step */
1148 case 0x09: /* 82559ER A-step */
1149 phyaddr = scanphy(ctlr);
1150 break;
1151 }
1152 if(phyaddr >= 0){
1153 /*
1154 * Resolve the highest common ability of the two
1155 * link partners. In descending order:
1156 * 0x0100 100BASE-TX Full Duplex
1157 * 0x0200 100BASE-T4
1158 * 0x0080 100BASE-TX
1159 * 0x0040 10BASE-T Full Duplex
1160 * 0x0020 10BASE-T
1161 */
1162 anar = miir(ctlr, phyaddr, 0x04);
1163 anlpar = miir(ctlr, phyaddr, 0x05) & 0x03E0;
1164 anar &= anlpar;
1165 bmcr = 0;
1166 if(anar & 0x380)
1167 bmcr = 0x2000;
1168 if(anar & 0x0140)
1169 bmcr |= 0x0100;
1170
1171 switch((ctlr->eeprom[6]>>8) & 0x001F){
1172
1173 case 0x04: /* DP83840 */
1174 case 0x0A: /* DP83840A */
1175 /*
1176 * The DP83840[A] requires some tweaking for
1177 * reliable operation.
1178 * The manual says bit 10 should be unconditionally
1179 * set although it supposedly only affects full-duplex
1180 * operation (an & 0x0140).
1181 */
1182 x = miir(ctlr, phyaddr, 0x17) & ~0x0520;
1183 x |= 0x0420;
1184 for(i = 0; i < ether->nopt; i++){
1185 if(cistrcmp(ether->opt[i], "congestioncontrol"))
1186 continue;
1187 x |= 0x0100;
1188 break;
1189 }
1190 miiw(ctlr, phyaddr, 0x17, x);
1191
1192 /*
1193 * If the link partner can't autonegotiate, determine
1194 * the speed from elsewhere.
1195 */
1196 if(anlpar == 0){
1197 miir(ctlr, phyaddr, 0x01);
1198 bmsr = miir(ctlr, phyaddr, 0x01);
1199 x = miir(ctlr, phyaddr, 0x19);
1200 if((bmsr & 0x0004) && !(x & 0x0040))
1201 bmcr = 0x2000;
1202 }
1203 break;
1204
1205 case 0x07: /* Intel 82555 */
1206 /*
1207 * Auto-negotiation may fail if the other end is
1208 * a DP83840A and the cable is short.
1209 */
1210 miir(ctlr, phyaddr, 0x01);
1211 bmsr = miir(ctlr, phyaddr, 0x01);
1212 if((miir(ctlr, phyaddr, 0) & 0x1000) && !(bmsr & 0x0020)){
1213 miiw(ctlr, phyaddr, 0x1A, 0x2010);
1214 x = miir(ctlr, phyaddr, 0);
1215 miiw(ctlr, phyaddr, 0, 0x0200|x);
1216 for(i = 0; i < 3000; i++){
1217 delay(1);
1218 if(miir(ctlr, phyaddr, 0x01) & 0x0020)
1219 break;
1220 }
1221 miiw(ctlr, phyaddr, 0x1A, 0x2000);
1222
1223 anar = miir(ctlr, phyaddr, 0x04);
1224 anlpar = miir(ctlr, phyaddr, 0x05) & 0x03E0;
1225 anar &= anlpar;
1226 bmcr = 0;
1227 if(anar & 0x380)
1228 bmcr = 0x2000;
1229 if(anar & 0x0140)
1230 bmcr |= 0x0100;
1231 }
1232 break;
1233 }
1234
1235 /*
1236 * Force speed and duplex if no auto-negotiation.
1237 */
1238 if(anlpar == 0){
1239 medium = -1;
1240 for(i = 0; i < ether->nopt; i++){
1241 for(k = 0; k < nelem(mediatable); k++){
1242 if(cistrcmp(mediatable[k], ether->opt[i]))
1243 continue;
1244 medium = k;
1245 break;
1246 }
1247
1248 switch(medium){
1249 default:
1250 break;
1251
1252 case 0x00: /* 10BASE-T */
1253 case 0x01: /* 10BASE-2 */
1254 case 0x02: /* 10BASE-5 */
1255 bmcr &= ~(0x2000|0x0100);
1256 ctlr->configdata[19] &= ~0x40;
1257 break;
1258
1259 case 0x03: /* 100BASE-TX */
1260 case 0x06: /* 100BASE-T4 */
1261 case 0x07: /* 100BASE-FX */
1262 ctlr->configdata[19] &= ~0x40;
1263 bmcr |= 0x2000;
1264 break;
1265
1266 case 0x04: /* 10BASE-TFD */
1267 bmcr = (bmcr & ~0x2000)|0x0100;
1268 ctlr->configdata[19] |= 0x40;
1269 break;
1270
1271 case 0x05: /* 100BASE-TXFD */
1272 case 0x08: /* 100BASE-FXFD */
1273 bmcr |= 0x2000|0x0100;
1274 ctlr->configdata[19] |= 0x40;
1275 break;
1276 }
1277 }
1278 if(medium != -1)
1279 miiw(ctlr, phyaddr, 0x00, bmcr);
1280 }
1281
1282 if(bmcr & 0x2000)
1283 ether->mbps = 100;
1284
1285 ctlr->configdata[8] = 1;
1286 ctlr->configdata[15] &= ~0x80;
1287 }
1288 else{
1289 ctlr->configdata[8] = 0;
1290 ctlr->configdata[15] |= 0x80;
1291 }
1292
1293 /*
1294 * Workaround for some broken HUB chips when connected at 10Mb/s
1295 * half-duplex.
1296 * This is a band-aid, but as there's no dynamic auto-negotiation
1297 * code at the moment, only deactivate the workaround code in txstart
1298 * if the link is 100Mb/s.
1299 */
1300 if(ether->mbps != 10)
1301 ctlr->nop = 0;
1302
1303 /*
1304 * Load the chip configuration and start it off.
1305 */
1306 if(ether->oq == 0)
1307 ether->oq = qopen(64*1024, Qmsg, 0, 0);
1308 configure(ether, 0);
1309 command(ctlr, CUstart, PADDR(&ctlr->cbr->status));
1310
1311 /*
1312 * Check if the adapter's station address is to be overridden.
1313 * If not, read it from the EEPROM and set in ether->ea prior to loading
1314 * the station address with the Individual Address Setup command.
1315 */
1316 memset(ea, 0, Eaddrlen);
1317 if(memcmp(ea, ether->ea, Eaddrlen) == 0){
1318 for(i = 0; i < Eaddrlen/2; i++){
1319 x = ctlr->eeprom[i];
1320 ether->ea[2*i] = x;
1321 ether->ea[2*i+1] = x>>8;
1322 }
1323 }
1324
1325 ilock(&ctlr->cblock);
1326 ctlr->action = CbIAS;
1327 txstart(ether);
1328 iunlock(&ctlr->cblock);
1329
1330 /*
1331 * Linkage to the generic ethernet driver.
1332 */
1333 ether->attach = attach;
1334 ether->transmit = transmit;
1335 ether->interrupt = interrupt;
1336 ether->ifstat = ifstat;
1337 ether->shutdown = shutdown;
1338
1339 ether->promiscuous = promiscuous;
1340 ether->multicast = multicast;
1341 ether->arg = ether;
1342
1343 return 0;
1344 }
1345
1346 void
ether82557link(void)1347 ether82557link(void)
1348 {
1349 addethercard("i82557", reset);
1350 }
1351