xref: /plan9/sys/src/9/pc/ether8169.c (revision ed8b952fb9064951ec9021247571fa072807b688) 
1 /*
2  * Realtek RTL8110S/8169S.
3  * Mostly there. There are some magic register values used
4  * which are not described in any datasheet or driver but seem
5  * to be necessary.
6  * No tuning has been done. Only tested on an RTL8110S, there
7  * are slight differences between the chips in the series so some
8  * tweaks may be needed.
9  */
10 #include "u.h"
11 #include "../port/lib.h"
12 #include "mem.h"
13 #include "dat.h"
14 #include "fns.h"
15 #include "io.h"
16 #include "../port/error.h"
17 #include "../port/netif.h"
18 
19 #include "etherif.h"
20 #include "ethermii.h"
21 
22 enum {					/* registers */
23 	Idr0		= 0x00,		/* MAC address */
24 	Mar0		= 0x08,		/* Multicast address */
25 	Dtccr		= 0x10,		/* Dump Tally Counter Command */
26 	Tnpds		= 0x20,		/* Transmit Normal Priority Descriptors */
27 	Thpds		= 0x28,		/* Transmit High Priority Descriptors */
28 	Flash		= 0x30,		/* Flash Memory Read/Write */
29 	Erbcr		= 0x34,		/* Early Receive Byte Count */
30 	Ersr		= 0x36,		/* Early Receive Status */
31 	Cr		= 0x37,		/* Command Register */
32 	Tppoll		= 0x38,		/* Transmit Priority Polling */
33 	Imr		= 0x3C,		/* Interrupt Mask */
34 	Isr		= 0x3E,		/* Interrupt Status */
35 	Tcr		= 0x40,		/* Transmit Configuration */
36 	Rcr		= 0x44,		/* Receive Configuration */
37 	Tctr		= 0x48,		/* Timer Count */
38 	Mpc		= 0x4C,		/* Missed Packet Counter */
39 	Cr9346		= 0x50,		/* 9346 Command Register */
40 	Config0		= 0x51,		/* Configuration Register 0 */
41 	Config1		= 0x52,		/* Configuration Register 1 */
42 	Config2		= 0x53,		/* Configuration Register 2 */
43 	Config3		= 0x54,		/* Configuration Register 3 */
44 	Config4		= 0x55,		/* Configuration Register 4 */
45 	Config5		= 0x56,		/* Configuration Register 5 */
46 	Timerint	= 0x58,		/* Timer Interrupt */
47 	Mulint		= 0x5C,		/* Multiple Interrupt Select */
48 	Phyar		= 0x60,		/* PHY Access */
49 	Tbicsr0		= 0x64,		/* TBI Control and Status */
50 	Tbianar		= 0x68,		/* TBI Auto-Negotiation Advertisment */
51 	Tbilpar		= 0x6A,		/* TBI Auto-Negotiation Link Partner */
52 	Phystatus	= 0x6C,		/* PHY Status */
53 
54 	Rms		= 0xDA,		/* Receive Packet Maximum Size */
55 	Cplusc		= 0xE0,		/* C+ Command */
56 	Rdsar		= 0xE4,		/* Receive Descriptor Start Address */
57 	Mtps		= 0xEC,		/* Max. Transmit Packet Size */
58 };
59 
60 enum {					/* Dtccr */
61 	Cmd		= 0x00000008,	/* Command */
62 };
63 
64 enum {					/* Cr */
65 	Te		= 0x04,		/* Transmitter Enable */
66 	Re		= 0x08,		/* Receiver Enable */
67 	Rst		= 0x10,		/* Software Reset */
68 };
69 
70 enum {					/* Tppoll */
71 	Fswint		= 0x01,		/* Forced Software Interrupt */
72 	Npq		= 0x40,		/* Normal Priority Queue polling */
73 	Hpq		= 0x80,		/* High Priority Queue polling */
74 };
75 
76 enum {					/* Imr/Isr */
77 	Rok		= 0x0001,	/* Receive OK */
78 	Rer		= 0x0002,	/* Receive Error */
79 	Tok		= 0x0004,	/* Transmit OK */
80 	Ter		= 0x0008,	/* Transmit Error */
81 	Rdu		= 0x0010,	/* Receive Descriptor Unavailable */
82 	Punlc		= 0x0020,	/* Packet Underrun or Link Change */
83 	Fovw		= 0x0040,	/* Receive FIFO Overflow */
84 	Tdu		= 0x0080,	/* Transmit Descriptor Unavailable */
85 	Swint		= 0x0100,	/* Software Interrupt */
86 	Timeout		= 0x4000,	/* Timer */
87 	Serr		= 0x8000,	/* System Error */
88 };
89 
90 enum {					/* Tcr */
91 	MtxdmaSHIFT	= 8,		/* Max. DMA Burst Size */
92 	MtxdmaMASK	= 0x00000700,
93 	Mtxdmaunlimited	= 0x00000700,
94 	Acrc		= 0x00010000,	/* Append CRC (not) */
95 	Lbk0		= 0x00020000,	/* Loopback Test 0 */
96 	Lbk1		= 0x00040000,	/* Loopback Test 1 */
97 	Ifg2		= 0x00080000,	/* Interframe Gap 2 */
98 	HwveridSHIFT	= 23,		/* Hardware Version ID */
99 	HwveridMASK	= 0x7C800000,
100 	Macv01		= 0x00000000,	/* RTL8169 */
101 	Macv02		= 0x00800000,	/* RTL8169S/8110S */
102 	Macv03		= 0x04000000,	/* RTL8169S/8110S */
103 	Macv04		= 0x10000000,	/* RTL8169SB/8110SB */
104 	Macv05		= 0x18000000,	/* RTL8169SC/8110SC */
105 	Macv11		= 0x30000000,	/* RTL8168B/8111B */
106 	Macv12		= 0x38000000,	/* RTL8169B/8111B */
107 	Macv13		= 0x34000000,	/* RTL8101E */
108 	Macv14		= 0x30800000,	/* RTL8100E */
109 	Macv15		= 0x38800000,	/* RTL8100E */
110 	Ifg0		= 0x01000000,	/* Interframe Gap 0 */
111 	Ifg1		= 0x02000000,	/* Interframe Gap 1 */
112 };
113 
114 enum {					/* Rcr */
115 	Aap		= 0x00000001,	/* Accept All Packets */
116 	Apm		= 0x00000002,	/* Accept Physical Match */
117 	Am		= 0x00000004,	/* Accept Multicast */
118 	Ab		= 0x00000008,	/* Accept Broadcast */
119 	Ar		= 0x00000010,	/* Accept Runt */
120 	Aer		= 0x00000020,	/* Accept Error */
121 	Sel9356		= 0x00000040,	/* 9356 EEPROM used */
122 	MrxdmaSHIFT	= 8,		/* Max. DMA Burst Size */
123 	MrxdmaMASK	= 0x00000700,
124 	Mrxdmaunlimited	= 0x00000700,
125 	RxfthSHIFT	= 13,		/* Receive Buffer Length */
126 	RxfthMASK	= 0x0000E000,
127 	Rxfth256	= 0x00008000,
128 	Rxfthnone	= 0x0000E000,
129 	Rer8		= 0x00010000,	/* Accept Error Packets > 8 bytes */
130 	MulERINT	= 0x01000000,	/* Multiple Early Interrupt Select */
131 };
132 
133 enum {					/* Cr9346 */
134 	Eedo		= 0x01,		/* */
135 	Eedi		= 0x02,		/* */
136 	Eesk		= 0x04,		/* */
137 	Eecs		= 0x08,		/* */
138 	Eem0		= 0x40,		/* Operating Mode */
139 	Eem1		= 0x80,
140 };
141 
142 enum {					/* Phyar */
143 	DataMASK	= 0x0000FFFF,	/* 16-bit GMII/MII Register Data */
144 	DataSHIFT	= 0,
145 	RegaddrMASK	= 0x001F0000,	/* 5-bit GMII/MII Register Address */
146 	RegaddrSHIFT	= 16,
147 	Flag		= 0x80000000,	/* */
148 };
149 
150 enum {					/* Phystatus */
151 	Fd		= 0x01,		/* Full Duplex */
152 	Linksts		= 0x02,		/* Link Status */
153 	Speed10		= 0x04,		/* */
154 	Speed100	= 0x08,		/* */
155 	Speed1000	= 0x10,		/* */
156 	Rxflow		= 0x20,		/* */
157 	Txflow		= 0x40,		/* */
158 	Entbi		= 0x80,		/* */
159 };
160 
161 enum {					/* Cplusc */
162 	Mulrw		= 0x0008,	/* PCI Multiple R/W Enable */
163 	Dac		= 0x0010,	/* PCI Dual Address Cycle Enable */
164 	Rxchksum	= 0x0020,	/* Receive Checksum Offload Enable */
165 	Rxvlan		= 0x0040,	/* Receive VLAN De-tagging Enable */
166 	Endian		= 0x0200,	/* Endian Mode */
167 };
168 
169 typedef struct D D;			/* Transmit/Receive Descriptor */
170 struct D {
171 	u32int	control;
172 	u32int	vlan;
173 	u32int	addrlo;
174 	u32int	addrhi;
175 };
176 
177 enum {					/* Transmit Descriptor control */
178 	TxflMASK	= 0x0000FFFF,	/* Transmit Frame Length */
179 	TxflSHIFT	= 0,
180 	Tcps		= 0x00010000,	/* TCP Checksum Offload */
181 	Udpcs		= 0x00020000,	/* UDP Checksum Offload */
182 	Ipcs		= 0x00040000,	/* IP Checksum Offload */
183 	Lgsen		= 0x08000000,	/* Large Send */
184 };
185 
186 enum {					/* Receive Descriptor control */
187 	RxflMASK	= 0x00003FFF,	/* Receive Frame Length */
188 	RxflSHIFT	= 0,
189 	Tcpf		= 0x00004000,	/* TCP Checksum Failure */
190 	Udpf		= 0x00008000,	/* UDP Checksum Failure */
191 	Ipf		= 0x00010000,	/* IP Checksum Failure */
192 	Pid0		= 0x00020000,	/* Protocol ID0 */
193 	Pid1		= 0x00040000,	/* Protocol ID1 */
194 	Crce		= 0x00080000,	/* CRC Error */
195 	Runt		= 0x00100000,	/* Runt Packet */
196 	Res		= 0x00200000,	/* Receive Error Summary */
197 	Rwt		= 0x00400000,	/* Receive Watchdog Timer Expired */
198 	Fovf		= 0x00800000,	/* FIFO Overflow */
199 	Bovf		= 0x01000000,	/* Buffer Overflow */
200 	Bar		= 0x02000000,	/* Broadcast Address Received */
201 	Pam		= 0x04000000,	/* Physical Address Matched */
202 	Mar		= 0x08000000,	/* Multicast Address Received */
203 };
204 
205 enum {					/* General Descriptor control */
206 	Ls		= 0x10000000,	/* Last Segment Descriptor */
207 	Fs		= 0x20000000,	/* First Segment Descriptor */
208 	Eor		= 0x40000000,	/* End of Descriptor Ring */
209 	Own		= 0x80000000,	/* Ownership */
210 };
211 
212 /*
213  */
214 enum {					/* Ring sizes  (<= 1024) */
215 	Ntd		= 32,		/* Transmit Ring */
216 	Nrd		= 128,		/* Receive Ring */
217 
218 	Mps		= ROUNDUP(ETHERMAXTU+4, 128),
219 };
220 
221 typedef struct Dtcc Dtcc;
222 struct Dtcc {
223 	u64int	txok;
224 	u64int	rxok;
225 	u64int	txer;
226 	u32int	rxer;
227 	u16int	misspkt;
228 	u16int	fae;
229 	u32int	tx1col;
230 	u32int	txmcol;
231 	u64int	rxokph;
232 	u64int	rxokbrd;
233 	u32int	rxokmu;
234 	u16int	txabt;
235 	u16int	txundrn;
236 };
237 
238 enum {						/* Variants */
239 	Rtl8100e	= (0x8136<<16)|0x10EC,	/* RTL810[01]E ? */
240 	Rtl8169c	= (0x0116<<16)|0x16EC,	/* RTL8169C+ (USR997902) */
241 	Rtl8169sc	= (0x8167<<16)|0x10EC,	/* RTL8169SC */
242 	Rtl8168b	= (0x8168<<16)|0x10EC,	/* RTL8168B */
243 	Rtl8169		= (0x8169<<16)|0x10EC,	/* RTL8169 */
244 };
245 
246 typedef struct Ctlr Ctlr;
247 typedef struct Ctlr {
248 	int	port;
249 	Pcidev*	pcidev;
250 	Ctlr*	next;
251 	int	active;
252 
253 	QLock	alock;			/* attach */
254 	Lock	ilock;			/* init */
255 	int	init;			/*  */
256 
257 	int	pciv;			/*  */
258 	int	macv;			/* MAC version */
259 	int	phyv;			/* PHY version */
260 
261 	Mii*	mii;
262 
263 	Lock	tlock;			/* transmit */
264 	D*	td;			/* descriptor ring */
265 	Block**	tb;			/* transmit buffers */
266 	int	ntd;
267 
268 	int	tdh;			/* head - producer index (host) */
269 	int	tdt;			/* tail - consumer index (NIC) */
270 	int	ntdfree;
271 	int	ntq;
272 
273 	int	mtps;			/* Max. Transmit Packet Size */
274 
275 	Lock	rlock;			/* receive */
276 	D*	rd;			/* descriptor ring */
277 	Block**	rb;			/* receive buffers */
278 	int	nrd;
279 
280 	int	rdh;			/* head - producer index (NIC) */
281 	int	rdt;			/* tail - consumer index (host) */
282 	int	nrdfree;
283 
284 	int	tcr;			/* transmit configuration register */
285 	int	rcr;			/* receive configuration register */
286 	int	imr;
287 
288 	QLock	slock;			/* statistics */
289 	Dtcc*	dtcc;
290 	uint	txdu;
291 	uint	tcpf;
292 	uint	udpf;
293 	uint	ipf;
294 	uint	fovf;
295 	uint	ierrs;
296 	uint	rer;
297 	uint	rdu;
298 	uint	punlc;
299 	uint	fovw;
300 } Ctlr;
301 
302 static Ctlr* rtl8169ctlrhead;
303 static Ctlr* rtl8169ctlrtail;
304 
305 #define csr8r(c, r)	(inb((c)->port+(r)))
306 #define csr16r(c, r)	(ins((c)->port+(r)))
307 #define csr32r(c, r)	(inl((c)->port+(r)))
308 #define csr8w(c, r, b)	(outb((c)->port+(r), (u8int)(b)))
309 #define csr16w(c, r, w)	(outs((c)->port+(r), (u16int)(w)))
310 #define csr32w(c, r, l)	(outl((c)->port+(r), (u32int)(l)))
311 
312 static int
313 rtl8169miimir(Mii* mii, int pa, int ra)
314 {
315 	uint r;
316 	int timeo;
317 	Ctlr *ctlr;
318 
319 	if(pa != 1)
320 		return -1;
321 	ctlr = mii->ctlr;
322 
323 	r = (ra<<16) & RegaddrMASK;
324 	csr32w(ctlr, Phyar, r);
325 	delay(1);
326 	for(timeo = 0; timeo < 2000; timeo++){
327 		if((r = csr32r(ctlr, Phyar)) & Flag)
328 			break;
329 		microdelay(100);
330 	}
331 	if(!(r & Flag))
332 		return -1;
333 
334 	return (r & DataMASK)>>DataSHIFT;
335 }
336 
337 static int
338 rtl8169miimiw(Mii* mii, int pa, int ra, int data)
339 {
340 	uint r;
341 	int timeo;
342 	Ctlr *ctlr;
343 
344 	if(pa != 1)
345 		return -1;
346 	ctlr = mii->ctlr;
347 
348 	r = Flag|((ra<<16) & RegaddrMASK)|((data<<DataSHIFT) & DataMASK);
349 	csr32w(ctlr, Phyar, r);
350 	delay(1);
351 	for(timeo = 0; timeo < 2000; timeo++){
352 		if(!((r = csr32r(ctlr, Phyar)) & Flag))
353 			break;
354 		microdelay(100);
355 	}
356 	if(r & Flag)
357 		return -1;
358 
359 	return 0;
360 }
361 
362 static int
363 rtl8169mii(Ctlr* ctlr)
364 {
365 	MiiPhy *phy;
366 
367 	/*
368 	 * Link management.
369 	 */
370 	if((ctlr->mii = malloc(sizeof(Mii))) == nil)
371 		return -1;
372 	ctlr->mii->mir = rtl8169miimir;
373 	ctlr->mii->miw = rtl8169miimiw;
374 	ctlr->mii->ctlr = ctlr;
375 
376 	/*
377 	 * Get rev number out of Phyidr2 so can config properly.
378 	 * There's probably more special stuff for Macv0[234] needed here.
379 	 */
380 	ctlr->phyv = rtl8169miimir(ctlr->mii, 1, Phyidr2) & 0x0F;
381 	if(ctlr->macv == Macv02){
382 		csr8w(ctlr, 0x82, 1);				/* magic */
383 		rtl8169miimiw(ctlr->mii, 1, 0x0B, 0x0000);	/* magic */
384 	}
385 
386 	if(mii(ctlr->mii, (1<<1)) == 0 || (phy = ctlr->mii->curphy) == nil){
387 		free(ctlr->mii);
388 		ctlr->mii = nil;
389 		return -1;
390 	}
391 	print("oui %#ux phyno %d, macv = %#8.8ux phyv = %#4.4ux\n",
392 		phy->oui, phy->phyno, ctlr->macv, ctlr->phyv);
393 
394 	miiane(ctlr->mii, ~0, ~0, ~0);
395 
396 	return 0;
397 }
398 
399 static void
400 rtl8169promiscuous(void* arg, int on)
401 {
402 	Ether *edev;
403 	Ctlr * ctlr;
404 
405 	edev = arg;
406 	ctlr = edev->ctlr;
407 	ilock(&ctlr->ilock);
408 
409 	if(on)
410 		ctlr->rcr |= Aap;
411 	else
412 		ctlr->rcr &= ~Aap;
413 	csr32w(ctlr, Rcr, ctlr->rcr);
414 	iunlock(&ctlr->ilock);
415 }
416 
417 static void
418 rtl8169multicast(void* arg, uchar*, int)
419 {
420 	rtl8169promiscuous(arg, 1);
421 }
422 
423 static long
424 rtl8169ifstat(Ether* edev, void* a, long n, ulong offset)
425 {
426 	char *p;
427 	Ctlr *ctlr;
428 	Dtcc *dtcc;
429 	int i, l, r, timeo;
430 
431 	ctlr = edev->ctlr;
432 	qlock(&ctlr->slock);
433 
434 	p = nil;
435 	if(waserror()){
436 		qunlock(&ctlr->slock);
437 		free(p);
438 		nexterror();
439 	}
440 
441 	csr32w(ctlr, Dtccr+4, 0);
442 	csr32w(ctlr, Dtccr, PCIWADDR(ctlr->dtcc)|Cmd);
443 	for(timeo = 0; timeo < 1000; timeo++){
444 		if(!(csr32r(ctlr, Dtccr) & Cmd))
445 			break;
446 		delay(1);
447 	}
448 	if(csr32r(ctlr, Dtccr) & Cmd)
449 		error(Eio);
450 	dtcc = ctlr->dtcc;
451 
452 	edev->oerrs = dtcc->txer;
453 	edev->crcs = dtcc->rxer;
454 	edev->frames = dtcc->fae;
455 	edev->buffs = dtcc->misspkt;
456 	edev->overflows = ctlr->txdu+ctlr->rdu;
457 
458 	if(n == 0){
459 		qunlock(&ctlr->slock);
460 		poperror();
461 		return 0;
462 	}
463 
464 	if((p = malloc(READSTR)) == nil)
465 		error(Enomem);
466 
467 	l = snprint(p, READSTR, "TxOk: %llud\n", dtcc->txok);
468 	l += snprint(p+l, READSTR-l, "RxOk: %llud\n", dtcc->rxok);
469 	l += snprint(p+l, READSTR-l, "TxEr: %llud\n", dtcc->txer);
470 	l += snprint(p+l, READSTR-l, "RxEr: %ud\n", dtcc->rxer);
471 	l += snprint(p+l, READSTR-l, "MissPkt: %ud\n", dtcc->misspkt);
472 	l += snprint(p+l, READSTR-l, "FAE: %ud\n", dtcc->fae);
473 	l += snprint(p+l, READSTR-l, "Tx1Col: %ud\n", dtcc->tx1col);
474 	l += snprint(p+l, READSTR-l, "TxMCol: %ud\n", dtcc->txmcol);
475 	l += snprint(p+l, READSTR-l, "RxOkPh: %llud\n", dtcc->rxokph);
476 	l += snprint(p+l, READSTR-l, "RxOkBrd: %llud\n", dtcc->rxokbrd);
477 	l += snprint(p+l, READSTR-l, "RxOkMu: %ud\n", dtcc->rxokmu);
478 	l += snprint(p+l, READSTR-l, "TxAbt: %ud\n", dtcc->txabt);
479 	l += snprint(p+l, READSTR-l, "TxUndrn: %ud\n", dtcc->txundrn);
480 
481 	l += snprint(p+l, READSTR-l, "txdu: %ud\n", ctlr->txdu);
482 	l += snprint(p+l, READSTR-l, "tcpf: %ud\n", ctlr->tcpf);
483 	l += snprint(p+l, READSTR-l, "udpf: %ud\n", ctlr->udpf);
484 	l += snprint(p+l, READSTR-l, "ipf: %ud\n", ctlr->ipf);
485 	l += snprint(p+l, READSTR-l, "fovf: %ud\n", ctlr->fovf);
486 	l += snprint(p+l, READSTR-l, "ierrs: %ud\n", ctlr->ierrs);
487 	l += snprint(p+l, READSTR-l, "rer: %ud\n", ctlr->rer);
488 	l += snprint(p+l, READSTR-l, "rdu: %ud\n", ctlr->rdu);
489 	l += snprint(p+l, READSTR-l, "punlc: %ud\n", ctlr->punlc);
490 	l += snprint(p+l, READSTR-l, "fovw: %ud\n", ctlr->fovw);
491 
492 	l += snprint(p+l, READSTR-l, "tcr: %#8.8ux\n", ctlr->tcr);
493 	l += snprint(p+l, READSTR-l, "rcr: %#8.8ux\n", ctlr->rcr);
494 
495 	if(ctlr->mii != nil && ctlr->mii->curphy != nil){
496 		l += snprint(p+l, READSTR, "phy:   ");
497 		for(i = 0; i < NMiiPhyr; i++){
498 			if(i && ((i & 0x07) == 0))
499 				l += snprint(p+l, READSTR-l, "\n       ");
500 			r = miimir(ctlr->mii, i);
501 			l += snprint(p+l, READSTR-l, " %4.4ux", r);
502 		}
503 		snprint(p+l, READSTR-l, "\n");
504 	}
505 
506 	n = readstr(offset, a, n, p);
507 
508 	qunlock(&ctlr->slock);
509 	poperror();
510 	free(p);
511 
512 	return n;
513 }
514 
515 static void
516 rtl8169halt(Ctlr* ctlr)
517 {
518 	csr8w(ctlr, Cr, 0);
519 	csr16w(ctlr, Imr, 0);
520 	csr16w(ctlr, Isr, ~0);
521 }
522 
523 static int
524 rtl8169reset(Ctlr* ctlr)
525 {
526 	u32int r;
527 	int timeo;
528 
529 	/*
530 	 * Soft reset the controller.
531 	 */
532 	csr8w(ctlr, Cr, Rst);
533 	for(r = timeo = 0; timeo < 1000; timeo++){
534 		r = csr8r(ctlr, Cr);
535 		if(!(r & Rst))
536 			break;
537 		delay(1);
538 	}
539 	rtl8169halt(ctlr);
540 
541 	if(r & Rst)
542 		return -1;
543 	return 0;
544 }
545 
546 static void
547 rtl8169replenish(Ctlr* ctlr)
548 {
549 	D *d;
550 	int rdt;
551 	Block *bp;
552 
553 	rdt = ctlr->rdt;
554 	while(NEXT(rdt, ctlr->nrd) != ctlr->rdh){
555 		d = &ctlr->rd[rdt];
556 		if(ctlr->rb[rdt] == nil){
557 			/*
558 			 * Simple allocation for now.
559 			 * This better be aligned on 8.
560 			 */
561 			bp = iallocb(Mps);
562 			if(bp == nil){
563 				iprint("no available buffers\n");
564 				break;
565 			}
566 			ctlr->rb[rdt] = bp;
567 			d->addrlo = PCIWADDR(bp->rp);
568 			d->addrhi = 0;
569 		}
570 		coherence();
571 		d->control |= Own|Mps;
572 		rdt = NEXT(rdt, ctlr->nrd);
573 		ctlr->nrdfree++;
574 	}
575 	ctlr->rdt = rdt;
576 }
577 
578 static int
579 rtl8169init(Ether* edev)
580 {
581 	int i;
582 	u32int r;
583 	Block *bp;
584 	Ctlr *ctlr;
585 	u8int cplusc;
586 
587 	ctlr = edev->ctlr;
588 	ilock(&ctlr->ilock);
589 
590 	rtl8169halt(ctlr);
591 
592 	/*
593 	 * MAC Address.
594 	 * Must put chip into config register write enable mode.
595 	 */
596 	csr8w(ctlr, Cr9346, Eem1|Eem0);
597 	r = (edev->ea[3]<<24)|(edev->ea[2]<<16)|(edev->ea[1]<<8)|edev->ea[0];
598 	csr32w(ctlr, Idr0, r);
599 	r = (edev->ea[5]<<8)|edev->ea[4];
600 	csr32w(ctlr, Idr0+4, r);
601 
602 	/*
603 	 * Transmitter.
604 	 */
605 	memset(ctlr->td, 0, sizeof(D)*ctlr->ntd);
606 	ctlr->tdh = ctlr->tdt = 0;
607 	ctlr->td[ctlr->ntd-1].control = Eor;
608 
609 	/*
610 	 * Receiver.
611 	 * Need to do something here about the multicast filter.
612 	 */
613 	memset(ctlr->rd, 0, sizeof(D)*ctlr->nrd);
614 	ctlr->nrdfree = ctlr->rdh = ctlr->rdt = 0;
615 	ctlr->rd[ctlr->nrd-1].control = Eor;
616 
617 	for(i = 0; i < ctlr->nrd; i++){
618 		if((bp = ctlr->rb[i]) != nil){
619 			ctlr->rb[i] = nil;
620 			freeb(bp);
621 		}
622 	}
623 	rtl8169replenish(ctlr);
624 	ctlr->rcr = Rxfthnone|Mrxdmaunlimited|Ab|Apm;
625 
626 	/*
627 	 * Mtps is in units of 128 except for the RTL8169
628 	 * where is is 32. If using jumbo frames should be
629 	 * set to 0x3F.
630 	 * Setting Mulrw in Cplusc disables the Tx/Rx DMA burst
631 	 * settings in Tcr/Rcr; the (1<<14) is magic.
632 	 */
633 	ctlr->mtps = HOWMANY(Mps, 128);
634 	cplusc = csr16r(ctlr, Cplusc) & ~(1<<14);
635 	cplusc |= /*Rxchksum|*/Mulrw;
636 	switch(ctlr->macv){
637 	default:
638 		return -1;
639 	case Macv01:
640 		ctlr->mtps = HOWMANY(Mps, 32);
641 		break;
642 	case Macv02:
643 	case Macv03:
644 		cplusc |= (1<<14);			/* magic */
645 		break;
646 	case Macv05:
647 		/*
648 		 * This is interpreted from clearly bogus code
649 		 * in the manufacturer-supplied driver, it could
650 		 * be wrong. Untested.
651 		 */
652 		r = csr8r(ctlr, Config2) & 0x07;
653 		if(r == 0x01)				/* 66MHz PCI */
654 			csr32w(ctlr, 0x7C, 0x0007FFFF);	/* magic */
655 		else
656 			csr32w(ctlr, 0x7C, 0x0007FF00);	/* magic */
657 		pciclrmwi(ctlr->pcidev);
658 		break;
659 	case Macv13:
660 		/*
661 		 * This is interpreted from clearly bogus code
662 		 * in the manufacturer-supplied driver, it could
663 		 * be wrong. Untested.
664 		 */
665 		pcicfgw8(ctlr->pcidev, 0x68, 0x00);	/* magic */
666 		pcicfgw8(ctlr->pcidev, 0x69, 0x08);	/* magic */
667 		break;
668 	case Macv04:
669 	case Macv11:
670 	case Macv12:
671 	case Macv14:
672 	case Macv15:
673 		break;
674 	}
675 
676 	/*
677 	 * Enable receiver/transmitter.
678 	 * Need to do this first or some of the settings below
679 	 * won't take.
680 	 */
681 	switch(ctlr->pciv){
682 	default:
683 		csr8w(ctlr, Cr, Te|Re);
684 		csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited);
685 		csr32w(ctlr, Rcr, ctlr->rcr);
686 	case Rtl8169sc:
687 	case Rtl8168b:
688 		break;
689 	}
690 
691 	/*
692 	 * Interrupts.
693 	 * Disable Tdu|Tok for now, the transmit routine will tidy.
694 	 * Tdu means the NIC ran out of descriptors to send, so it
695 	 * doesn't really need to ever be on.
696 	 */
697 	csr32w(ctlr, Timerint, 0);
698 	ctlr->imr = Serr|Timeout|Fovw|Punlc|Rdu|Ter|Rer|Rok;
699 	csr16w(ctlr, Imr, ctlr->imr);
700 
701 	/*
702 	 * Clear missed-packet counter;
703 	 * initial early transmit threshold value;
704 	 * set the descriptor ring base addresses;
705 	 * set the maximum receive packet size;
706 	 * no early-receive interrupts.
707 	 */
708 	csr32w(ctlr, Mpc, 0);
709 	csr8w(ctlr, Mtps, ctlr->mtps);
710 	csr32w(ctlr, Tnpds+4, 0);
711 	csr32w(ctlr, Tnpds, PCIWADDR(ctlr->td));
712 	csr32w(ctlr, Rdsar+4, 0);
713 	csr32w(ctlr, Rdsar, PCIWADDR(ctlr->rd));
714 	csr16w(ctlr, Rms, Mps);
715 	r = csr16r(ctlr, Mulint) & 0xF000;
716 	csr16w(ctlr, Mulint, r);
717 	csr16w(ctlr, Cplusc, cplusc);
718 
719 	/*
720 	 * Set configuration.
721 	 */
722 	switch(ctlr->pciv){
723 	default:
724 		break;
725 	case Rtl8169sc:
726 		csr16w(ctlr, 0xE2, 0);			/* magic */
727 		csr8w(ctlr, Cr, Te|Re);
728 		csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited);
729 		csr32w(ctlr, Rcr, ctlr->rcr);
730 		break;
731 	case Rtl8168b:
732 	case Rtl8169c:
733 		csr16w(ctlr, 0xE2, 0);			/* magic */
734 		csr16w(ctlr, Cplusc, 0x2000);		/* magic */
735 		csr8w(ctlr, Cr, Te|Re);
736 		csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited);
737 		csr32w(ctlr, Rcr, ctlr->rcr);
738 		csr16w(ctlr, Rms, 0x0800);
739 		csr8w(ctlr, Mtps, 0x3F);
740 		break;
741 	}
742 	ctlr->tcr = csr32r(ctlr, Tcr);
743 	csr8w(ctlr, Cr9346, 0);
744 
745 	iunlock(&ctlr->ilock);
746 
747 //	rtl8169mii(ctlr);
748 
749 	return 0;
750 }
751 
752 static void
753 rtl8169attach(Ether* edev)
754 {
755 	int timeo;
756 	Ctlr *ctlr;
757 
758 	ctlr = edev->ctlr;
759 	qlock(&ctlr->alock);
760 	if(ctlr->init == 0){
761 		/*
762 		 * Handle allocation/init errors here.
763 		 */
764 		ctlr->td = mallocalign(sizeof(D)*Ntd, 256, 0, 0);
765 		ctlr->tb = malloc(Ntd*sizeof(Block*));
766 		ctlr->ntd = Ntd;
767 		ctlr->rd = mallocalign(sizeof(D)*Nrd, 256, 0, 0);
768 		ctlr->rb = malloc(Nrd*sizeof(Block*));
769 		ctlr->nrd = Nrd;
770 		ctlr->dtcc = mallocalign(sizeof(Dtcc), 64, 0, 0);
771 		rtl8169init(edev);
772 		ctlr->init = 1;
773 	}
774 	qunlock(&ctlr->alock);
775 
776 	/*
777 	 * Wait for link to be ready.
778 	 */
779 	for(timeo = 0; timeo < 350; timeo++){
780 		if(miistatus(ctlr->mii) == 0)
781 			break;
782 		delay(100);		/* print fewer miistatus messages */
783 	}
784 }
785 
786 static void
787 rtl8169link(Ether* edev)
788 {
789 	uint r;
790 	int limit;
791 	Ctlr *ctlr;
792 
793 	ctlr = edev->ctlr;
794 
795 	/*
796 	 * Maybe the link changed - do we care very much?
797 	 * Could stall transmits if no link, maybe?
798 	 */
799 	if(!((r = csr8r(ctlr, Phystatus)) & Linksts)){
800 		edev->link = 0;
801 		return;
802 	}
803 	edev->link = 1;
804 
805 	limit = 256*1024;
806 	if(r & Speed10){
807 		edev->mbps = 10;
808 		limit = 65*1024;
809 	} else if(r & Speed100)
810 		edev->mbps = 100;
811 	else if(r & Speed1000)
812 		edev->mbps = 1000;
813 
814 	if(edev->oq != nil)
815 		qsetlimit(edev->oq, limit);
816 }
817 
818 static void
819 rtl8169transmit(Ether* edev)
820 {
821 	D *d;
822 	Block *bp;
823 	Ctlr *ctlr;
824 	int control, x;
825 
826 	ctlr = edev->ctlr;
827 
828 	ilock(&ctlr->tlock);
829 	for(x = ctlr->tdh; ctlr->ntq > 0; x = NEXT(x, ctlr->ntd)){
830 		d = &ctlr->td[x];
831 		if((control = d->control) & Own)
832 			break;
833 
834 		/*
835 		 * Check errors and log here.
836 		 */
837 		USED(control);
838 
839 		/*
840 		 * Free it up.
841 		 * Need to clean the descriptor here? Not really.
842 		 * Simple freeb for now (no chain and freeblist).
843 		 * Use ntq count for now.
844 		 */
845 		freeb(ctlr->tb[x]);
846 		ctlr->tb[x] = nil;
847 		d->control &= Eor;
848 
849 		ctlr->ntq--;
850 	}
851 	ctlr->tdh = x;
852 
853 	x = ctlr->tdt;
854 	while(ctlr->ntq < (ctlr->ntd-1)){
855 		if((bp = qget(edev->oq)) == nil)
856 			break;
857 
858 		d = &ctlr->td[x];
859 		d->addrlo = PCIWADDR(bp->rp);
860 		d->addrhi = 0;
861 		ctlr->tb[x] = bp;
862 		coherence();
863 		d->control |= Own|Fs|Ls|((BLEN(bp)<<TxflSHIFT) & TxflMASK);
864 
865 		x = NEXT(x, ctlr->ntd);
866 		ctlr->ntq++;
867 	}
868 	if(x != ctlr->tdt){
869 		ctlr->tdt = x;
870 		csr8w(ctlr, Tppoll, Npq);
871 	}
872 	else if(ctlr->ntq >= (ctlr->ntd-1))
873 		ctlr->txdu++;
874 
875 	iunlock(&ctlr->tlock);
876 }
877 
878 static void
879 rtl8169receive(Ether* edev)
880 {
881 	D *d;
882 	int rdh;
883 	Block *bp;
884 	Ctlr *ctlr;
885 	u32int control;
886 
887 	ctlr = edev->ctlr;
888 
889 	rdh = ctlr->rdh;
890 	for(;;){
891 		d = &ctlr->rd[rdh];
892 
893 		if(d->control & Own)
894 			break;
895 
896 		control = d->control;
897 		if((control & (Fs|Ls|Res)) == (Fs|Ls)){
898 			bp = ctlr->rb[rdh];
899 			ctlr->rb[rdh] = nil;
900 			bp->wp = bp->rp + ((control & RxflMASK)>>RxflSHIFT)-4;
901 			bp->next = nil;
902 
903 			if(control & Fovf)
904 				ctlr->fovf++;
905 
906 			switch(control & (Pid1|Pid0)){
907 			default:
908 				break;
909 			case Pid0:
910 				if(control & Tcpf){
911 					ctlr->tcpf++;
912 					break;
913 				}
914 				bp->flag |= Btcpck;
915 				break;
916 			case Pid1:
917 				if(control & Udpf){
918 					ctlr->udpf++;
919 					break;
920 				}
921 				bp->flag |= Budpck;
922 				break;
923 			case Pid1|Pid0:
924 				if(control & Ipf){
925 					ctlr->ipf++;
926 					break;
927 				}
928 				bp->flag |= Bipck;
929 				break;
930 			}
931 			etheriq(edev, bp, 1);
932 		}
933 		else{
934 			/*
935 			 * Error stuff here.
936 			print("control %#8.8ux\n", control);
937 			 */
938 		}
939 		d->control &= Eor;
940 		ctlr->nrdfree--;
941 		rdh = NEXT(rdh, ctlr->nrd);
942 
943 		if(ctlr->nrdfree < ctlr->nrd/2)
944 			rtl8169replenish(ctlr);
945 	}
946 	ctlr->rdh = rdh;
947 }
948 
949 static void
950 rtl8169interrupt(Ureg*, void* arg)
951 {
952 	Ctlr *ctlr;
953 	Ether *edev;
954 	u32int isr;
955 
956 	edev = arg;
957 	ctlr = edev->ctlr;
958 
959 	while((isr = csr16r(ctlr, Isr)) != 0 && isr != 0xFFFF){
960 		csr16w(ctlr, Isr, isr);
961 		if((isr & ctlr->imr) == 0)
962 			break;
963 		if(isr & (Fovw|Punlc|Rdu|Rer|Rok)){
964 			rtl8169receive(edev);
965 			if(!(isr & (Punlc|Rok)))
966 				ctlr->ierrs++;
967 			if(isr & Rer)
968 				ctlr->rer++;
969 			if(isr & Rdu)
970 				ctlr->rdu++;
971 			if(isr & Punlc)
972 				ctlr->punlc++;
973 			if(isr & Fovw)
974 				ctlr->fovw++;
975 			isr &= ~(Fovw|Rdu|Rer|Rok);
976 		}
977 
978 		if(isr & (Tdu|Ter|Tok)){
979 			rtl8169transmit(edev);
980 			isr &= ~(Tdu|Ter|Tok);
981 		}
982 
983 		if(isr & Punlc){
984 			rtl8169link(edev);
985 			isr &= ~Punlc;
986 		}
987 
988 		/*
989 		 * Some of the reserved bits get set sometimes...
990 		 */
991 		if(isr & (Serr|Timeout|Tdu|Fovw|Punlc|Rdu|Ter|Tok|Rer|Rok))
992 			panic("rtl8169interrupt: imr %#4.4ux isr %#4.4ux\n",
993 				csr16r(ctlr, Imr), isr);
994 	}
995 }
996 
997 static void
998 rtl8169pci(void)
999 {
1000 	Pcidev *p;
1001 	Ctlr *ctlr;
1002 	int i, port;
1003 
1004 	p = nil;
1005 	while(p = pcimatch(p, 0, 0)){
1006 		if(p->ccrb != 0x02 || p->ccru != 0)
1007 			continue;
1008 
1009 		switch(i = ((p->did<<16)|p->vid)){
1010 		default:
1011 			continue;
1012 		case Rtl8100e:			/* RTL810[01]E ? */
1013 		case Rtl8169c:			/* RTL8169C */
1014 		case Rtl8169sc:			/* RTL8169SC */
1015 		case Rtl8168b:			/* RTL8168B */
1016 		case Rtl8169:			/* RTL8169 */
1017 			break;
1018 		case (0xC107<<16)|0x1259:	/* Corega CG-LAPCIGT */
1019 			i = Rtl8169;
1020 			break;
1021 		}
1022 
1023 		port = p->mem[0].bar & ~0x01;
1024 		if(ioalloc(port, p->mem[0].size, 0, "rtl8169") < 0){
1025 			print("rtl8169: port %#ux in use\n", port);
1026 			continue;
1027 		}
1028 
1029 		ctlr = malloc(sizeof(Ctlr));
1030 		ctlr->port = port;
1031 		ctlr->pcidev = p;
1032 		ctlr->pciv = i;
1033 
1034 		if(pcigetpms(p) > 0){
1035 			pcisetpms(p, 0);
1036 
1037 			for(i = 0; i < 6; i++)
1038 				pcicfgw32(p, PciBAR0+i*4, p->mem[i].bar);
1039 			pcicfgw8(p, PciINTL, p->intl);
1040 			pcicfgw8(p, PciLTR, p->ltr);
1041 			pcicfgw8(p, PciCLS, p->cls);
1042 			pcicfgw16(p, PciPCR, p->pcr);
1043 		}
1044 
1045 		if(rtl8169reset(ctlr)){
1046 			iofree(port);
1047 			free(ctlr);
1048 			continue;
1049 		}
1050 
1051 		/*
1052 		 * Extract the chip hardware version,
1053 		 * needed to configure each properly.
1054 		 */
1055 		ctlr->macv = csr32r(ctlr, Tcr) & HwveridMASK;
1056 
1057 		rtl8169mii(ctlr);
1058 
1059 		pcisetbme(p);
1060 
1061 		if(rtl8169ctlrhead != nil)
1062 			rtl8169ctlrtail->next = ctlr;
1063 		else
1064 			rtl8169ctlrhead = ctlr;
1065 		rtl8169ctlrtail = ctlr;
1066 	}
1067 }
1068 
1069 static int
1070 rtl8169pnp(Ether* edev)
1071 {
1072 	u32int r;
1073 	Ctlr *ctlr;
1074 	uchar ea[Eaddrlen];
1075 
1076 	if(rtl8169ctlrhead == nil)
1077 		rtl8169pci();
1078 
1079 	/*
1080 	 * Any adapter matches if no edev->port is supplied,
1081 	 * otherwise the ports must match.
1082 	 */
1083 	for(ctlr = rtl8169ctlrhead; ctlr != nil; ctlr = ctlr->next){
1084 		if(ctlr->active)
1085 			continue;
1086 		if(edev->port == 0 || edev->port == ctlr->port){
1087 			ctlr->active = 1;
1088 			break;
1089 		}
1090 	}
1091 	if(ctlr == nil)
1092 		return -1;
1093 
1094 	edev->ctlr = ctlr;
1095 	edev->port = ctlr->port;
1096 	edev->irq = ctlr->pcidev->intl;
1097 	edev->tbdf = ctlr->pcidev->tbdf;
1098 	edev->mbps = 100;
1099 
1100 	/*
1101 	 * Check if the adapter's station address is to be overridden.
1102 	 * If not, read it from the device and set in edev->ea.
1103 	 */
1104 	memset(ea, 0, Eaddrlen);
1105 	if(memcmp(ea, edev->ea, Eaddrlen) == 0){
1106 		r = csr32r(ctlr, Idr0);
1107 		edev->ea[0] = r;
1108 		edev->ea[1] = r>>8;
1109 		edev->ea[2] = r>>16;
1110 		edev->ea[3] = r>>24;
1111 		r = csr32r(ctlr, Idr0+4);
1112 		edev->ea[4] = r;
1113 		edev->ea[5] = r>>8;
1114 	}
1115 
1116 	edev->attach = rtl8169attach;
1117 	edev->transmit = rtl8169transmit;
1118 	edev->interrupt = rtl8169interrupt;
1119 	edev->ifstat = rtl8169ifstat;
1120 
1121 	edev->arg = edev;
1122 	edev->promiscuous = rtl8169promiscuous;
1123 	edev->multicast = rtl8169multicast;
1124 //	edev->shutdown = rtl8169shutdown;
1125 
1126 	rtl8169link(edev);
1127 
1128 	return 0;
1129 }
1130 
1131 void
1132 ether8169link(void)
1133 {
1134 	addethercard("rtl8169", rtl8169pnp);
1135 }
1136