1 /*
2 * Realtek RTL8110S/8169S Gigabit Ethernet Controllers.
3 * Mostly there. There are some magic register values used
4 * which are not described in any datasheet or driver but seem
5 * to be necessary.
6 * No tuning has been done. Only tested on an RTL8110S, there
7 * are slight differences between the chips in the series so some
8 * tweaks may be needed.
9 */
10 #include "u.h"
11 #include "../port/lib.h"
12 #include "mem.h"
13 #include "dat.h"
14 #include "fns.h"
15 #include "io.h"
16 #include "../port/error.h"
17 #include "../port/netif.h"
18
19 #include "etherif.h"
20 #include "ethermii.h"
21
22 enum { /* registers */
23 Idr0 = 0x00, /* MAC address */
24 Mar0 = 0x08, /* Multicast address */
25 Dtccr = 0x10, /* Dump Tally Counter Command */
26 Tnpds = 0x20, /* Transmit Normal Priority Descriptors */
27 Thpds = 0x28, /* Transmit High Priority Descriptors */
28 Flash = 0x30, /* Flash Memory Read/Write */
29 Erbcr = 0x34, /* Early Receive Byte Count */
30 Ersr = 0x36, /* Early Receive Status */
31 Cr = 0x37, /* Command Register */
32 Tppoll = 0x38, /* Transmit Priority Polling */
33 Imr = 0x3C, /* Interrupt Mask */
34 Isr = 0x3E, /* Interrupt Status */
35 Tcr = 0x40, /* Transmit Configuration */
36 Rcr = 0x44, /* Receive Configuration */
37 Tctr = 0x48, /* Timer Count */
38 Mpc = 0x4C, /* Missed Packet Counter */
39 Cr9346 = 0x50, /* 9346 Command Register */
40 Config0 = 0x51, /* Configuration Register 0 */
41 Config1 = 0x52, /* Configuration Register 1 */
42 Config2 = 0x53, /* Configuration Register 2 */
43 Config3 = 0x54, /* Configuration Register 3 */
44 Config4 = 0x55, /* Configuration Register 4 */
45 Config5 = 0x56, /* Configuration Register 5 */
46 Timerint = 0x58, /* Timer Interrupt */
47 Mulint = 0x5C, /* Multiple Interrupt Select */
48 Phyar = 0x60, /* PHY Access */
49 Tbicsr0 = 0x64, /* TBI Control and Status */
50 Tbianar = 0x68, /* TBI Auto-Negotiation Advertisment */
51 Tbilpar = 0x6A, /* TBI Auto-Negotiation Link Partner */
52 Phystatus = 0x6C, /* PHY Status */
53
54 Rms = 0xDA, /* Receive Packet Maximum Size */
55 Cplusc = 0xE0, /* C+ Command */
56 Coal = 0xE2, /* Interrupt Mitigation (Coalesce) */
57 Rdsar = 0xE4, /* Receive Descriptor Start Address */
58 Etx = 0xEC, /* Early Transmit Threshold */
59 };
60
61 enum { /* Dtccr */
62 Cmd = 0x00000008, /* Command */
63 };
64
65 enum { /* Cr */
66 Te = 0x04, /* Transmitter Enable */
67 Re = 0x08, /* Receiver Enable */
68 Rst = 0x10, /* Software Reset */
69 };
70
71 enum { /* Tppoll */
72 Fswint = 0x01, /* Forced Software Interrupt */
73 Npq = 0x40, /* Normal Priority Queue polling */
74 Hpq = 0x80, /* High Priority Queue polling */
75 };
76
77 enum { /* Imr/Isr */
78 Rok = 0x0001, /* Receive OK */
79 Rer = 0x0002, /* Receive Error */
80 Tok = 0x0004, /* Transmit OK */
81 Ter = 0x0008, /* Transmit Error */
82 Rdu = 0x0010, /* Receive Descriptor Unavailable */
83 Punlc = 0x0020, /* Packet Underrun or Link Change */
84 Fovw = 0x0040, /* Receive FIFO Overflow */
85 Tdu = 0x0080, /* Transmit Descriptor Unavailable */
86 Swint = 0x0100, /* Software Interrupt */
87 Timeout = 0x4000, /* Timer */
88 Serr = 0x8000, /* System Error */
89 };
90
91 enum { /* Tcr */
92 MtxdmaSHIFT = 8, /* Max. DMA Burst Size */
93 MtxdmaMASK = 0x00000700,
94 Mtxdmaunlimited = 0x00000700,
95 Acrc = 0x00010000, /* Append CRC (not) */
96 Lbk0 = 0x00020000, /* Loopback Test 0 */
97 Lbk1 = 0x00040000, /* Loopback Test 1 */
98 Ifg2 = 0x00080000, /* Interframe Gap 2 */
99 HwveridSHIFT = 23, /* Hardware Version ID */
100 HwveridMASK = 0x7C800000,
101 Macv01 = 0x00000000, /* RTL8169 */
102 Macv02 = 0x00800000, /* RTL8169S/8110S */
103 Macv03 = 0x04000000, /* RTL8169S/8110S */
104 Macv04 = 0x10000000, /* RTL8169SB/8110SB */
105 Macv05 = 0x18000000, /* RTL8169SC/8110SC */
106 Macv07 = 0x24800000, /* RTL8102e */
107 Macv07a = 0x34800000, /* RTL8102e */
108 Macv11 = 0x30000000, /* RTL8168B/8111B */
109 Macv12 = 0x38000000, /* RTL8169B/8111B */
110 Macv12a = 0x3c000000, /* RTL8169C/8111C */
111 Macv13 = 0x34000000, /* RTL8101E */
112 Macv14 = 0x30800000, /* RTL8100E */
113 Macv15 = 0x38800000, /* RTL8100E */
114 // Macv19 = 0x3c000000, /* dup Macv12a: RTL8111c-gr */
115 Macv25 = 0x28000000, /* RTL8168D */
116 Macv2c = 0x2c000000, /* RTL8168E */
117 Macv34 = 0x2c800000, /* RTL8168E */
118 Ifg0 = 0x01000000, /* Interframe Gap 0 */
119 Ifg1 = 0x02000000, /* Interframe Gap 1 */
120 };
121
122 enum { /* Rcr */
123 Aap = 0x00000001, /* Accept All Packets */
124 Apm = 0x00000002, /* Accept Physical Match */
125 Am = 0x00000004, /* Accept Multicast */
126 Ab = 0x00000008, /* Accept Broadcast */
127 Ar = 0x00000010, /* Accept Runt */
128 Aer = 0x00000020, /* Accept Error */
129 Sel9356 = 0x00000040, /* 9356 EEPROM used */
130 MrxdmaSHIFT = 8, /* Max. DMA Burst Size */
131 MrxdmaMASK = 0x00000700,
132 Mrxdmaunlimited = 0x00000700,
133 RxfthSHIFT = 13, /* Receive Buffer Length */
134 RxfthMASK = 0x0000E000,
135 Rxfth256 = 0x00008000,
136 Rxfthnone = 0x0000E000,
137 Rer8 = 0x00010000, /* Accept Error Packets > 8 bytes */
138 MulERINT = 0x01000000, /* Multiple Early Interrupt Select */
139 };
140
141 enum { /* Cr9346 */
142 Eedo = 0x01, /* */
143 Eedi = 0x02, /* */
144 Eesk = 0x04, /* */
145 Eecs = 0x08, /* */
146 Eem0 = 0x40, /* Operating Mode */
147 Eem1 = 0x80,
148 };
149
150 enum { /* Phyar */
151 DataMASK = 0x0000FFFF, /* 16-bit GMII/MII Register Data */
152 DataSHIFT = 0,
153 RegaddrMASK = 0x001F0000, /* 5-bit GMII/MII Register Address */
154 RegaddrSHIFT = 16,
155 Flag = 0x80000000, /* */
156 };
157
158 enum { /* Phystatus */
159 Fd = 0x01, /* Full Duplex */
160 Linksts = 0x02, /* Link Status */
161 Speed10 = 0x04, /* */
162 Speed100 = 0x08, /* */
163 Speed1000 = 0x10, /* */
164 Rxflow = 0x20, /* */
165 Txflow = 0x40, /* */
166 Entbi = 0x80, /* */
167 };
168
169 enum { /* Cplusc */
170 Mulrw = 0x0008, /* PCI Multiple R/W Enable */
171 Dac = 0x0010, /* PCI Dual Address Cycle Enable */
172 Rxchksum = 0x0020, /* Receive Checksum Offload Enable */
173 Rxvlan = 0x0040, /* Receive VLAN De-tagging Enable */
174 Endian = 0x0200, /* Endian Mode */
175 };
176
177 typedef struct D D; /* Transmit/Receive Descriptor */
178 struct D {
179 u32int control;
180 u32int vlan;
181 u32int addrlo;
182 u32int addrhi;
183 };
184
185 enum { /* Transmit Descriptor control */
186 TxflMASK = 0x0000FFFF, /* Transmit Frame Length */
187 TxflSHIFT = 0,
188 Tcps = 0x00010000, /* TCP Checksum Offload */
189 Udpcs = 0x00020000, /* UDP Checksum Offload */
190 Ipcs = 0x00040000, /* IP Checksum Offload */
191 Lgsen = 0x08000000, /* TSO; WARNING: contains lark's vomit */
192 };
193
194 enum { /* Receive Descriptor control */
195 RxflMASK = 0x00001FFF, /* Receive Frame Length */
196 Tcpf = 0x00004000, /* TCP Checksum Failure */
197 Udpf = 0x00008000, /* UDP Checksum Failure */
198 Ipf = 0x00010000, /* IP Checksum Failure */
199 Pid0 = 0x00020000, /* Protocol ID0 */
200 Pid1 = 0x00040000, /* Protocol ID1 */
201 Crce = 0x00080000, /* CRC Error */
202 Runt = 0x00100000, /* Runt Packet */
203 Res = 0x00200000, /* Receive Error Summary */
204 Rwt = 0x00400000, /* Receive Watchdog Timer Expired */
205 Fovf = 0x00800000, /* FIFO Overflow */
206 Bovf = 0x01000000, /* Buffer Overflow */
207 Bar = 0x02000000, /* Broadcast Address Received */
208 Pam = 0x04000000, /* Physical Address Matched */
209 Mar = 0x08000000, /* Multicast Address Received */
210 };
211
212 enum { /* General Descriptor control */
213 Ls = 0x10000000, /* Last Segment Descriptor */
214 Fs = 0x20000000, /* First Segment Descriptor */
215 Eor = 0x40000000, /* End of Descriptor Ring */
216 Own = 0x80000000, /* Ownership */
217 };
218
219 /*
220 */
221 enum { /* Ring sizes (<= 1024) */
222 /* were 1024 & 64, but 253 and 9 are ample. */
223 Nrd = 256, /* Receive Ring */
224 Ntd = 32, /* Transmit Ring */
225
226 Mtu = ETHERMAXTU,
227 Mps = ROUNDUP(ETHERMAXTU+4, 128),
228 // Mps = Mtu + 8 + 14, /* if(mtu>ETHERMAXTU) */
229 };
230
231 typedef struct Dtcc Dtcc;
232 struct Dtcc {
233 u64int txok;
234 u64int rxok;
235 u64int txer;
236 u32int rxer;
237 u16int misspkt;
238 u16int fae;
239 u32int tx1col;
240 u32int txmcol;
241 u64int rxokph;
242 u64int rxokbrd;
243 u32int rxokmu;
244 u16int txabt;
245 u16int txundrn;
246 };
247
248 enum { /* Variants */
249 Rtl8100e = (0x8136<<16)|0x10EC, /* RTL810[01]E: pci -e */
250 Rtl8169c = (0x0116<<16)|0x16EC, /* RTL8169C+ (USR997902) */
251 Rtl8169sc = (0x8167<<16)|0x10EC, /* RTL8169SC */
252 Rtl8168b = (0x8168<<16)|0x10EC, /* RTL8168B: pci-e */
253 Rtl8169 = (0x8169<<16)|0x10EC, /* RTL8169 */
254 };
255
256 typedef struct Ctlr Ctlr;
257 typedef struct Ctlr {
258 int port;
259 Pcidev* pcidev;
260 Ctlr* next;
261 int active;
262
263 QLock alock; /* attach */
264 Lock ilock; /* init */
265 int init; /* */
266
267 int pciv; /* */
268 int macv; /* MAC version */
269 int phyv; /* PHY version */
270 int pcie; /* flag: pci-express device? */
271
272 uvlong mchash; /* multicast hash */
273
274 Mii* mii;
275
276 Lock tlock; /* transmit */
277 D* td; /* descriptor ring */
278 Block** tb; /* transmit buffers */
279 int ntd;
280
281 int tdh; /* head - producer index (host) */
282 int tdt; /* tail - consumer index (NIC) */
283 int ntdfree;
284 int ntq;
285
286 // int rbsz; /* receive buffer size */
287
288 Lock rlock; /* receive */
289 D* rd; /* descriptor ring */
290 Block** rb; /* receive buffers */
291 int nrd;
292
293 int rdh; /* head - producer index (NIC) */
294 int rdt; /* tail - consumer index (host) */
295 int nrdfree;
296
297 int tcr; /* transmit configuration register */
298 int rcr; /* receive configuration register */
299 int imr;
300
301 // Watermark wmrb;
302 Watermark wmrd;
303 Watermark wmtd;
304
305 QLock slock; /* statistics */
306 Dtcc* dtcc;
307 uint txdu;
308 uint tcpf;
309 uint udpf;
310 uint ipf;
311 uint fovf;
312 uint ierrs;
313 uint rer;
314 uint rdu;
315 uint punlc;
316 uint fovw;
317 uint mcast;
318 uint frag; /* partial packets; rb was too small */
319 } Ctlr;
320
321 static Ctlr* rtl8169ctlrhead;
322 static Ctlr* rtl8169ctlrtail;
323
324 #define csr8r(c, r) (inb((c)->port+(r)))
325 #define csr16r(c, r) (ins((c)->port+(r)))
326 #define csr32r(c, r) (inl((c)->port+(r)))
327 #define csr8w(c, r, b) (outb((c)->port+(r), (u8int)(b)))
328 #define csr16w(c, r, w) (outs((c)->port+(r), (u16int)(w)))
329 #define csr32w(c, r, l) (outl((c)->port+(r), (u32int)(l)))
330
331 static int
rtl8169miimir(Mii * mii,int pa,int ra)332 rtl8169miimir(Mii* mii, int pa, int ra)
333 {
334 uint r;
335 int timeo;
336 Ctlr *ctlr;
337
338 if(pa != 1)
339 return -1;
340 ctlr = mii->ctlr;
341
342 r = (ra<<16) & RegaddrMASK;
343 csr32w(ctlr, Phyar, r);
344 delay(1);
345 for(timeo = 0; timeo < 2000; timeo++){
346 if((r = csr32r(ctlr, Phyar)) & Flag)
347 break;
348 microdelay(100);
349 }
350 if(!(r & Flag))
351 return -1;
352
353 return (r & DataMASK)>>DataSHIFT;
354 }
355
356 static int
rtl8169miimiw(Mii * mii,int pa,int ra,int data)357 rtl8169miimiw(Mii* mii, int pa, int ra, int data)
358 {
359 uint r;
360 int timeo;
361 Ctlr *ctlr;
362
363 if(pa != 1)
364 return -1;
365 ctlr = mii->ctlr;
366
367 r = Flag|((ra<<16) & RegaddrMASK)|((data<<DataSHIFT) & DataMASK);
368 csr32w(ctlr, Phyar, r);
369 delay(1);
370 for(timeo = 0; timeo < 2000; timeo++){
371 if(!((r = csr32r(ctlr, Phyar)) & Flag))
372 break;
373 microdelay(100);
374 }
375 if(r & Flag)
376 return -1;
377
378 return 0;
379 }
380
381 static int
rtl8169mii(Ctlr * ctlr)382 rtl8169mii(Ctlr* ctlr)
383 {
384 MiiPhy *phy;
385
386 /*
387 * Link management.
388 */
389 if((ctlr->mii = malloc(sizeof(Mii))) == nil)
390 return -1;
391 ctlr->mii->mir = rtl8169miimir;
392 ctlr->mii->miw = rtl8169miimiw;
393 ctlr->mii->ctlr = ctlr;
394
395 /*
396 * Get rev number out of Phyidr2 so can config properly.
397 * There's probably more special stuff for Macv0[234] needed here.
398 */
399 ctlr->phyv = rtl8169miimir(ctlr->mii, 1, Phyidr2) & 0x0F;
400 if(ctlr->macv == Macv02){
401 csr8w(ctlr, 0x82, 1); /* magic */
402 rtl8169miimiw(ctlr->mii, 1, 0x0B, 0x0000); /* magic */
403 }
404
405 if(mii(ctlr->mii, (1<<1)) == 0 || (phy = ctlr->mii->curphy) == nil){
406 free(ctlr->mii);
407 ctlr->mii = nil;
408 return -1;
409 }
410 print("oui %#ux phyno %d, macv = %#8.8ux phyv = %#4.4ux\n",
411 phy->oui, phy->phyno, ctlr->macv, ctlr->phyv);
412
413 miiane(ctlr->mii, ~0, ~0, ~0);
414
415 return 0;
416 }
417
418 static void
rtl8169promiscuous(void * arg,int on)419 rtl8169promiscuous(void* arg, int on)
420 {
421 Ether *edev;
422 Ctlr * ctlr;
423
424 edev = arg;
425 ctlr = edev->ctlr;
426 ilock(&ctlr->ilock);
427
428 if(on)
429 ctlr->rcr |= Aap;
430 else
431 ctlr->rcr &= ~Aap;
432 csr32w(ctlr, Rcr, ctlr->rcr);
433 iunlock(&ctlr->ilock);
434 }
435
436 enum {
437 /* everyone else uses 0x04c11db7, but they both produce the same crc */
438 Etherpolybe = 0x04c11db6,
439 Bytemask = (1<<8) - 1,
440 };
441
442 static ulong
ethercrcbe(uchar * addr,long len)443 ethercrcbe(uchar *addr, long len)
444 {
445 int i, j;
446 ulong c, crc, carry;
447
448 crc = ~0UL;
449 for (i = 0; i < len; i++) {
450 c = addr[i];
451 for (j = 0; j < 8; j++) {
452 carry = ((crc & (1UL << 31))? 1: 0) ^ (c & 1);
453 crc <<= 1;
454 c >>= 1;
455 if (carry)
456 crc = (crc ^ Etherpolybe) | carry;
457 }
458 }
459 return crc;
460 }
461
462 static ulong
swabl(ulong l)463 swabl(ulong l)
464 {
465 return l>>24 | (l>>8) & (Bytemask<<8) |
466 (l<<8) & (Bytemask<<16) | l<<24;
467 }
468
469 static void
rtl8169multicast(void * ether,uchar * eaddr,int add)470 rtl8169multicast(void* ether, uchar *eaddr, int add)
471 {
472 Ether *edev;
473 Ctlr *ctlr;
474
475 if (!add)
476 return; /* ok to keep receiving on old mcast addrs */
477
478 edev = ether;
479 ctlr = edev->ctlr;
480 ilock(&ctlr->ilock);
481
482 ctlr->mchash |= 1ULL << (ethercrcbe(eaddr, Eaddrlen) >> 26);
483
484 ctlr->rcr |= Am;
485 csr32w(ctlr, Rcr, ctlr->rcr);
486
487 /* pci-e variants reverse the order of the hash byte registers */
488 if (ctlr->pcie) {
489 csr32w(ctlr, Mar0, swabl(ctlr->mchash>>32));
490 csr32w(ctlr, Mar0+4, swabl(ctlr->mchash));
491 } else {
492 csr32w(ctlr, Mar0, ctlr->mchash);
493 csr32w(ctlr, Mar0+4, ctlr->mchash>>32);
494 }
495
496 iunlock(&ctlr->ilock);
497 }
498
499 static long
rtl8169ifstat(Ether * edev,void * a,long n,ulong offset)500 rtl8169ifstat(Ether* edev, void* a, long n, ulong offset)
501 {
502 char *p, *s, *e;
503 Ctlr *ctlr;
504 Dtcc *dtcc;
505 int i, l, r, timeo;
506
507 ctlr = edev->ctlr;
508 qlock(&ctlr->slock);
509
510 p = nil;
511 if(waserror()){
512 qunlock(&ctlr->slock);
513 free(p);
514 nexterror();
515 }
516
517 dtcc = ctlr->dtcc;
518 assert(dtcc);
519 csr32w(ctlr, Dtccr+4, 0);
520 csr32w(ctlr, Dtccr, PCIWADDR(dtcc)|Cmd);
521 for(timeo = 0; timeo < 1000; timeo++){
522 if(!(csr32r(ctlr, Dtccr) & Cmd))
523 break;
524 delay(1);
525 }
526 if(csr32r(ctlr, Dtccr) & Cmd)
527 error(Eio);
528
529 edev->oerrs = dtcc->txer;
530 edev->crcs = dtcc->rxer;
531 edev->frames = dtcc->fae;
532 edev->buffs = dtcc->misspkt;
533 edev->overflows = ctlr->txdu+ctlr->rdu;
534
535 if(n == 0){
536 qunlock(&ctlr->slock);
537 poperror();
538 return 0;
539 }
540
541 if((p = malloc(READSTR)) == nil)
542 error(Enomem);
543 e = p + READSTR;
544
545 l = snprint(p, READSTR, "TxOk: %llud\n", dtcc->txok);
546 l += snprint(p+l, READSTR-l, "RxOk: %llud\n", dtcc->rxok);
547 l += snprint(p+l, READSTR-l, "TxEr: %llud\n", dtcc->txer);
548 l += snprint(p+l, READSTR-l, "RxEr: %ud\n", dtcc->rxer);
549 l += snprint(p+l, READSTR-l, "MissPkt: %ud\n", dtcc->misspkt);
550 l += snprint(p+l, READSTR-l, "FAE: %ud\n", dtcc->fae);
551 l += snprint(p+l, READSTR-l, "Tx1Col: %ud\n", dtcc->tx1col);
552 l += snprint(p+l, READSTR-l, "TxMCol: %ud\n", dtcc->txmcol);
553 l += snprint(p+l, READSTR-l, "RxOkPh: %llud\n", dtcc->rxokph);
554 l += snprint(p+l, READSTR-l, "RxOkBrd: %llud\n", dtcc->rxokbrd);
555 l += snprint(p+l, READSTR-l, "RxOkMu: %ud\n", dtcc->rxokmu);
556 l += snprint(p+l, READSTR-l, "TxAbt: %ud\n", dtcc->txabt);
557 l += snprint(p+l, READSTR-l, "TxUndrn: %ud\n", dtcc->txundrn);
558
559 l += snprint(p+l, READSTR-l, "txdu: %ud\n", ctlr->txdu);
560 l += snprint(p+l, READSTR-l, "tcpf: %ud\n", ctlr->tcpf);
561 l += snprint(p+l, READSTR-l, "udpf: %ud\n", ctlr->udpf);
562 l += snprint(p+l, READSTR-l, "ipf: %ud\n", ctlr->ipf);
563 l += snprint(p+l, READSTR-l, "fovf: %ud\n", ctlr->fovf);
564 l += snprint(p+l, READSTR-l, "ierrs: %ud\n", ctlr->ierrs);
565 l += snprint(p+l, READSTR-l, "rer: %ud\n", ctlr->rer);
566 l += snprint(p+l, READSTR-l, "rdu: %ud\n", ctlr->rdu);
567 l += snprint(p+l, READSTR-l, "punlc: %ud\n", ctlr->punlc);
568 l += snprint(p+l, READSTR-l, "fovw: %ud\n", ctlr->fovw);
569
570 l += snprint(p+l, READSTR-l, "tcr: %#8.8ux\n", ctlr->tcr);
571 l += snprint(p+l, READSTR-l, "rcr: %#8.8ux\n", ctlr->rcr);
572 l += snprint(p+l, READSTR-l, "multicast: %ud\n", ctlr->mcast);
573
574 if(ctlr->mii != nil && ctlr->mii->curphy != nil){
575 l += snprint(p+l, READSTR, "phy: ");
576 for(i = 0; i < NMiiPhyr; i++){
577 if(i && ((i & 0x07) == 0))
578 l += snprint(p+l, READSTR-l, "\n ");
579 r = miimir(ctlr->mii, i);
580 l += snprint(p+l, READSTR-l, " %4.4ux", r);
581 }
582 snprint(p+l, READSTR-l, "\n");
583 }
584 s = p + l + 1;
585 // s = seprintmark(s, e, &ctlr->wmrb);
586 s = seprintmark(s, e, &ctlr->wmrd);
587 s = seprintmark(s, e, &ctlr->wmtd);
588 USED(s);
589
590 n = readstr(offset, a, n, p);
591
592 qunlock(&ctlr->slock);
593 poperror();
594 free(p);
595
596 return n;
597 }
598
599 static void
rtl8169halt(Ctlr * ctlr)600 rtl8169halt(Ctlr* ctlr)
601 {
602 csr32w(ctlr, Timerint, 0);
603 csr8w(ctlr, Cr, 0);
604 csr16w(ctlr, Imr, 0);
605 csr16w(ctlr, Isr, ~0);
606 }
607
608 static int
rtl8169reset(Ctlr * ctlr)609 rtl8169reset(Ctlr* ctlr)
610 {
611 u32int r;
612 int timeo;
613
614 /*
615 * Soft reset the controller.
616 */
617 csr8w(ctlr, Cr, Rst);
618 for(r = timeo = 0; timeo < 1000; timeo++){
619 r = csr8r(ctlr, Cr);
620 if(!(r & Rst))
621 break;
622 delay(1);
623 }
624 rtl8169halt(ctlr);
625
626 if(r & Rst)
627 return -1;
628 return 0;
629 }
630
631 static void
rtl8169shutdown(Ether * ether)632 rtl8169shutdown(Ether *ether)
633 {
634 rtl8169reset(ether->ctlr);
635 }
636
637 static void
rtl8169replenish(Ctlr * ctlr)638 rtl8169replenish(Ctlr* ctlr)
639 {
640 D *d;
641 int rdt;
642 Block *bp;
643
644 rdt = ctlr->rdt;
645 while(NEXT(rdt, ctlr->nrd) != ctlr->rdh){
646 d = &ctlr->rd[rdt];
647 if(ctlr->rb[rdt] == nil){
648 /*
649 * Simple allocation for now.
650 * This better be aligned on 8.
651 */
652 bp = iallocb(Mps);
653 if(bp == nil){
654 iprint("no available buffers\n");
655 break;
656 }
657 ctlr->rb[rdt] = bp;
658 d->addrlo = PCIWADDR(bp->rp);
659 d->addrhi = 0;
660 coherence();
661 }else
662 iprint("i8169: rx overrun\n");
663 d->control |= Own|Mps;
664 rdt = NEXT(rdt, ctlr->nrd);
665 ctlr->nrdfree++;
666 }
667 ctlr->rdt = rdt;
668 }
669
670 static int
rtl8169init(Ether * edev)671 rtl8169init(Ether* edev)
672 {
673 u32int r;
674 Ctlr *ctlr;
675 u8int cplusc;
676
677 ctlr = edev->ctlr;
678 ilock(&ctlr->ilock);
679
680 rtl8169reset(ctlr);
681
682 /*
683 * MAC Address is not settable on some (all?) chips.
684 * Must put chip into config register write enable mode.
685 */
686 csr8w(ctlr, Cr9346, Eem1|Eem0);
687
688 /*
689 * Transmitter.
690 */
691 memset(ctlr->td, 0, sizeof(D)*ctlr->ntd);
692 ctlr->tdh = ctlr->tdt = 0;
693 ctlr->td[ctlr->ntd-1].control = Eor;
694
695 /*
696 * Receiver.
697 * Need to do something here about the multicast filter.
698 */
699 memset(ctlr->rd, 0, sizeof(D)*ctlr->nrd);
700 ctlr->nrdfree = ctlr->rdh = ctlr->rdt = 0;
701 ctlr->rd[ctlr->nrd-1].control = Eor;
702
703 rtl8169replenish(ctlr);
704 ctlr->rcr = Rxfthnone|Mrxdmaunlimited|Ab|Am|Apm;
705
706 /*
707 * Setting Mulrw in Cplusc disables the Tx/Rx DMA burst
708 * settings in Tcr/Rcr; the (1<<14) is magic.
709 */
710 cplusc = csr16r(ctlr, Cplusc) & ~(1<<14);
711 cplusc |= /*Rxchksum|*/Mulrw;
712 switch(ctlr->macv){
713 default:
714 panic("ether8169: unknown macv %#08ux for vid %#ux did %#ux",
715 ctlr->macv, ctlr->pcidev->vid, ctlr->pcidev->did);
716 case Macv01:
717 break;
718 case Macv02:
719 case Macv03:
720 cplusc |= 1<<14; /* magic */
721 break;
722 case Macv05:
723 /*
724 * This is interpreted from clearly bogus code
725 * in the manufacturer-supplied driver, it could
726 * be wrong. Untested.
727 */
728 r = csr8r(ctlr, Config2) & 0x07;
729 if(r == 0x01) /* 66MHz PCI */
730 csr32w(ctlr, 0x7C, 0x0007FFFF); /* magic */
731 else
732 csr32w(ctlr, 0x7C, 0x0007FF00); /* magic */
733 pciclrmwi(ctlr->pcidev);
734 break;
735 case Macv13:
736 /*
737 * This is interpreted from clearly bogus code
738 * in the manufacturer-supplied driver, it could
739 * be wrong. Untested.
740 */
741 pcicfgw8(ctlr->pcidev, 0x68, 0x00); /* magic */
742 pcicfgw8(ctlr->pcidev, 0x69, 0x08); /* magic */
743 break;
744 case Macv04:
745 case Macv07:
746 case Macv07a:
747 case Macv11:
748 case Macv12:
749 case Macv12a:
750 case Macv14:
751 case Macv15:
752 case Macv25:
753 case Macv2c:
754 case Macv34:
755 break;
756 }
757
758 /*
759 * Enable receiver/transmitter.
760 * Need to do this first or some of the settings below
761 * won't take.
762 */
763 switch(ctlr->pciv){
764 default:
765 csr8w(ctlr, Cr, Te|Re);
766 csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited);
767 csr32w(ctlr, Rcr, ctlr->rcr);
768 csr32w(ctlr, Mar0, 0);
769 csr32w(ctlr, Mar0+4, 0);
770 ctlr->mchash = 0;
771 case Rtl8169sc:
772 case Rtl8168b:
773 break;
774 }
775
776 /*
777 * Interrupts.
778 * Disable Tdu|Tok for now, the transmit routine will tidy.
779 * Tdu means the NIC ran out of descriptors to send, so it
780 * doesn't really need to ever be on.
781 */
782 csr32w(ctlr, Timerint, 0);
783 ctlr->imr = Serr|Timeout|Fovw|Punlc|Rdu|Ter|Rer|Rok;
784 csr16w(ctlr, Imr, ctlr->imr);
785
786 /*
787 * Clear missed-packet counter;
788 * clear early transmit threshold value;
789 * set the descriptor ring base addresses;
790 * set the maximum receive packet size;
791 * no early-receive interrupts.
792 *
793 * note: the maximum rx size is a filter. the size of the buffer
794 * in the descriptor ring is still honored. we will toss >Mtu
795 * packets because they've been fragmented into multiple
796 * rx buffers.
797 */
798 csr32w(ctlr, Mpc, 0);
799 csr8w(ctlr, Etx, 0x3f); /* magic */
800 csr32w(ctlr, Tnpds+4, 0);
801 csr32w(ctlr, Tnpds, PCIWADDR(ctlr->td));
802 csr32w(ctlr, Rdsar+4, 0);
803 csr32w(ctlr, Rdsar, PCIWADDR(ctlr->rd));
804 csr16w(ctlr, Rms, 16383); /* was Mps; see above comment */
805 r = csr16r(ctlr, Mulint) & 0xF000; /* no early rx interrupts */
806 csr16w(ctlr, Mulint, r);
807 csr16w(ctlr, Cplusc, cplusc);
808 csr16w(ctlr, Coal, 0);
809
810 /*
811 * Set configuration.
812 */
813 switch(ctlr->pciv){
814 case Rtl8169sc:
815 csr8w(ctlr, Cr, Te|Re);
816 csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited);
817 csr32w(ctlr, Rcr, ctlr->rcr);
818 break;
819 case Rtl8168b:
820 case Rtl8169c:
821 csr16w(ctlr, Cplusc, 0x2000); /* magic */
822 csr8w(ctlr, Cr, Te|Re);
823 csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited);
824 csr32w(ctlr, Rcr, ctlr->rcr);
825 break;
826 }
827 ctlr->tcr = csr32r(ctlr, Tcr);
828 csr8w(ctlr, Cr9346, 0);
829
830 iunlock(&ctlr->ilock);
831
832 // rtl8169mii(ctlr);
833
834 return 0;
835 }
836
837 static void
rtl8169attach(Ether * edev)838 rtl8169attach(Ether* edev)
839 {
840 int timeo;
841 Ctlr *ctlr;
842
843 ctlr = edev->ctlr;
844 qlock(&ctlr->alock);
845 if(ctlr->init == 0){
846 ctlr->td = mallocalign(sizeof(D)*Ntd, 256, 0, 0);
847 ctlr->tb = malloc(Ntd*sizeof(Block*));
848 ctlr->ntd = Ntd;
849 ctlr->rd = mallocalign(sizeof(D)*Nrd, 256, 0, 0);
850 ctlr->rb = malloc(Nrd*sizeof(Block*));
851 ctlr->nrd = Nrd;
852 ctlr->dtcc = mallocalign(sizeof(Dtcc), 64, 0, 0);
853 if(ctlr->td == nil || ctlr->tb == nil || ctlr->rd == nil ||
854 ctlr->rb == nil || ctlr->dtcc == nil) {
855 free(ctlr->td);
856 free(ctlr->tb);
857 free(ctlr->rd);
858 free(ctlr->rb);
859 free(ctlr->dtcc);
860 qunlock(&ctlr->alock);
861 error(Enomem);
862 }
863 rtl8169init(edev);
864 // initmark(&ctlr->wmrb, Nrb, "rcv bufs unprocessed");
865 initmark(&ctlr->wmrd, Nrd-1, "rcv descrs processed at once");
866 initmark(&ctlr->wmtd, Ntd-1, "xmit descr queue len");
867 ctlr->init = 1;
868 }
869 qunlock(&ctlr->alock);
870
871 /* Don't wait long for link to be ready. */
872 for(timeo = 0; timeo < 10; timeo++){
873 if(miistatus(ctlr->mii) == 0)
874 break;
875 delay(100); /* print fewer miistatus messages */
876 }
877 }
878
879 static void
rtl8169link(Ether * edev)880 rtl8169link(Ether* edev)
881 {
882 uint r;
883 int limit;
884 Ctlr *ctlr;
885
886 ctlr = edev->ctlr;
887
888 /*
889 * Maybe the link changed - do we care very much?
890 * Could stall transmits if no link, maybe?
891 */
892 if(!((r = csr8r(ctlr, Phystatus)) & Linksts)){
893 edev->link = 0;
894 return;
895 }
896 edev->link = 1;
897
898 limit = 256*1024;
899 if(r & Speed10){
900 edev->mbps = 10;
901 limit = 65*1024;
902 } else if(r & Speed100)
903 edev->mbps = 100;
904 else if(r & Speed1000)
905 edev->mbps = 1000;
906
907 if(edev->oq != nil)
908 qsetlimit(edev->oq, limit);
909 }
910
911 static void
rtl8169transmit(Ether * edev)912 rtl8169transmit(Ether* edev)
913 {
914 D *d;
915 Block *bp;
916 Ctlr *ctlr;
917 int control, x;
918
919 ctlr = edev->ctlr;
920
921 ilock(&ctlr->tlock);
922 for(x = ctlr->tdh; ctlr->ntq > 0; x = NEXT(x, ctlr->ntd)){
923 d = &ctlr->td[x];
924 if((control = d->control) & Own)
925 break;
926
927 /*
928 * Check errors and log here.
929 */
930 USED(control);
931
932 /*
933 * Free it up.
934 * Need to clean the descriptor here? Not really.
935 * Simple freeb for now (no chain and freeblist).
936 * Use ntq count for now.
937 */
938 freeb(ctlr->tb[x]);
939 ctlr->tb[x] = nil;
940 d->control &= Eor;
941
942 ctlr->ntq--;
943 }
944 ctlr->tdh = x;
945
946 x = ctlr->tdt;
947 while(ctlr->ntq < (ctlr->ntd-1)){
948 if((bp = qget(edev->oq)) == nil)
949 break;
950
951 d = &ctlr->td[x];
952 d->addrlo = PCIWADDR(bp->rp);
953 d->addrhi = 0;
954 ctlr->tb[x] = bp;
955 coherence();
956 d->control |= Own | Fs | Ls | BLEN(bp);
957
958 /* note size of queue of tds awaiting transmission */
959 notemark(&ctlr->wmtd, (x + Ntd - ctlr->tdh) % Ntd);
960 x = NEXT(x, ctlr->ntd);
961 ctlr->ntq++;
962 }
963 if(x != ctlr->tdt){
964 ctlr->tdt = x;
965 csr8w(ctlr, Tppoll, Npq);
966 }
967 else if(ctlr->ntq >= (ctlr->ntd-1))
968 ctlr->txdu++;
969
970 iunlock(&ctlr->tlock);
971 }
972
973 static void
rtl8169receive(Ether * edev)974 rtl8169receive(Ether* edev)
975 {
976 D *d;
977 int rdh, passed;
978 Block *bp;
979 Ctlr *ctlr;
980 u32int control;
981
982 ctlr = edev->ctlr;
983
984 rdh = ctlr->rdh;
985 passed = 0;
986 for(;;){
987 d = &ctlr->rd[rdh];
988
989 if(d->control & Own)
990 break;
991
992 control = d->control;
993 if((control & (Fs|Ls|Res)) == (Fs|Ls)){
994 bp = ctlr->rb[rdh];
995 bp->wp = bp->rp + (control & RxflMASK) - 4;
996
997 if(control & Fovf)
998 ctlr->fovf++;
999 if(control & Mar)
1000 ctlr->mcast++;
1001
1002 switch(control & (Pid1|Pid0)){
1003 default:
1004 break;
1005 case Pid0:
1006 if(control & Tcpf){
1007 ctlr->tcpf++;
1008 break;
1009 }
1010 bp->flag |= Btcpck;
1011 break;
1012 case Pid1:
1013 if(control & Udpf){
1014 ctlr->udpf++;
1015 break;
1016 }
1017 bp->flag |= Budpck;
1018 break;
1019 case Pid1|Pid0:
1020 if(control & Ipf){
1021 ctlr->ipf++;
1022 break;
1023 }
1024 bp->flag |= Bipck;
1025 break;
1026 }
1027 etheriq(edev, bp, 1);
1028 passed++;
1029 }else{
1030 if(!(control & Res))
1031 ctlr->frag++;
1032 /* iprint("i8169: control %#.8ux\n", control); */
1033 freeb(ctlr->rb[rdh]);
1034 }
1035 ctlr->rb[rdh] = nil;
1036 d->control &= Eor;
1037 ctlr->nrdfree--;
1038 rdh = NEXT(rdh, ctlr->nrd);
1039
1040 if(ctlr->nrdfree < ctlr->nrd/2)
1041 rtl8169replenish(ctlr);
1042 }
1043 /* note how many rds had full buffers */
1044 notemark(&ctlr->wmrd, passed);
1045 ctlr->rdh = rdh;
1046 }
1047
1048 static void
rtl8169interrupt(Ureg *,void * arg)1049 rtl8169interrupt(Ureg*, void* arg)
1050 {
1051 Ctlr *ctlr;
1052 Ether *edev;
1053 u32int isr;
1054
1055 edev = arg;
1056 ctlr = edev->ctlr;
1057
1058 while((isr = csr16r(ctlr, Isr)) != 0 && isr != 0xFFFF){
1059 csr16w(ctlr, Isr, isr);
1060 if((isr & ctlr->imr) == 0)
1061 break;
1062 if(isr & (Fovw|Punlc|Rdu|Rer|Rok)){
1063 rtl8169receive(edev);
1064 if(!(isr & (Punlc|Rok)))
1065 ctlr->ierrs++;
1066 if(isr & Rer)
1067 ctlr->rer++;
1068 if(isr & Rdu)
1069 ctlr->rdu++;
1070 if(isr & Punlc)
1071 ctlr->punlc++;
1072 if(isr & Fovw)
1073 ctlr->fovw++;
1074 isr &= ~(Fovw|Rdu|Rer|Rok);
1075 }
1076
1077 if(isr & (Tdu|Ter|Tok)){
1078 rtl8169transmit(edev);
1079 isr &= ~(Tdu|Ter|Tok);
1080 }
1081
1082 if(isr & Punlc){
1083 rtl8169link(edev);
1084 isr &= ~Punlc;
1085 }
1086
1087 /*
1088 * Some of the reserved bits get set sometimes...
1089 */
1090 if(isr & (Serr|Timeout|Tdu|Fovw|Punlc|Rdu|Ter|Tok|Rer|Rok))
1091 panic("rtl8169interrupt: imr %#4.4ux isr %#4.4ux",
1092 csr16r(ctlr, Imr), isr);
1093 }
1094 }
1095
1096 int
vetmacv(Ctlr * ctlr,uint * macv)1097 vetmacv(Ctlr *ctlr, uint *macv)
1098 {
1099 *macv = csr32r(ctlr, Tcr) & HwveridMASK;
1100 switch(*macv){
1101 default:
1102 return -1;
1103 case Macv01:
1104 case Macv02:
1105 case Macv03:
1106 case Macv04:
1107 case Macv05:
1108 case Macv07:
1109 case Macv07a:
1110 case Macv11:
1111 case Macv12:
1112 case Macv12a:
1113 case Macv13:
1114 case Macv14:
1115 case Macv15:
1116 case Macv25:
1117 case Macv2c:
1118 case Macv34:
1119 break;
1120 }
1121 return 0;
1122 }
1123
1124 static void
rtl8169pci(void)1125 rtl8169pci(void)
1126 {
1127 Pcidev *p;
1128 Ctlr *ctlr;
1129 int i, port, pcie;
1130 uint macv;
1131
1132 p = nil;
1133 while(p = pcimatch(p, 0, 0)){
1134 if(p->ccrb != 0x02 || p->ccru != 0)
1135 continue;
1136
1137 pcie = 0;
1138 switch(i = ((p->did<<16)|p->vid)){
1139 default:
1140 continue;
1141 case Rtl8100e: /* RTL810[01]E ? */
1142 case Rtl8168b: /* RTL8168B */
1143 pcie = 1;
1144 break;
1145 case Rtl8169c: /* RTL8169C */
1146 case Rtl8169sc: /* RTL8169SC */
1147 case Rtl8169: /* RTL8169 */
1148 break;
1149 case (0xC107<<16)|0x1259: /* Corega CG-LAPCIGT */
1150 i = Rtl8169;
1151 break;
1152 }
1153
1154 port = p->mem[0].bar & ~0x01;
1155 if(ioalloc(port, p->mem[0].size, 0, "rtl8169") < 0){
1156 print("rtl8169: port %#ux in use\n", port);
1157 continue;
1158 }
1159 ctlr = malloc(sizeof(Ctlr));
1160 if(ctlr == nil)
1161 error(Enomem);
1162 ctlr->port = port;
1163 ctlr->pcidev = p;
1164 ctlr->pciv = i;
1165 ctlr->pcie = pcie;
1166
1167 if(vetmacv(ctlr, &macv) == -1){
1168 iofree(port);
1169 free(ctlr);
1170 print("rtl8169: unknown mac %.4ux %.8ux\n", p->did, macv);
1171 continue;
1172 }
1173
1174 if(pcigetpms(p) > 0){
1175 pcisetpms(p, 0);
1176
1177 for(i = 0; i < 6; i++)
1178 pcicfgw32(p, PciBAR0+i*4, p->mem[i].bar);
1179 pcicfgw8(p, PciINTL, p->intl);
1180 pcicfgw8(p, PciLTR, p->ltr);
1181 pcicfgw8(p, PciCLS, p->cls);
1182 pcicfgw16(p, PciPCR, p->pcr);
1183 }
1184
1185 if(rtl8169reset(ctlr)){
1186 iofree(port);
1187 free(ctlr);
1188 continue;
1189 }
1190
1191 /*
1192 * Extract the chip hardware version,
1193 * needed to configure each properly.
1194 */
1195 ctlr->macv = macv;
1196
1197 rtl8169mii(ctlr);
1198
1199 pcisetbme(p);
1200
1201 if(rtl8169ctlrhead != nil)
1202 rtl8169ctlrtail->next = ctlr;
1203 else
1204 rtl8169ctlrhead = ctlr;
1205 rtl8169ctlrtail = ctlr;
1206 }
1207 }
1208
1209 static int
rtl8169pnp(Ether * edev)1210 rtl8169pnp(Ether* edev)
1211 {
1212 u32int r;
1213 Ctlr *ctlr;
1214 uchar ea[Eaddrlen];
1215 static int once;
1216
1217 if(once == 0){
1218 once = 1;
1219 rtl8169pci();
1220 }
1221
1222 /*
1223 * Any adapter matches if no edev->port is supplied,
1224 * otherwise the ports must match.
1225 */
1226 for(ctlr = rtl8169ctlrhead; ctlr != nil; ctlr = ctlr->next){
1227 if(ctlr->active)
1228 continue;
1229 if(edev->port == 0 || edev->port == ctlr->port){
1230 ctlr->active = 1;
1231 break;
1232 }
1233 }
1234 if(ctlr == nil)
1235 return -1;
1236
1237 edev->ctlr = ctlr;
1238 edev->port = ctlr->port;
1239 edev->irq = ctlr->pcidev->intl;
1240 edev->tbdf = ctlr->pcidev->tbdf;
1241 edev->mbps = 1000;
1242 edev->maxmtu = Mtu;
1243
1244 /*
1245 * Check if the adapter's station address is to be overridden.
1246 * If not, read it from the device and set in edev->ea.
1247 */
1248 memset(ea, 0, Eaddrlen);
1249 if(memcmp(ea, edev->ea, Eaddrlen) == 0){
1250 r = csr32r(ctlr, Idr0);
1251 edev->ea[0] = r;
1252 edev->ea[1] = r>>8;
1253 edev->ea[2] = r>>16;
1254 edev->ea[3] = r>>24;
1255 r = csr32r(ctlr, Idr0+4);
1256 edev->ea[4] = r;
1257 edev->ea[5] = r>>8;
1258 }
1259
1260 edev->attach = rtl8169attach;
1261 edev->transmit = rtl8169transmit;
1262 edev->interrupt = rtl8169interrupt;
1263 edev->ifstat = rtl8169ifstat;
1264
1265 edev->arg = edev;
1266 edev->promiscuous = rtl8169promiscuous;
1267 edev->multicast = rtl8169multicast;
1268 edev->shutdown = rtl8169shutdown;
1269
1270 rtl8169link(edev);
1271
1272 return 0;
1273 }
1274
1275 void
ether8169link(void)1276 ether8169link(void)
1277 {
1278 addethercard("rtl8169", rtl8169pnp);
1279 }
1280