1 /* 2 * Realtek RTL8110S/8169S Gigabit Ethernet Controllers. 3 * Mostly there. There are some magic register values used 4 * which are not described in any datasheet or driver but seem 5 * to be necessary. 6 * No tuning has been done. Only tested on an RTL8110S, there 7 * are slight differences between the chips in the series so some 8 * tweaks may be needed. 9 */ 10 #include "u.h" 11 #include "../port/lib.h" 12 #include "mem.h" 13 #include "dat.h" 14 #include "fns.h" 15 #include "io.h" 16 #include "../port/error.h" 17 #include "../port/netif.h" 18 19 #include "etherif.h" 20 #include "ethermii.h" 21 22 enum { /* registers */ 23 Idr0 = 0x00, /* MAC address */ 24 Mar0 = 0x08, /* Multicast address */ 25 Dtccr = 0x10, /* Dump Tally Counter Command */ 26 Tnpds = 0x20, /* Transmit Normal Priority Descriptors */ 27 Thpds = 0x28, /* Transmit High Priority Descriptors */ 28 Flash = 0x30, /* Flash Memory Read/Write */ 29 Erbcr = 0x34, /* Early Receive Byte Count */ 30 Ersr = 0x36, /* Early Receive Status */ 31 Cr = 0x37, /* Command Register */ 32 Tppoll = 0x38, /* Transmit Priority Polling */ 33 Imr = 0x3C, /* Interrupt Mask */ 34 Isr = 0x3E, /* Interrupt Status */ 35 Tcr = 0x40, /* Transmit Configuration */ 36 Rcr = 0x44, /* Receive Configuration */ 37 Tctr = 0x48, /* Timer Count */ 38 Mpc = 0x4C, /* Missed Packet Counter */ 39 Cr9346 = 0x50, /* 9346 Command Register */ 40 Config0 = 0x51, /* Configuration Register 0 */ 41 Config1 = 0x52, /* Configuration Register 1 */ 42 Config2 = 0x53, /* Configuration Register 2 */ 43 Config3 = 0x54, /* Configuration Register 3 */ 44 Config4 = 0x55, /* Configuration Register 4 */ 45 Config5 = 0x56, /* Configuration Register 5 */ 46 Timerint = 0x58, /* Timer Interrupt */ 47 Mulint = 0x5C, /* Multiple Interrupt Select */ 48 Phyar = 0x60, /* PHY Access */ 49 Tbicsr0 = 0x64, /* TBI Control and Status */ 50 Tbianar = 0x68, /* TBI Auto-Negotiation Advertisment */ 51 Tbilpar = 0x6A, /* TBI Auto-Negotiation Link Partner */ 52 Phystatus = 0x6C, /* PHY Status */ 53 54 Rms = 0xDA, /* Receive Packet Maximum Size */ 55 Cplusc = 0xE0, /* C+ Command */ 56 Coal = 0xE2, /* Interrupt Mitigation (Coalesce) */ 57 Rdsar = 0xE4, /* Receive Descriptor Start Address */ 58 Etx = 0xEC, /* Early Transmit Threshold */ 59 }; 60 61 enum { /* Dtccr */ 62 Cmd = 0x00000008, /* Command */ 63 }; 64 65 enum { /* Cr */ 66 Te = 0x04, /* Transmitter Enable */ 67 Re = 0x08, /* Receiver Enable */ 68 Rst = 0x10, /* Software Reset */ 69 }; 70 71 enum { /* Tppoll */ 72 Fswint = 0x01, /* Forced Software Interrupt */ 73 Npq = 0x40, /* Normal Priority Queue polling */ 74 Hpq = 0x80, /* High Priority Queue polling */ 75 }; 76 77 enum { /* Imr/Isr */ 78 Rok = 0x0001, /* Receive OK */ 79 Rer = 0x0002, /* Receive Error */ 80 Tok = 0x0004, /* Transmit OK */ 81 Ter = 0x0008, /* Transmit Error */ 82 Rdu = 0x0010, /* Receive Descriptor Unavailable */ 83 Punlc = 0x0020, /* Packet Underrun or Link Change */ 84 Fovw = 0x0040, /* Receive FIFO Overflow */ 85 Tdu = 0x0080, /* Transmit Descriptor Unavailable */ 86 Swint = 0x0100, /* Software Interrupt */ 87 Timeout = 0x4000, /* Timer */ 88 Serr = 0x8000, /* System Error */ 89 }; 90 91 enum { /* Tcr */ 92 MtxdmaSHIFT = 8, /* Max. DMA Burst Size */ 93 MtxdmaMASK = 0x00000700, 94 Mtxdmaunlimited = 0x00000700, 95 Acrc = 0x00010000, /* Append CRC (not) */ 96 Lbk0 = 0x00020000, /* Loopback Test 0 */ 97 Lbk1 = 0x00040000, /* Loopback Test 1 */ 98 Ifg2 = 0x00080000, /* Interframe Gap 2 */ 99 HwveridSHIFT = 23, /* Hardware Version ID */ 100 HwveridMASK = 0x7C800000, 101 Macv01 = 0x00000000, /* RTL8169 */ 102 Macv02 = 0x00800000, /* RTL8169S/8110S */ 103 Macv03 = 0x04000000, /* RTL8169S/8110S */ 104 Macv04 = 0x10000000, /* RTL8169SB/8110SB */ 105 Macv05 = 0x18000000, /* RTL8169SC/8110SC */ 106 Macv07 = 0x24800000, /* RTL8102e */ 107 Macv07a = 0x34800000, /* RTL8102e */ 108 Macv11 = 0x30000000, /* RTL8168B/8111B */ 109 Macv12 = 0x38000000, /* RTL8169B/8111B */ 110 Macv12a = 0x3c000000, /* RTL8169C/8111C */ 111 Macv13 = 0x34000000, /* RTL8101E */ 112 Macv14 = 0x30800000, /* RTL8100E */ 113 Macv15 = 0x38800000, /* RTL8100E */ 114 // Macv19 = 0x3c000000, /* dup Macv12a: RTL8111c-gr */ 115 Macv25 = 0x28000000, /* RTL8168D */ 116 Macv2c = 0x2c000000, /* RTL8168E */ 117 Macv34 = 0x2c800000, /* RTL8168E */ 118 Ifg0 = 0x01000000, /* Interframe Gap 0 */ 119 Ifg1 = 0x02000000, /* Interframe Gap 1 */ 120 }; 121 122 enum { /* Rcr */ 123 Aap = 0x00000001, /* Accept All Packets */ 124 Apm = 0x00000002, /* Accept Physical Match */ 125 Am = 0x00000004, /* Accept Multicast */ 126 Ab = 0x00000008, /* Accept Broadcast */ 127 Ar = 0x00000010, /* Accept Runt */ 128 Aer = 0x00000020, /* Accept Error */ 129 Sel9356 = 0x00000040, /* 9356 EEPROM used */ 130 MrxdmaSHIFT = 8, /* Max. DMA Burst Size */ 131 MrxdmaMASK = 0x00000700, 132 Mrxdmaunlimited = 0x00000700, 133 RxfthSHIFT = 13, /* Receive Buffer Length */ 134 RxfthMASK = 0x0000E000, 135 Rxfth256 = 0x00008000, 136 Rxfthnone = 0x0000E000, 137 Rer8 = 0x00010000, /* Accept Error Packets > 8 bytes */ 138 MulERINT = 0x01000000, /* Multiple Early Interrupt Select */ 139 }; 140 141 enum { /* Cr9346 */ 142 Eedo = 0x01, /* */ 143 Eedi = 0x02, /* */ 144 Eesk = 0x04, /* */ 145 Eecs = 0x08, /* */ 146 Eem0 = 0x40, /* Operating Mode */ 147 Eem1 = 0x80, 148 }; 149 150 enum { /* Phyar */ 151 DataMASK = 0x0000FFFF, /* 16-bit GMII/MII Register Data */ 152 DataSHIFT = 0, 153 RegaddrMASK = 0x001F0000, /* 5-bit GMII/MII Register Address */ 154 RegaddrSHIFT = 16, 155 Flag = 0x80000000, /* */ 156 }; 157 158 enum { /* Phystatus */ 159 Fd = 0x01, /* Full Duplex */ 160 Linksts = 0x02, /* Link Status */ 161 Speed10 = 0x04, /* */ 162 Speed100 = 0x08, /* */ 163 Speed1000 = 0x10, /* */ 164 Rxflow = 0x20, /* */ 165 Txflow = 0x40, /* */ 166 Entbi = 0x80, /* */ 167 }; 168 169 enum { /* Cplusc */ 170 Mulrw = 0x0008, /* PCI Multiple R/W Enable */ 171 Dac = 0x0010, /* PCI Dual Address Cycle Enable */ 172 Rxchksum = 0x0020, /* Receive Checksum Offload Enable */ 173 Rxvlan = 0x0040, /* Receive VLAN De-tagging Enable */ 174 Endian = 0x0200, /* Endian Mode */ 175 }; 176 177 typedef struct D D; /* Transmit/Receive Descriptor */ 178 struct D { 179 u32int control; 180 u32int vlan; 181 u32int addrlo; 182 u32int addrhi; 183 }; 184 185 enum { /* Transmit Descriptor control */ 186 TxflMASK = 0x0000FFFF, /* Transmit Frame Length */ 187 TxflSHIFT = 0, 188 Tcps = 0x00010000, /* TCP Checksum Offload */ 189 Udpcs = 0x00020000, /* UDP Checksum Offload */ 190 Ipcs = 0x00040000, /* IP Checksum Offload */ 191 Lgsen = 0x08000000, /* TSO; WARNING: contains lark's vomit */ 192 }; 193 194 enum { /* Receive Descriptor control */ 195 RxflMASK = 0x00001FFF, /* Receive Frame Length */ 196 Tcpf = 0x00004000, /* TCP Checksum Failure */ 197 Udpf = 0x00008000, /* UDP Checksum Failure */ 198 Ipf = 0x00010000, /* IP Checksum Failure */ 199 Pid0 = 0x00020000, /* Protocol ID0 */ 200 Pid1 = 0x00040000, /* Protocol ID1 */ 201 Crce = 0x00080000, /* CRC Error */ 202 Runt = 0x00100000, /* Runt Packet */ 203 Res = 0x00200000, /* Receive Error Summary */ 204 Rwt = 0x00400000, /* Receive Watchdog Timer Expired */ 205 Fovf = 0x00800000, /* FIFO Overflow */ 206 Bovf = 0x01000000, /* Buffer Overflow */ 207 Bar = 0x02000000, /* Broadcast Address Received */ 208 Pam = 0x04000000, /* Physical Address Matched */ 209 Mar = 0x08000000, /* Multicast Address Received */ 210 }; 211 212 enum { /* General Descriptor control */ 213 Ls = 0x10000000, /* Last Segment Descriptor */ 214 Fs = 0x20000000, /* First Segment Descriptor */ 215 Eor = 0x40000000, /* End of Descriptor Ring */ 216 Own = 0x80000000, /* Ownership */ 217 }; 218 219 /* 220 */ 221 enum { /* Ring sizes (<= 1024) */ 222 Ntd = 64, /* Transmit Ring */ 223 Nrd = 1024, /* Receive Ring */ 224 225 Mtu = ETHERMAXTU, 226 Mps = ROUNDUP(ETHERMAXTU+4, 128), 227 // Mps = Mtu + 8 + 14, /* if(mtu>ETHERMAXTU) */ 228 }; 229 230 typedef struct Dtcc Dtcc; 231 struct Dtcc { 232 u64int txok; 233 u64int rxok; 234 u64int txer; 235 u32int rxer; 236 u16int misspkt; 237 u16int fae; 238 u32int tx1col; 239 u32int txmcol; 240 u64int rxokph; 241 u64int rxokbrd; 242 u32int rxokmu; 243 u16int txabt; 244 u16int txundrn; 245 }; 246 247 enum { /* Variants */ 248 Rtl8100e = (0x8136<<16)|0x10EC, /* RTL810[01]E: pci -e */ 249 Rtl8169c = (0x0116<<16)|0x16EC, /* RTL8169C+ (USR997902) */ 250 Rtl8169sc = (0x8167<<16)|0x10EC, /* RTL8169SC */ 251 Rtl8168b = (0x8168<<16)|0x10EC, /* RTL8168B: pci-e */ 252 Rtl8169 = (0x8169<<16)|0x10EC, /* RTL8169 */ 253 }; 254 255 typedef struct Ctlr Ctlr; 256 typedef struct Ctlr { 257 int port; 258 Pcidev* pcidev; 259 Ctlr* next; 260 int active; 261 262 QLock alock; /* attach */ 263 Lock ilock; /* init */ 264 int init; /* */ 265 266 int pciv; /* */ 267 int macv; /* MAC version */ 268 int phyv; /* PHY version */ 269 int pcie; /* flag: pci-express device? */ 270 271 uvlong mchash; /* multicast hash */ 272 273 Mii* mii; 274 275 Lock tlock; /* transmit */ 276 D* td; /* descriptor ring */ 277 Block** tb; /* transmit buffers */ 278 int ntd; 279 280 int tdh; /* head - producer index (host) */ 281 int tdt; /* tail - consumer index (NIC) */ 282 int ntdfree; 283 int ntq; 284 285 // int rbsz; /* receive buffer size */ 286 287 Lock rlock; /* receive */ 288 D* rd; /* descriptor ring */ 289 Block** rb; /* receive buffers */ 290 int nrd; 291 292 int rdh; /* head - producer index (NIC) */ 293 int rdt; /* tail - consumer index (host) */ 294 int nrdfree; 295 296 int tcr; /* transmit configuration register */ 297 int rcr; /* receive configuration register */ 298 int imr; 299 300 QLock slock; /* statistics */ 301 Dtcc* dtcc; 302 uint txdu; 303 uint tcpf; 304 uint udpf; 305 uint ipf; 306 uint fovf; 307 uint ierrs; 308 uint rer; 309 uint rdu; 310 uint punlc; 311 uint fovw; 312 uint mcast; 313 uint frag; /* partial packets; rb was too small */ 314 } Ctlr; 315 316 static Ctlr* rtl8169ctlrhead; 317 static Ctlr* rtl8169ctlrtail; 318 319 #define csr8r(c, r) (inb((c)->port+(r))) 320 #define csr16r(c, r) (ins((c)->port+(r))) 321 #define csr32r(c, r) (inl((c)->port+(r))) 322 #define csr8w(c, r, b) (outb((c)->port+(r), (u8int)(b))) 323 #define csr16w(c, r, w) (outs((c)->port+(r), (u16int)(w))) 324 #define csr32w(c, r, l) (outl((c)->port+(r), (u32int)(l))) 325 326 static int 327 rtl8169miimir(Mii* mii, int pa, int ra) 328 { 329 uint r; 330 int timeo; 331 Ctlr *ctlr; 332 333 if(pa != 1) 334 return -1; 335 ctlr = mii->ctlr; 336 337 r = (ra<<16) & RegaddrMASK; 338 csr32w(ctlr, Phyar, r); 339 delay(1); 340 for(timeo = 0; timeo < 2000; timeo++){ 341 if((r = csr32r(ctlr, Phyar)) & Flag) 342 break; 343 microdelay(100); 344 } 345 if(!(r & Flag)) 346 return -1; 347 348 return (r & DataMASK)>>DataSHIFT; 349 } 350 351 static int 352 rtl8169miimiw(Mii* mii, int pa, int ra, int data) 353 { 354 uint r; 355 int timeo; 356 Ctlr *ctlr; 357 358 if(pa != 1) 359 return -1; 360 ctlr = mii->ctlr; 361 362 r = Flag|((ra<<16) & RegaddrMASK)|((data<<DataSHIFT) & DataMASK); 363 csr32w(ctlr, Phyar, r); 364 delay(1); 365 for(timeo = 0; timeo < 2000; timeo++){ 366 if(!((r = csr32r(ctlr, Phyar)) & Flag)) 367 break; 368 microdelay(100); 369 } 370 if(r & Flag) 371 return -1; 372 373 return 0; 374 } 375 376 static int 377 rtl8169mii(Ctlr* ctlr) 378 { 379 MiiPhy *phy; 380 381 /* 382 * Link management. 383 */ 384 if((ctlr->mii = malloc(sizeof(Mii))) == nil) 385 return -1; 386 ctlr->mii->mir = rtl8169miimir; 387 ctlr->mii->miw = rtl8169miimiw; 388 ctlr->mii->ctlr = ctlr; 389 390 /* 391 * Get rev number out of Phyidr2 so can config properly. 392 * There's probably more special stuff for Macv0[234] needed here. 393 */ 394 ctlr->phyv = rtl8169miimir(ctlr->mii, 1, Phyidr2) & 0x0F; 395 if(ctlr->macv == Macv02){ 396 csr8w(ctlr, 0x82, 1); /* magic */ 397 rtl8169miimiw(ctlr->mii, 1, 0x0B, 0x0000); /* magic */ 398 } 399 400 if(mii(ctlr->mii, (1<<1)) == 0 || (phy = ctlr->mii->curphy) == nil){ 401 free(ctlr->mii); 402 ctlr->mii = nil; 403 return -1; 404 } 405 print("oui %#ux phyno %d, macv = %#8.8ux phyv = %#4.4ux\n", 406 phy->oui, phy->phyno, ctlr->macv, ctlr->phyv); 407 408 miiane(ctlr->mii, ~0, ~0, ~0); 409 410 return 0; 411 } 412 413 static void 414 rtl8169promiscuous(void* arg, int on) 415 { 416 Ether *edev; 417 Ctlr * ctlr; 418 419 edev = arg; 420 ctlr = edev->ctlr; 421 ilock(&ctlr->ilock); 422 423 if(on) 424 ctlr->rcr |= Aap; 425 else 426 ctlr->rcr &= ~Aap; 427 csr32w(ctlr, Rcr, ctlr->rcr); 428 iunlock(&ctlr->ilock); 429 } 430 431 enum { 432 /* everyone else uses 0x04c11db7, but they both produce the same crc */ 433 Etherpolybe = 0x04c11db6, 434 Bytemask = (1<<8) - 1, 435 }; 436 437 static ulong 438 ethercrcbe(uchar *addr, long len) 439 { 440 int i, j; 441 ulong c, crc, carry; 442 443 crc = ~0UL; 444 for (i = 0; i < len; i++) { 445 c = addr[i]; 446 for (j = 0; j < 8; j++) { 447 carry = ((crc & (1UL << 31))? 1: 0) ^ (c & 1); 448 crc <<= 1; 449 c >>= 1; 450 if (carry) 451 crc = (crc ^ Etherpolybe) | carry; 452 } 453 } 454 return crc; 455 } 456 457 static ulong 458 swabl(ulong l) 459 { 460 return l>>24 | (l>>8) & (Bytemask<<8) | 461 (l<<8) & (Bytemask<<16) | l<<24; 462 } 463 464 static void 465 rtl8169multicast(void* ether, uchar *eaddr, int add) 466 { 467 Ether *edev; 468 Ctlr *ctlr; 469 470 if (!add) 471 return; /* ok to keep receiving on old mcast addrs */ 472 473 edev = ether; 474 ctlr = edev->ctlr; 475 ilock(&ctlr->ilock); 476 477 ctlr->mchash |= 1ULL << (ethercrcbe(eaddr, Eaddrlen) >> 26); 478 479 ctlr->rcr |= Am; 480 csr32w(ctlr, Rcr, ctlr->rcr); 481 482 /* pci-e variants reverse the order of the hash byte registers */ 483 if (ctlr->pcie) { 484 csr32w(ctlr, Mar0, swabl(ctlr->mchash>>32)); 485 csr32w(ctlr, Mar0+4, swabl(ctlr->mchash)); 486 } else { 487 csr32w(ctlr, Mar0, ctlr->mchash); 488 csr32w(ctlr, Mar0+4, ctlr->mchash>>32); 489 } 490 491 iunlock(&ctlr->ilock); 492 } 493 494 static long 495 rtl8169ifstat(Ether* edev, void* a, long n, ulong offset) 496 { 497 char *p; 498 Ctlr *ctlr; 499 Dtcc *dtcc; 500 int i, l, r, timeo; 501 502 ctlr = edev->ctlr; 503 qlock(&ctlr->slock); 504 505 p = nil; 506 if(waserror()){ 507 qunlock(&ctlr->slock); 508 free(p); 509 nexterror(); 510 } 511 512 csr32w(ctlr, Dtccr+4, 0); 513 csr32w(ctlr, Dtccr, PCIWADDR(ctlr->dtcc)|Cmd); 514 for(timeo = 0; timeo < 1000; timeo++){ 515 if(!(csr32r(ctlr, Dtccr) & Cmd)) 516 break; 517 delay(1); 518 } 519 if(csr32r(ctlr, Dtccr) & Cmd) 520 error(Eio); 521 522 dtcc = ctlr->dtcc; 523 524 edev->oerrs = dtcc->txer; 525 edev->crcs = dtcc->rxer; 526 edev->frames = dtcc->fae; 527 edev->buffs = dtcc->misspkt; 528 edev->overflows = ctlr->txdu+ctlr->rdu; 529 530 if(n == 0){ 531 qunlock(&ctlr->slock); 532 poperror(); 533 return 0; 534 } 535 536 if((p = malloc(READSTR)) == nil) 537 error(Enomem); 538 539 l = snprint(p, READSTR, "TxOk: %llud\n", dtcc->txok); 540 l += snprint(p+l, READSTR-l, "RxOk: %llud\n", dtcc->rxok); 541 l += snprint(p+l, READSTR-l, "TxEr: %llud\n", dtcc->txer); 542 l += snprint(p+l, READSTR-l, "RxEr: %ud\n", dtcc->rxer); 543 l += snprint(p+l, READSTR-l, "MissPkt: %ud\n", dtcc->misspkt); 544 l += snprint(p+l, READSTR-l, "FAE: %ud\n", dtcc->fae); 545 l += snprint(p+l, READSTR-l, "Tx1Col: %ud\n", dtcc->tx1col); 546 l += snprint(p+l, READSTR-l, "TxMCol: %ud\n", dtcc->txmcol); 547 l += snprint(p+l, READSTR-l, "RxOkPh: %llud\n", dtcc->rxokph); 548 l += snprint(p+l, READSTR-l, "RxOkBrd: %llud\n", dtcc->rxokbrd); 549 l += snprint(p+l, READSTR-l, "RxOkMu: %ud\n", dtcc->rxokmu); 550 l += snprint(p+l, READSTR-l, "TxAbt: %ud\n", dtcc->txabt); 551 l += snprint(p+l, READSTR-l, "TxUndrn: %ud\n", dtcc->txundrn); 552 553 l += snprint(p+l, READSTR-l, "txdu: %ud\n", ctlr->txdu); 554 l += snprint(p+l, READSTR-l, "tcpf: %ud\n", ctlr->tcpf); 555 l += snprint(p+l, READSTR-l, "udpf: %ud\n", ctlr->udpf); 556 l += snprint(p+l, READSTR-l, "ipf: %ud\n", ctlr->ipf); 557 l += snprint(p+l, READSTR-l, "fovf: %ud\n", ctlr->fovf); 558 l += snprint(p+l, READSTR-l, "ierrs: %ud\n", ctlr->ierrs); 559 l += snprint(p+l, READSTR-l, "rer: %ud\n", ctlr->rer); 560 l += snprint(p+l, READSTR-l, "rdu: %ud\n", ctlr->rdu); 561 l += snprint(p+l, READSTR-l, "punlc: %ud\n", ctlr->punlc); 562 l += snprint(p+l, READSTR-l, "fovw: %ud\n", ctlr->fovw); 563 564 l += snprint(p+l, READSTR-l, "tcr: %#8.8ux\n", ctlr->tcr); 565 l += snprint(p+l, READSTR-l, "rcr: %#8.8ux\n", ctlr->rcr); 566 l += snprint(p+l, READSTR-l, "multicast: %ud\n", ctlr->mcast); 567 568 if(ctlr->mii != nil && ctlr->mii->curphy != nil){ 569 l += snprint(p+l, READSTR, "phy: "); 570 for(i = 0; i < NMiiPhyr; i++){ 571 if(i && ((i & 0x07) == 0)) 572 l += snprint(p+l, READSTR-l, "\n "); 573 r = miimir(ctlr->mii, i); 574 l += snprint(p+l, READSTR-l, " %4.4ux", r); 575 } 576 snprint(p+l, READSTR-l, "\n"); 577 } 578 579 n = readstr(offset, a, n, p); 580 581 qunlock(&ctlr->slock); 582 poperror(); 583 free(p); 584 585 return n; 586 } 587 588 static void 589 rtl8169halt(Ctlr* ctlr) 590 { 591 csr32w(ctlr, Timerint, 0); 592 csr8w(ctlr, Cr, 0); 593 csr16w(ctlr, Imr, 0); 594 csr16w(ctlr, Isr, ~0); 595 } 596 597 static int 598 rtl8169reset(Ctlr* ctlr) 599 { 600 u32int r; 601 int timeo; 602 603 /* 604 * Soft reset the controller. 605 */ 606 csr8w(ctlr, Cr, Rst); 607 for(r = timeo = 0; timeo < 1000; timeo++){ 608 r = csr8r(ctlr, Cr); 609 if(!(r & Rst)) 610 break; 611 delay(1); 612 } 613 rtl8169halt(ctlr); 614 615 if(r & Rst) 616 return -1; 617 return 0; 618 } 619 620 static void 621 rtl8169shutdown(Ether *ether) 622 { 623 rtl8169reset(ether->ctlr); 624 } 625 626 static void 627 rtl8169replenish(Ctlr* ctlr) 628 { 629 D *d; 630 int rdt; 631 Block *bp; 632 633 rdt = ctlr->rdt; 634 while(NEXT(rdt, ctlr->nrd) != ctlr->rdh){ 635 d = &ctlr->rd[rdt]; 636 if(ctlr->rb[rdt] == nil){ 637 /* 638 * Simple allocation for now. 639 * This better be aligned on 8. 640 */ 641 bp = iallocb(Mps); 642 if(bp == nil){ 643 iprint("no available buffers\n"); 644 break; 645 } 646 ctlr->rb[rdt] = bp; 647 d->addrlo = PCIWADDR(bp->rp); 648 d->addrhi = 0; 649 coherence(); 650 }else 651 iprint("i8169: rx overrun\n"); 652 d->control |= Own|Mps; 653 rdt = NEXT(rdt, ctlr->nrd); 654 ctlr->nrdfree++; 655 } 656 ctlr->rdt = rdt; 657 } 658 659 static int 660 rtl8169init(Ether* edev) 661 { 662 u32int r; 663 Ctlr *ctlr; 664 u8int cplusc; 665 666 ctlr = edev->ctlr; 667 ilock(&ctlr->ilock); 668 669 rtl8169reset(ctlr); 670 671 /* 672 * MAC Address is not settable on some (all?) chips. 673 * Must put chip into config register write enable mode. 674 */ 675 csr8w(ctlr, Cr9346, Eem1|Eem0); 676 677 /* 678 * Transmitter. 679 */ 680 memset(ctlr->td, 0, sizeof(D)*ctlr->ntd); 681 ctlr->tdh = ctlr->tdt = 0; 682 ctlr->td[ctlr->ntd-1].control = Eor; 683 684 /* 685 * Receiver. 686 * Need to do something here about the multicast filter. 687 */ 688 memset(ctlr->rd, 0, sizeof(D)*ctlr->nrd); 689 ctlr->nrdfree = ctlr->rdh = ctlr->rdt = 0; 690 ctlr->rd[ctlr->nrd-1].control = Eor; 691 692 rtl8169replenish(ctlr); 693 ctlr->rcr = Rxfthnone|Mrxdmaunlimited|Ab|Am|Apm; 694 695 /* 696 * Setting Mulrw in Cplusc disables the Tx/Rx DMA burst 697 * settings in Tcr/Rcr; the (1<<14) is magic. 698 */ 699 cplusc = csr16r(ctlr, Cplusc) & ~(1<<14); 700 cplusc |= /*Rxchksum|*/Mulrw; 701 switch(ctlr->macv){ 702 default: 703 panic("ether8169: unknown macv %#08ux for vid %#ux did %#ux", 704 ctlr->macv, ctlr->pcidev->vid, ctlr->pcidev->did); 705 case Macv01: 706 break; 707 case Macv02: 708 case Macv03: 709 cplusc |= 1<<14; /* magic */ 710 break; 711 case Macv05: 712 /* 713 * This is interpreted from clearly bogus code 714 * in the manufacturer-supplied driver, it could 715 * be wrong. Untested. 716 */ 717 r = csr8r(ctlr, Config2) & 0x07; 718 if(r == 0x01) /* 66MHz PCI */ 719 csr32w(ctlr, 0x7C, 0x0007FFFF); /* magic */ 720 else 721 csr32w(ctlr, 0x7C, 0x0007FF00); /* magic */ 722 pciclrmwi(ctlr->pcidev); 723 break; 724 case Macv13: 725 /* 726 * This is interpreted from clearly bogus code 727 * in the manufacturer-supplied driver, it could 728 * be wrong. Untested. 729 */ 730 pcicfgw8(ctlr->pcidev, 0x68, 0x00); /* magic */ 731 pcicfgw8(ctlr->pcidev, 0x69, 0x08); /* magic */ 732 break; 733 case Macv04: 734 case Macv07: 735 case Macv07a: 736 case Macv11: 737 case Macv12: 738 case Macv12a: 739 case Macv14: 740 case Macv15: 741 case Macv25: 742 case Macv2c: 743 case Macv34: 744 break; 745 } 746 747 /* 748 * Enable receiver/transmitter. 749 * Need to do this first or some of the settings below 750 * won't take. 751 */ 752 switch(ctlr->pciv){ 753 default: 754 csr8w(ctlr, Cr, Te|Re); 755 csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited); 756 csr32w(ctlr, Rcr, ctlr->rcr); 757 csr32w(ctlr, Mar0, 0); 758 csr32w(ctlr, Mar0+4, 0); 759 ctlr->mchash = 0; 760 case Rtl8169sc: 761 case Rtl8168b: 762 break; 763 } 764 765 /* 766 * Interrupts. 767 * Disable Tdu|Tok for now, the transmit routine will tidy. 768 * Tdu means the NIC ran out of descriptors to send, so it 769 * doesn't really need to ever be on. 770 */ 771 csr32w(ctlr, Timerint, 0); 772 ctlr->imr = Serr|Timeout|Fovw|Punlc|Rdu|Ter|Rer|Rok; 773 csr16w(ctlr, Imr, ctlr->imr); 774 775 /* 776 * Clear missed-packet counter; 777 * clear early transmit threshold value; 778 * set the descriptor ring base addresses; 779 * set the maximum receive packet size; 780 * no early-receive interrupts. 781 * 782 * note: the maximum rx size is a filter. the size of the buffer 783 * in the descriptor ring is still honored. we will toss >Mtu 784 * packets because they've been fragmented into multiple 785 * rx buffers. 786 */ 787 csr32w(ctlr, Mpc, 0); 788 csr8w(ctlr, Etx, 0x3f); /* magic */ 789 csr32w(ctlr, Tnpds+4, 0); 790 csr32w(ctlr, Tnpds, PCIWADDR(ctlr->td)); 791 csr32w(ctlr, Rdsar+4, 0); 792 csr32w(ctlr, Rdsar, PCIWADDR(ctlr->rd)); 793 csr16w(ctlr, Rms, 16383); /* was Mps; see above comment */ 794 r = csr16r(ctlr, Mulint) & 0xF000; /* no early rx interrupts */ 795 csr16w(ctlr, Mulint, r); 796 csr16w(ctlr, Cplusc, cplusc); 797 csr16w(ctlr, Coal, 0); 798 799 /* 800 * Set configuration. 801 */ 802 switch(ctlr->pciv){ 803 case Rtl8169sc: 804 csr8w(ctlr, Cr, Te|Re); 805 csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited); 806 csr32w(ctlr, Rcr, ctlr->rcr); 807 break; 808 case Rtl8168b: 809 case Rtl8169c: 810 csr16w(ctlr, Cplusc, 0x2000); /* magic */ 811 csr8w(ctlr, Cr, Te|Re); 812 csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited); 813 csr32w(ctlr, Rcr, ctlr->rcr); 814 break; 815 } 816 ctlr->tcr = csr32r(ctlr, Tcr); 817 csr8w(ctlr, Cr9346, 0); 818 819 iunlock(&ctlr->ilock); 820 821 // rtl8169mii(ctlr); 822 823 return 0; 824 } 825 826 static void 827 rtl8169attach(Ether* edev) 828 { 829 int timeo; 830 Ctlr *ctlr; 831 832 ctlr = edev->ctlr; 833 qlock(&ctlr->alock); 834 if(ctlr->init == 0){ 835 ctlr->td = mallocalign(sizeof(D)*Ntd, 256, 0, 0); 836 ctlr->tb = malloc(Ntd*sizeof(Block*)); 837 ctlr->ntd = Ntd; 838 ctlr->rd = mallocalign(sizeof(D)*Nrd, 256, 0, 0); 839 ctlr->rb = malloc(Nrd*sizeof(Block*)); 840 ctlr->nrd = Nrd; 841 ctlr->dtcc = mallocalign(sizeof(Dtcc), 64, 0, 0); 842 if(ctlr->td == nil || ctlr->tb == nil || ctlr->rd == nil || 843 ctlr->rb == nil || ctlr->dtcc == nil) { 844 free(ctlr->td); 845 free(ctlr->tb); 846 free(ctlr->rd); 847 free(ctlr->rb); 848 free(ctlr->dtcc); 849 qunlock(&ctlr->alock); 850 error(Enomem); 851 } 852 memset(ctlr->dtcc, 0, sizeof(Dtcc)); /* paranoia */ 853 rtl8169init(edev); 854 ctlr->init = 1; 855 } 856 qunlock(&ctlr->alock); 857 858 /* Don't wait long for link to be ready. */ 859 for(timeo = 0; timeo < 10; timeo++){ 860 if(miistatus(ctlr->mii) == 0) 861 break; 862 delay(100); /* print fewer miistatus messages */ 863 } 864 } 865 866 static void 867 rtl8169link(Ether* edev) 868 { 869 uint r; 870 int limit; 871 Ctlr *ctlr; 872 873 ctlr = edev->ctlr; 874 875 /* 876 * Maybe the link changed - do we care very much? 877 * Could stall transmits if no link, maybe? 878 */ 879 if(!((r = csr8r(ctlr, Phystatus)) & Linksts)){ 880 edev->link = 0; 881 return; 882 } 883 edev->link = 1; 884 885 limit = 256*1024; 886 if(r & Speed10){ 887 edev->mbps = 10; 888 limit = 65*1024; 889 } else if(r & Speed100) 890 edev->mbps = 100; 891 else if(r & Speed1000) 892 edev->mbps = 1000; 893 894 if(edev->oq != nil) 895 qsetlimit(edev->oq, limit); 896 } 897 898 static void 899 rtl8169transmit(Ether* edev) 900 { 901 D *d; 902 Block *bp; 903 Ctlr *ctlr; 904 int control, x; 905 906 ctlr = edev->ctlr; 907 908 ilock(&ctlr->tlock); 909 for(x = ctlr->tdh; ctlr->ntq > 0; x = NEXT(x, ctlr->ntd)){ 910 d = &ctlr->td[x]; 911 if((control = d->control) & Own) 912 break; 913 914 /* 915 * Check errors and log here. 916 */ 917 USED(control); 918 919 /* 920 * Free it up. 921 * Need to clean the descriptor here? Not really. 922 * Simple freeb for now (no chain and freeblist). 923 * Use ntq count for now. 924 */ 925 freeb(ctlr->tb[x]); 926 ctlr->tb[x] = nil; 927 d->control &= Eor; 928 929 ctlr->ntq--; 930 } 931 ctlr->tdh = x; 932 933 x = ctlr->tdt; 934 while(ctlr->ntq < (ctlr->ntd-1)){ 935 if((bp = qget(edev->oq)) == nil) 936 break; 937 938 d = &ctlr->td[x]; 939 d->addrlo = PCIWADDR(bp->rp); 940 d->addrhi = 0; 941 ctlr->tb[x] = bp; 942 coherence(); 943 d->control |= Own | Fs | Ls | BLEN(bp); 944 945 x = NEXT(x, ctlr->ntd); 946 ctlr->ntq++; 947 } 948 if(x != ctlr->tdt){ 949 ctlr->tdt = x; 950 csr8w(ctlr, Tppoll, Npq); 951 } 952 else if(ctlr->ntq >= (ctlr->ntd-1)) 953 ctlr->txdu++; 954 955 iunlock(&ctlr->tlock); 956 } 957 958 static void 959 rtl8169receive(Ether* edev) 960 { 961 D *d; 962 int rdh; 963 Block *bp; 964 Ctlr *ctlr; 965 u32int control; 966 967 ctlr = edev->ctlr; 968 969 rdh = ctlr->rdh; 970 for(;;){ 971 d = &ctlr->rd[rdh]; 972 973 if(d->control & Own) 974 break; 975 976 control = d->control; 977 if((control & (Fs|Ls|Res)) == (Fs|Ls)){ 978 bp = ctlr->rb[rdh]; 979 bp->wp = bp->rp + (control & RxflMASK) - 4; 980 981 if(control & Fovf) 982 ctlr->fovf++; 983 if(control & Mar) 984 ctlr->mcast++; 985 986 switch(control & (Pid1|Pid0)){ 987 default: 988 break; 989 case Pid0: 990 if(control & Tcpf){ 991 ctlr->tcpf++; 992 break; 993 } 994 bp->flag |= Btcpck; 995 break; 996 case Pid1: 997 if(control & Udpf){ 998 ctlr->udpf++; 999 break; 1000 } 1001 bp->flag |= Budpck; 1002 break; 1003 case Pid1|Pid0: 1004 if(control & Ipf){ 1005 ctlr->ipf++; 1006 break; 1007 } 1008 bp->flag |= Bipck; 1009 break; 1010 } 1011 etheriq(edev, bp, 1); 1012 }else{ 1013 if(!(control & Res)) 1014 ctlr->frag++; 1015 /* iprint("i8169: control %#.8ux\n", control); */ 1016 freeb(ctlr->rb[rdh]); 1017 } 1018 ctlr->rb[rdh] = nil; 1019 d->control &= Eor; 1020 ctlr->nrdfree--; 1021 rdh = NEXT(rdh, ctlr->nrd); 1022 1023 if(ctlr->nrdfree < ctlr->nrd/2) 1024 rtl8169replenish(ctlr); 1025 } 1026 ctlr->rdh = rdh; 1027 } 1028 1029 static void 1030 rtl8169interrupt(Ureg*, void* arg) 1031 { 1032 Ctlr *ctlr; 1033 Ether *edev; 1034 u32int isr; 1035 1036 edev = arg; 1037 ctlr = edev->ctlr; 1038 1039 while((isr = csr16r(ctlr, Isr)) != 0 && isr != 0xFFFF){ 1040 csr16w(ctlr, Isr, isr); 1041 if((isr & ctlr->imr) == 0) 1042 break; 1043 if(isr & (Fovw|Punlc|Rdu|Rer|Rok)){ 1044 rtl8169receive(edev); 1045 if(!(isr & (Punlc|Rok))) 1046 ctlr->ierrs++; 1047 if(isr & Rer) 1048 ctlr->rer++; 1049 if(isr & Rdu) 1050 ctlr->rdu++; 1051 if(isr & Punlc) 1052 ctlr->punlc++; 1053 if(isr & Fovw) 1054 ctlr->fovw++; 1055 isr &= ~(Fovw|Rdu|Rer|Rok); 1056 } 1057 1058 if(isr & (Tdu|Ter|Tok)){ 1059 rtl8169transmit(edev); 1060 isr &= ~(Tdu|Ter|Tok); 1061 } 1062 1063 if(isr & Punlc){ 1064 rtl8169link(edev); 1065 isr &= ~Punlc; 1066 } 1067 1068 /* 1069 * Some of the reserved bits get set sometimes... 1070 */ 1071 if(isr & (Serr|Timeout|Tdu|Fovw|Punlc|Rdu|Ter|Tok|Rer|Rok)) 1072 panic("rtl8169interrupt: imr %#4.4ux isr %#4.4ux", 1073 csr16r(ctlr, Imr), isr); 1074 } 1075 } 1076 1077 int 1078 vetmacv(Ctlr *ctlr, uint *macv) 1079 { 1080 *macv = csr32r(ctlr, Tcr) & HwveridMASK; 1081 switch(*macv){ 1082 default: 1083 return -1; 1084 case Macv01: 1085 case Macv02: 1086 case Macv03: 1087 case Macv04: 1088 case Macv05: 1089 case Macv07: 1090 case Macv07a: 1091 case Macv11: 1092 case Macv12: 1093 case Macv12a: 1094 case Macv13: 1095 case Macv14: 1096 case Macv15: 1097 case Macv25: 1098 case Macv2c: 1099 case Macv34: 1100 break; 1101 } 1102 return 0; 1103 } 1104 1105 static void 1106 rtl8169pci(void) 1107 { 1108 Pcidev *p; 1109 Ctlr *ctlr; 1110 int i, port, pcie; 1111 uint macv; 1112 1113 p = nil; 1114 while(p = pcimatch(p, 0, 0)){ 1115 if(p->ccrb != 0x02 || p->ccru != 0) 1116 continue; 1117 1118 pcie = 0; 1119 switch(i = ((p->did<<16)|p->vid)){ 1120 default: 1121 continue; 1122 case Rtl8100e: /* RTL810[01]E ? */ 1123 case Rtl8168b: /* RTL8168B */ 1124 pcie = 1; 1125 break; 1126 case Rtl8169c: /* RTL8169C */ 1127 case Rtl8169sc: /* RTL8169SC */ 1128 case Rtl8169: /* RTL8169 */ 1129 break; 1130 case (0xC107<<16)|0x1259: /* Corega CG-LAPCIGT */ 1131 i = Rtl8169; 1132 break; 1133 } 1134 1135 port = p->mem[0].bar & ~0x01; 1136 if(ioalloc(port, p->mem[0].size, 0, "rtl8169") < 0){ 1137 print("rtl8169: port %#ux in use\n", port); 1138 continue; 1139 } 1140 ctlr = malloc(sizeof(Ctlr)); 1141 if(ctlr == nil) 1142 error(Enomem); 1143 ctlr->port = port; 1144 ctlr->pcidev = p; 1145 ctlr->pciv = i; 1146 ctlr->pcie = pcie; 1147 1148 if(vetmacv(ctlr, &macv) == -1){ 1149 iofree(port); 1150 free(ctlr); 1151 print("rtl8169: unknown mac %.4ux %.8ux\n", p->did, macv); 1152 continue; 1153 } 1154 1155 if(pcigetpms(p) > 0){ 1156 pcisetpms(p, 0); 1157 1158 for(i = 0; i < 6; i++) 1159 pcicfgw32(p, PciBAR0+i*4, p->mem[i].bar); 1160 pcicfgw8(p, PciINTL, p->intl); 1161 pcicfgw8(p, PciLTR, p->ltr); 1162 pcicfgw8(p, PciCLS, p->cls); 1163 pcicfgw16(p, PciPCR, p->pcr); 1164 } 1165 1166 if(rtl8169reset(ctlr)){ 1167 iofree(port); 1168 free(ctlr); 1169 continue; 1170 } 1171 1172 /* 1173 * Extract the chip hardware version, 1174 * needed to configure each properly. 1175 */ 1176 ctlr->macv = macv; 1177 1178 rtl8169mii(ctlr); 1179 1180 pcisetbme(p); 1181 1182 if(rtl8169ctlrhead != nil) 1183 rtl8169ctlrtail->next = ctlr; 1184 else 1185 rtl8169ctlrhead = ctlr; 1186 rtl8169ctlrtail = ctlr; 1187 } 1188 } 1189 1190 static int 1191 rtl8169pnp(Ether* edev) 1192 { 1193 u32int r; 1194 Ctlr *ctlr; 1195 uchar ea[Eaddrlen]; 1196 static int once; 1197 1198 if(once == 0){ 1199 once = 1; 1200 rtl8169pci(); 1201 } 1202 1203 /* 1204 * Any adapter matches if no edev->port is supplied, 1205 * otherwise the ports must match. 1206 */ 1207 for(ctlr = rtl8169ctlrhead; ctlr != nil; ctlr = ctlr->next){ 1208 if(ctlr->active) 1209 continue; 1210 if(edev->port == 0 || edev->port == ctlr->port){ 1211 ctlr->active = 1; 1212 break; 1213 } 1214 } 1215 if(ctlr == nil) 1216 return -1; 1217 1218 edev->ctlr = ctlr; 1219 edev->port = ctlr->port; 1220 edev->irq = ctlr->pcidev->intl; 1221 edev->tbdf = ctlr->pcidev->tbdf; 1222 edev->mbps = 1000; 1223 edev->maxmtu = Mtu; 1224 1225 /* 1226 * Check if the adapter's station address is to be overridden. 1227 * If not, read it from the device and set in edev->ea. 1228 */ 1229 memset(ea, 0, Eaddrlen); 1230 if(memcmp(ea, edev->ea, Eaddrlen) == 0){ 1231 r = csr32r(ctlr, Idr0); 1232 edev->ea[0] = r; 1233 edev->ea[1] = r>>8; 1234 edev->ea[2] = r>>16; 1235 edev->ea[3] = r>>24; 1236 r = csr32r(ctlr, Idr0+4); 1237 edev->ea[4] = r; 1238 edev->ea[5] = r>>8; 1239 } 1240 1241 edev->attach = rtl8169attach; 1242 edev->transmit = rtl8169transmit; 1243 edev->interrupt = rtl8169interrupt; 1244 edev->ifstat = rtl8169ifstat; 1245 1246 edev->arg = edev; 1247 edev->promiscuous = rtl8169promiscuous; 1248 edev->multicast = rtl8169multicast; 1249 edev->shutdown = rtl8169shutdown; 1250 1251 rtl8169link(edev); 1252 1253 return 0; 1254 } 1255 1256 void 1257 ether8169link(void) 1258 { 1259 addethercard("rtl8169", rtl8169pnp); 1260 } 1261