1 /* 2 * Realtek 8139 (but not the 8129). 3 * Error recovery for the various over/under -flow conditions 4 * may need work. 5 */ 6 #include "u.h" 7 #include "../port/lib.h" 8 #include "mem.h" 9 #include "dat.h" 10 #include "fns.h" 11 #include "io.h" 12 #include "../port/error.h" 13 #include "../port/netif.h" 14 15 #include "etherif.h" 16 17 enum { /* registers */ 18 Idr0 = 0x0000, /* MAC address */ 19 Mar0 = 0x0008, /* Multicast address */ 20 Tsd0 = 0x0010, /* Transmit Status Descriptor0 */ 21 Tsad0 = 0x0020, /* Transmit Start Address Descriptor0 */ 22 Rbstart = 0x0030, /* Receive Buffer Start Address */ 23 Erbcr = 0x0034, /* Early Receive Byte Count */ 24 Ersr = 0x0036, /* Early Receive Status */ 25 Cr = 0x0037, /* Command Register */ 26 Capr = 0x0038, /* Current Address of Packet Read */ 27 Cbr = 0x003A, /* Current Buffer Address */ 28 Imr = 0x003C, /* Interrupt Mask */ 29 Isr = 0x003E, /* Interrupt Status */ 30 Tcr = 0x0040, /* Transmit Configuration */ 31 Rcr = 0x0044, /* Receive Configuration */ 32 Tctr = 0x0048, /* Timer Count */ 33 Mpc = 0x004C, /* Missed Packet Counter */ 34 Cr9346 = 0x0050, /* 9346 Command Register */ 35 Config0 = 0x0051, /* Configuration Register 0 */ 36 Config1 = 0x0052, /* Configuration Register 1 */ 37 TimerInt = 0x0054, /* Timer Interrupt */ 38 Msr = 0x0058, /* Media Status */ 39 Config3 = 0x0059, /* Configuration Register 3 */ 40 Config4 = 0x005A, /* Configuration Register 4 */ 41 Mulint = 0x005C, /* Multiple Interrupt Select */ 42 RerID = 0x005E, /* PCI Revision ID */ 43 Tsad = 0x0060, /* Transmit Status of all Descriptors */ 44 45 Bmcr = 0x0062, /* Basic Mode Control */ 46 Bmsr = 0x0064, /* Basic Mode Status */ 47 Anar = 0x0066, /* Auto-Negotiation Advertisment */ 48 Anlpar = 0x0068, /* Auto-Negotiation Link Partner */ 49 Aner = 0x006A, /* Auto-Negotiation Expansion */ 50 Dis = 0x006C, /* Disconnect Counter */ 51 Fcsc = 0x006E, /* False Carrier Sense Counter */ 52 Nwaytr = 0x0070, /* N-way Test */ 53 Rec = 0x0072, /* RX_ER Counter */ 54 Cscr = 0x0074, /* CS Configuration */ 55 Phy1parm = 0x0078, /* PHY Parameter 1 */ 56 Twparm = 0x007C, /* Twister Parameter */ 57 Phy2parm = 0x0080, /* PHY Parameter 2 */ 58 }; 59 60 enum { /* Cr */ 61 Bufe = 0x01, /* Rx Buffer Empty */ 62 Te = 0x04, /* Transmitter Enable */ 63 Re = 0x08, /* Receiver Enable */ 64 Rst = 0x10, /* Software Reset */ 65 }; 66 67 enum { /* Imr/Isr */ 68 Rok = 0x0001, /* Receive OK */ 69 Rer = 0x0002, /* Receive Error */ 70 Tok = 0x0004, /* Transmit OK */ 71 Ter = 0x0008, /* Transmit Error */ 72 Rxovw = 0x0010, /* Receive Buffer Overflow */ 73 PunLc = 0x0020, /* Packet Underrun or Link Change */ 74 Fovw = 0x0040, /* Receive FIFO Overflow */ 75 Clc = 0x2000, /* Cable Length Change */ 76 Timerbit = 0x4000, /* Timer */ 77 Serr = 0x8000, /* System Error */ 78 }; 79 80 enum { /* Tcr */ 81 Clrabt = 0x00000001, /* Clear Abort */ 82 TxrrSHIFT = 4, /* Transmit Retry Count */ 83 TxrrMASK = 0x000000F0, 84 MtxdmaSHIFT = 8, /* Max. DMA Burst Size */ 85 MtxdmaMASK = 0x00000700, 86 Mtxdma2048 = 0x00000700, 87 Acrc = 0x00010000, /* Append CRC (not) */ 88 LbkSHIFT = 17, /* Loopback Test */ 89 LbkMASK = 0x00060000, 90 Rtl8139ArevG = 0x00800000, /* RTL8139A Rev. G ID */ 91 IfgSHIFT = 24, /* Interframe Gap */ 92 IfgMASK = 0x03000000, 93 HwveridSHIFT = 26, /* Hardware Version ID */ 94 HwveridMASK = 0x7C000000, 95 }; 96 97 enum { /* Rcr */ 98 Aap = 0x00000001, /* Accept All Packets */ 99 Apm = 0x00000002, /* Accept Physical Match */ 100 Am = 0x00000004, /* Accept Multicast */ 101 Ab = 0x00000008, /* Accept Broadcast */ 102 Ar = 0x00000010, /* Accept Runt */ 103 Aer = 0x00000020, /* Accept Error */ 104 Sel9356 = 0x00000040, /* 9356 EEPROM used */ 105 Wrap = 0x00000080, /* Rx Buffer Wrap Control */ 106 MrxdmaSHIFT = 8, /* Max. DMA Burst Size */ 107 MrxdmaMASK = 0x00000700, 108 Mrxdmaunlimited = 0x00000700, 109 RblenSHIFT = 11, /* Receive Buffer Length */ 110 RblenMASK = 0x00001800, 111 Rblen8K = 0x00000000, /* 8KB+16 */ 112 Rblen16K = 0x00000800, /* 16KB+16 */ 113 Rblen32K = 0x00001000, /* 32KB+16 */ 114 Rblen64K = 0x00001800, /* 64KB+16 */ 115 RxfthSHIFT = 13, /* Receive Buffer Length */ 116 RxfthMASK = 0x0000E000, 117 Rxfth256 = 0x00008000, 118 Rxfthnone = 0x0000E000, 119 Rer8 = 0x00010000, /* Accept Error Packets > 8 bytes */ 120 MulERINT = 0x00020000, /* Multiple Early Interrupt Select */ 121 ErxthSHIFT = 24, /* Early Rx Threshold */ 122 ErxthMASK = 0x0F000000, 123 Erxthnone = 0x00000000, 124 }; 125 126 enum { /* Received Packet Status */ 127 Rcok = 0x0001, /* Receive Completed OK */ 128 Fae = 0x0002, /* Frame Alignment Error */ 129 Crc = 0x0004, /* CRC Error */ 130 Long = 0x0008, /* Long Packet */ 131 Runt = 0x0010, /* Runt Packet Received */ 132 Ise = 0x0020, /* Invalid Symbol Error */ 133 Bar = 0x2000, /* Broadcast Address Received */ 134 Pam = 0x4000, /* Physical Address Matched */ 135 Mar = 0x8000, /* Multicast Address Received */ 136 }; 137 138 enum { /* Media Status Register */ 139 Rxpf = 0x01, /* Pause Flag */ 140 Txpf = 0x02, /* Pause Flag */ 141 Linkb = 0x04, /* Inverse of Link Status */ 142 Speed10 = 0x08, /* 10Mbps */ 143 Auxstatus = 0x10, /* Aux. Power Present Status */ 144 Rxfce = 0x40, /* Receive Flow Control Enable */ 145 Txfce = 0x80, /* Transmit Flow Control Enable */ 146 }; 147 148 typedef struct Td Td; 149 struct Td { /* Soft Transmit Descriptor */ 150 int tsd; 151 int tsad; 152 uchar* data; 153 Block* bp; 154 }; 155 156 enum { /* Tsd0 */ 157 SizeSHIFT = 0, /* Descriptor Size */ 158 SizeMASK = 0x00001FFF, 159 Own = 0x00002000, 160 Tun = 0x00004000, /* Transmit FIFO Underrun */ 161 Tcok = 0x00008000, /* Transmit COmpleted OK */ 162 EtxthSHIFT = 16, /* Early Tx Threshold */ 163 EtxthMASK = 0x001F0000, 164 NccSHIFT = 24, /* Number of Collisions Count */ 165 NccMASK = 0x0F000000, 166 Cdh = 0x10000000, /* CD Heartbeat */ 167 Owc = 0x20000000, /* Out of Window Collision */ 168 Tabt = 0x40000000, /* Transmit Abort */ 169 Crs = 0x80000000, /* Carrier Sense Lost */ 170 }; 171 172 enum { 173 Rblen = Rblen64K, /* Receive Buffer Length */ 174 Ntd = 4, /* Number of Transmit Descriptors */ 175 Tdbsz = ROUNDUP(sizeof(Etherpkt), 4), 176 }; 177 178 typedef struct Ctlr Ctlr; 179 typedef struct Ctlr { 180 int port; 181 Pcidev* pcidev; 182 Ctlr* next; 183 int active; 184 int id; 185 186 QLock alock; /* attach */ 187 Lock ilock; /* init */ 188 void* alloc; /* base of per-Ctlr allocated data */ 189 190 int rcr; /* receive configuration register */ 191 uchar* rbstart; /* receive buffer */ 192 int rblen; /* receive buffer length */ 193 int ierrs; /* receive errors */ 194 195 Lock tlock; /* transmit */ 196 Td td[Ntd]; 197 int ntd; /* descriptors active */ 198 int tdh; /* host index into td */ 199 int tdi; /* interface index into td */ 200 int etxth; /* early transmit threshold */ 201 int taligned; /* packet required no alignment */ 202 int tunaligned; /* packet required alignment */ 203 204 int dis; /* disconnect counter */ 205 int fcsc; /* false carrier sense counter */ 206 int rec; /* RX_ER counter */ 207 } Ctlr; 208 209 static Ctlr* ctlrhead; 210 static Ctlr* ctlrtail; 211 212 #define csr8r(c, r) (inb((c)->port+(r))) 213 #define csr16r(c, r) (ins((c)->port+(r))) 214 #define csr32r(c, r) (inl((c)->port+(r))) 215 #define csr8w(c, r, b) (outb((c)->port+(r), (int)(b))) 216 #define csr16w(c, r, w) (outs((c)->port+(r), (ushort)(w))) 217 #define csr32w(c, r, l) (outl((c)->port+(r), (ulong)(l))) 218 219 static void 220 rtl8139promiscuous(void* arg, int on) 221 { 222 Ether *edev; 223 Ctlr * ctlr; 224 225 edev = arg; 226 ctlr = edev->ctlr; 227 ilock(&ctlr->ilock); 228 229 if(on) 230 ctlr->rcr |= Aap; 231 else 232 ctlr->rcr &= ~Aap; 233 csr32w(ctlr, Rcr, ctlr->rcr); 234 iunlock(&ctlr->ilock); 235 } 236 237 static void 238 rtl8139multicast(void* arg, uchar*, int) 239 { 240 rtl8139promiscuous(arg, 1); 241 } 242 243 static long 244 rtl8139ifstat(Ether* edev, void* a, long n, ulong offset) 245 { 246 int l; 247 char *p; 248 Ctlr *ctlr; 249 250 ctlr = edev->ctlr; 251 p = malloc(READSTR); 252 l = snprint(p, READSTR, "rcr %#8.8ux\n", ctlr->rcr); 253 l += snprint(p+l, READSTR-l, "ierrs %d\n", ctlr->ierrs); 254 l += snprint(p+l, READSTR-l, "etxth %d\n", ctlr->etxth); 255 l += snprint(p+l, READSTR-l, "taligned %d\n", ctlr->taligned); 256 l += snprint(p+l, READSTR-l, "tunaligned %d\n", ctlr->tunaligned); 257 ctlr->dis += csr16r(ctlr, Dis); 258 l += snprint(p+l, READSTR-l, "dis %d\n", ctlr->dis); 259 ctlr->fcsc += csr16r(ctlr, Fcsc); 260 l += snprint(p+l, READSTR-l, "fcscnt %d\n", ctlr->fcsc); 261 ctlr->rec += csr16r(ctlr, Rec); 262 l += snprint(p+l, READSTR-l, "rec %d\n", ctlr->rec); 263 264 l += snprint(p+l, READSTR-l, "Tcr %#8.8lux\n", csr32r(ctlr, Tcr)); 265 l += snprint(p+l, READSTR-l, "Config0 %#2.2ux\n", csr8r(ctlr, Config0)); 266 l += snprint(p+l, READSTR-l, "Config1 %#2.2ux\n", csr8r(ctlr, Config1)); 267 l += snprint(p+l, READSTR-l, "Msr %#2.2ux\n", csr8r(ctlr, Msr)); 268 l += snprint(p+l, READSTR-l, "Config3 %#2.2ux\n", csr8r(ctlr, Config3)); 269 l += snprint(p+l, READSTR-l, "Config4 %#2.2ux\n", csr8r(ctlr, Config4)); 270 271 l += snprint(p+l, READSTR-l, "Bmcr %#4.4ux\n", csr16r(ctlr, Bmcr)); 272 l += snprint(p+l, READSTR-l, "Bmsr %#4.4ux\n", csr16r(ctlr, Bmsr)); 273 l += snprint(p+l, READSTR-l, "Anar %#4.4ux\n", csr16r(ctlr, Anar)); 274 l += snprint(p+l, READSTR-l, "Anlpar %#4.4ux\n", csr16r(ctlr, Anlpar)); 275 l += snprint(p+l, READSTR-l, "Aner %#4.4ux\n", csr16r(ctlr, Aner)); 276 l += snprint(p+l, READSTR-l, "Nwaytr %#4.4ux\n", csr16r(ctlr, Nwaytr)); 277 snprint(p+l, READSTR-l, "Cscr %#4.4ux\n", csr16r(ctlr, Cscr)); 278 n = readstr(offset, a, n, p); 279 free(p); 280 281 return n; 282 } 283 284 static int 285 rtl8139reset(Ctlr* ctlr) 286 { 287 int timeo; 288 289 /* 290 * Soft reset the controller. 291 */ 292 csr8w(ctlr, Cr, Rst); 293 for(timeo = 0; timeo < 1000; timeo++){ 294 if(!(csr8r(ctlr, Cr) & Rst)) 295 return 0; 296 delay(1); 297 } 298 299 return -1; 300 } 301 302 static void 303 rtl8139halt(Ctlr* ctlr) 304 { 305 int i; 306 307 csr8w(ctlr, Cr, 0); 308 csr16w(ctlr, Imr, 0); 309 csr16w(ctlr, Isr, ~0); 310 311 for(i = 0; i < Ntd; i++){ 312 if(ctlr->td[i].bp == nil) 313 continue; 314 freeb(ctlr->td[i].bp); 315 ctlr->td[i].bp = nil; 316 } 317 } 318 319 static void 320 rtl8139init(Ether* edev) 321 { 322 int i; 323 ulong r; 324 Ctlr *ctlr; 325 uchar *alloc; 326 327 ctlr = edev->ctlr; 328 ilock(&ctlr->ilock); 329 330 rtl8139halt(ctlr); 331 332 /* 333 * MAC Address. 334 */ 335 r = (edev->ea[3]<<24)|(edev->ea[2]<<16)|(edev->ea[1]<<8)|edev->ea[0]; 336 csr32w(ctlr, Idr0, r); 337 r = (edev->ea[5]<<8)|edev->ea[4]; 338 csr32w(ctlr, Idr0+4, r); 339 340 /* 341 * Receiver 342 */ 343 alloc = (uchar*)ROUNDUP((ulong)ctlr->alloc, 32); 344 ctlr->rbstart = alloc; 345 alloc += ctlr->rblen+16; 346 memset(ctlr->rbstart, 0, ctlr->rblen+16); 347 csr32w(ctlr, Rbstart, PCIWADDR(ctlr->rbstart)); 348 ctlr->rcr = Rxfth256|Rblen|Mrxdmaunlimited|Ab|Apm; 349 350 /* 351 * Transmitter. 352 */ 353 for(i = 0; i < Ntd; i++){ 354 ctlr->td[i].tsd = Tsd0+i*4; 355 ctlr->td[i].tsad = Tsad0+i*4; 356 ctlr->td[i].data = alloc; 357 alloc += Tdbsz; 358 ctlr->td[i].bp = nil; 359 } 360 ctlr->ntd = ctlr->tdh = ctlr->tdi = 0; 361 ctlr->etxth = 128/32; 362 363 /* 364 * Interrupts. 365 */ 366 csr32w(ctlr, TimerInt, 0); 367 csr16w(ctlr, Imr, Serr|Timerbit|Fovw|PunLc|Rxovw|Ter|Tok|Rer|Rok); 368 csr32w(ctlr, Mpc, 0); 369 370 /* 371 * Enable receiver/transmitter. 372 * Need to enable before writing the Rcr or it won't take. 373 */ 374 csr8w(ctlr, Cr, Te|Re); 375 csr32w(ctlr, Tcr, Mtxdma2048); 376 csr32w(ctlr, Rcr, ctlr->rcr); 377 378 iunlock(&ctlr->ilock); 379 } 380 381 static void 382 rtl8139attach(Ether* edev) 383 { 384 Ctlr *ctlr; 385 386 ctlr = edev->ctlr; 387 qlock(&ctlr->alock); 388 if(ctlr->alloc == nil){ 389 ctlr->rblen = 1<<((Rblen>>RblenSHIFT)+13); 390 ctlr->alloc = mallocz(ctlr->rblen+16 + Ntd*Tdbsz + 32, 0); 391 rtl8139init(edev); 392 } 393 qunlock(&ctlr->alock); 394 } 395 396 static void 397 rtl8139txstart(Ether* edev) 398 { 399 Td *td; 400 int size; 401 Block *bp; 402 Ctlr *ctlr; 403 404 ctlr = edev->ctlr; 405 while(ctlr->ntd < Ntd){ 406 bp = qget(edev->oq); 407 if(bp == nil) 408 break; 409 size = BLEN(bp); 410 411 td = &ctlr->td[ctlr->tdh]; 412 if(((int)bp->rp) & 0x03){ 413 memmove(td->data, bp->rp, size); 414 freeb(bp); 415 csr32w(ctlr, td->tsad, PCIWADDR(td->data)); 416 ctlr->tunaligned++; 417 } 418 else{ 419 td->bp = bp; 420 csr32w(ctlr, td->tsad, PCIWADDR(bp->rp)); 421 ctlr->taligned++; 422 } 423 csr32w(ctlr, td->tsd, (ctlr->etxth<<EtxthSHIFT)|size); 424 425 ctlr->ntd++; 426 ctlr->tdh = NEXT(ctlr->tdh, Ntd); 427 } 428 } 429 430 static void 431 rtl8139transmit(Ether* edev) 432 { 433 Ctlr *ctlr; 434 435 ctlr = edev->ctlr; 436 ilock(&ctlr->tlock); 437 rtl8139txstart(edev); 438 iunlock(&ctlr->tlock); 439 } 440 441 static void 442 rtl8139receive(Ether* edev) 443 { 444 Block *bp; 445 Ctlr *ctlr; 446 ushort capr; 447 uchar cr, *p; 448 int l, length, status; 449 450 ctlr = edev->ctlr; 451 452 /* 453 * Capr is where the host is reading from, 454 * Cbr is where the NIC is currently writing. 455 */ 456 capr = (csr16r(ctlr, Capr)+16) % ctlr->rblen; 457 while(!(csr8r(ctlr, Cr) & Bufe)){ 458 p = ctlr->rbstart+capr; 459 460 /* 461 * Apparently the packet length may be 0xFFF0 if 462 * the NIC is still copying the packet into memory. 463 */ 464 length = (*(p+3)<<8)|*(p+2); 465 if(length == 0xFFF0) 466 break; 467 status = (*(p+1)<<8)|*p; 468 469 if(!(status & Rcok)){ 470 if(status & (Ise|Fae)) 471 edev->frames++; 472 if(status & Crc) 473 edev->crcs++; 474 if(status & (Runt|Long)) 475 edev->buffs++; 476 477 /* 478 * Reset the receiver. 479 * Also may have to restore the multicast list 480 * here too if it ever gets used. 481 */ 482 cr = csr8r(ctlr, Cr); 483 csr8w(ctlr, Cr, cr & ~Re); 484 csr32w(ctlr, Rbstart, PCIWADDR(ctlr->rbstart)); 485 csr8w(ctlr, Cr, cr); 486 csr32w(ctlr, Rcr, ctlr->rcr); 487 488 continue; 489 } 490 491 /* 492 * Receive Completed OK. 493 * Very simplistic; there are ways this could be done 494 * without copying, but the juice probably isn't worth 495 * the squeeze. 496 * The packet length includes a 4 byte CRC on the end. 497 */ 498 capr = (capr+4) % ctlr->rblen; 499 p = ctlr->rbstart+capr; 500 capr = (capr+length) % ctlr->rblen; 501 502 if((bp = iallocb(length)) != nil){ 503 if(p+length >= ctlr->rbstart+ctlr->rblen){ 504 l = ctlr->rbstart+ctlr->rblen - p; 505 memmove(bp->wp, p, l); 506 bp->wp += l; 507 length -= l; 508 p = ctlr->rbstart; 509 } 510 if(length > 0){ 511 memmove(bp->wp, p, length); 512 bp->wp += length; 513 } 514 bp->wp -= 4; 515 etheriq(edev, bp, 1); 516 } 517 518 capr = ROUNDUP(capr, 4); 519 csr16w(ctlr, Capr, capr-16); 520 } 521 } 522 523 static void 524 rtl8139interrupt(Ureg*, void* arg) 525 { 526 Td *td; 527 Ctlr *ctlr; 528 Ether *edev; 529 int isr, msr, tsd; 530 531 edev = arg; 532 ctlr = edev->ctlr; 533 534 while((isr = csr16r(ctlr, Isr)) != 0){ 535 csr16w(ctlr, Isr, isr); 536 if(isr & (Fovw|PunLc|Rxovw|Rer|Rok)){ 537 rtl8139receive(edev); 538 if(!(isr & Rok)) 539 ctlr->ierrs++; 540 isr &= ~(Fovw|Rxovw|Rer|Rok); 541 } 542 543 if(isr & (Ter|Tok)){ 544 ilock(&ctlr->tlock); 545 while(ctlr->ntd){ 546 td = &ctlr->td[ctlr->tdi]; 547 tsd = csr32r(ctlr, td->tsd); 548 if(!(tsd & (Tabt|Tun|Tcok))) 549 break; 550 551 if(!(tsd & Tcok)){ 552 if(tsd & Tun){ 553 if(ctlr->etxth < ETHERMAXTU/32) 554 ctlr->etxth++; 555 } 556 edev->oerrs++; 557 } 558 559 if(td->bp != nil){ 560 freeb(td->bp); 561 td->bp = nil; 562 } 563 564 ctlr->ntd--; 565 ctlr->tdi = NEXT(ctlr->tdi, Ntd); 566 } 567 rtl8139txstart(edev); 568 iunlock(&ctlr->tlock); 569 isr &= ~(Ter|Tok); 570 } 571 572 if(isr & PunLc){ 573 /* 574 * Maybe the link changed - do we care very much? 575 */ 576 msr = csr8r(ctlr, Msr); 577 if(!(msr & Linkb)){ 578 if(!(msr & Speed10) && edev->mbps != 100){ 579 edev->mbps = 100; 580 qsetlimit(edev->oq, 256*1024); 581 } 582 else if((msr & Speed10) && edev->mbps != 10){ 583 edev->mbps = 10; 584 qsetlimit(edev->oq, 65*1024); 585 } 586 } 587 isr &= ~(Clc|PunLc); 588 } 589 590 /* 591 * Only Serr|Timerbit should be left by now. 592 * Should anything be done to tidy up? TimerInt isn't 593 * used so that can be cleared. A PCI bus error is indicated 594 * by Serr, that's pretty serious; is there anyhing to do 595 * other than try to reinitialise the chip? 596 */ 597 if((isr & (Serr|Timerbit)) != 0){ 598 iprint("rtl8139interrupt: imr %#4.4ux isr %#4.4ux\n", 599 csr16r(ctlr, Imr), isr); 600 if(isr & Timerbit) 601 csr32w(ctlr, TimerInt, 0); 602 if(isr & Serr) 603 rtl8139init(edev); 604 } 605 } 606 } 607 608 static Ctlr* 609 rtl8139match(Ether* edev, int id) 610 { 611 Pcidev *p; 612 Ctlr *ctlr; 613 int i, port; 614 615 /* 616 * Any adapter matches if no edev->port is supplied, 617 * otherwise the ports must match. 618 */ 619 for(ctlr = ctlrhead; ctlr != nil; ctlr = ctlr->next){ 620 if(ctlr->active) 621 continue; 622 p = ctlr->pcidev; 623 if(((p->did<<16)|p->vid) != id) 624 continue; 625 port = p->mem[0].bar & ~0x01; 626 if(edev->port != 0 && edev->port != port) 627 continue; 628 629 if(ioalloc(port, p->mem[0].size, 0, "rtl8139") < 0){ 630 print("rtl8139: port %#ux in use\n", port); 631 continue; 632 } 633 634 if(pcigetpms(p) > 0){ 635 pcisetpms(p, 0); 636 637 for(i = 0; i < 6; i++) 638 pcicfgw32(p, PciBAR0+i*4, p->mem[i].bar); 639 pcicfgw8(p, PciINTL, p->intl); 640 pcicfgw8(p, PciLTR, p->ltr); 641 pcicfgw8(p, PciCLS, p->cls); 642 pcicfgw16(p, PciPCR, p->pcr); 643 } 644 645 ctlr->port = port; 646 if(rtl8139reset(ctlr)) { 647 iofree(port); 648 continue; 649 } 650 pcisetbme(p); 651 652 ctlr->active = 1; 653 return ctlr; 654 } 655 return nil; 656 } 657 658 static struct { 659 char* name; 660 int id; 661 } rtl8139pci[] = { 662 { "rtl8139", (0x8139<<16)|0x10EC, }, /* generic */ 663 { "smc1211", (0x1211<<16)|0x1113, }, /* SMC EZ-Card */ 664 { "dfe-538tx", (0x1300<<16)|0x1186, }, /* D-Link DFE-538TX */ 665 { "dfe-560txd", (0x1340<<16)|0x1186, }, /* D-Link DFE-560TXD */ 666 { nil }, 667 }; 668 669 static int 670 rtl8139pnp(Ether* edev) 671 { 672 int i, id; 673 Pcidev *p; 674 Ctlr *ctlr; 675 uchar ea[Eaddrlen]; 676 677 /* 678 * Make a list of all ethernet controllers 679 * if not already done. 680 */ 681 if(ctlrhead == nil){ 682 p = nil; 683 while(p = pcimatch(p, 0, 0)){ 684 if(p->ccrb != 0x02 || p->ccru != 0) 685 continue; 686 ctlr = malloc(sizeof(Ctlr)); 687 ctlr->pcidev = p; 688 ctlr->id = (p->did<<16)|p->vid; 689 690 if(ctlrhead != nil) 691 ctlrtail->next = ctlr; 692 else 693 ctlrhead = ctlr; 694 ctlrtail = ctlr; 695 } 696 } 697 698 /* 699 * Is it an RTL8139 under a different name? 700 * Normally a search is made through all the found controllers 701 * for one which matches any of the known vid+did pairs. 702 * If a vid+did pair is specified a search is made for that 703 * specific controller only. 704 */ 705 id = 0; 706 for(i = 0; i < edev->nopt; i++){ 707 if(cistrncmp(edev->opt[i], "id=", 3) == 0) 708 id = strtol(&edev->opt[i][3], nil, 0); 709 } 710 711 ctlr = nil; 712 if(id != 0) 713 ctlr = rtl8139match(edev, id); 714 else for(i = 0; rtl8139pci[i].name; i++){ 715 if((ctlr = rtl8139match(edev, rtl8139pci[i].id)) != nil) 716 break; 717 } 718 if(ctlr == nil) 719 return -1; 720 721 edev->ctlr = ctlr; 722 edev->port = ctlr->port; 723 edev->irq = ctlr->pcidev->intl; 724 edev->tbdf = ctlr->pcidev->tbdf; 725 726 /* 727 * Check if the adapter's station address is to be overridden. 728 * If not, read it from the device and set in edev->ea. 729 */ 730 memset(ea, 0, Eaddrlen); 731 if(memcmp(ea, edev->ea, Eaddrlen) == 0){ 732 i = csr32r(ctlr, Idr0); 733 edev->ea[0] = i; 734 edev->ea[1] = i>>8; 735 edev->ea[2] = i>>16; 736 edev->ea[3] = i>>24; 737 i = csr32r(ctlr, Idr0+4); 738 edev->ea[4] = i; 739 edev->ea[5] = i>>8; 740 } 741 742 edev->attach = rtl8139attach; 743 edev->transmit = rtl8139transmit; 744 edev->interrupt = rtl8139interrupt; 745 edev->ifstat = rtl8139ifstat; 746 747 edev->arg = edev; 748 edev->promiscuous = rtl8139promiscuous; 749 edev->multicast = rtl8139multicast; 750 // edev->shutdown = rtl8139shutdown; 751 752 /* 753 * This should be much more dynamic but will do for now. 754 */ 755 if((csr8r(ctlr, Msr) & (Speed10|Linkb)) == 0) 756 edev->mbps = 100; 757 758 return 0; 759 } 760 761 void 762 ether8139link(void) 763 { 764 addethercard("rtl8139", rtl8139pnp); 765 } 766