1 /*
2 * Realtek 8139 (but not the 8129).
3 * Error recovery for the various over/under -flow conditions
4 * may need work.
5 */
6 #include "u.h"
7 #include "../port/lib.h"
8 #include "mem.h"
9 #include "dat.h"
10 #include "fns.h"
11 #include "io.h"
12 #include "../port/error.h"
13 #include "../port/netif.h"
14
15 #include "etherif.h"
16
17 enum { /* registers */
18 Idr0 = 0x0000, /* MAC address */
19 Mar0 = 0x0008, /* Multicast address */
20 Tsd0 = 0x0010, /* Transmit Status Descriptor0 */
21 Tsad0 = 0x0020, /* Transmit Start Address Descriptor0 */
22 Rbstart = 0x0030, /* Receive Buffer Start Address */
23 Erbcr = 0x0034, /* Early Receive Byte Count */
24 Ersr = 0x0036, /* Early Receive Status */
25 Cr = 0x0037, /* Command Register */
26 Capr = 0x0038, /* Current Address of Packet Read */
27 Cbr = 0x003A, /* Current Buffer Address */
28 Imr = 0x003C, /* Interrupt Mask */
29 Isr = 0x003E, /* Interrupt Status */
30 Tcr = 0x0040, /* Transmit Configuration */
31 Rcr = 0x0044, /* Receive Configuration */
32 Tctr = 0x0048, /* Timer Count */
33 Mpc = 0x004C, /* Missed Packet Counter */
34 Cr9346 = 0x0050, /* 9346 Command Register */
35 Config0 = 0x0051, /* Configuration Register 0 */
36 Config1 = 0x0052, /* Configuration Register 1 */
37 TimerInt = 0x0054, /* Timer Interrupt */
38 Msr = 0x0058, /* Media Status */
39 Config3 = 0x0059, /* Configuration Register 3 */
40 Config4 = 0x005A, /* Configuration Register 4 */
41 Mulint = 0x005C, /* Multiple Interrupt Select */
42 RerID = 0x005E, /* PCI Revision ID */
43 Tsad = 0x0060, /* Transmit Status of all Descriptors */
44
45 Bmcr = 0x0062, /* Basic Mode Control */
46 Bmsr = 0x0064, /* Basic Mode Status */
47 Anar = 0x0066, /* Auto-Negotiation Advertisment */
48 Anlpar = 0x0068, /* Auto-Negotiation Link Partner */
49 Aner = 0x006A, /* Auto-Negotiation Expansion */
50 Dis = 0x006C, /* Disconnect Counter */
51 Fcsc = 0x006E, /* False Carrier Sense Counter */
52 Nwaytr = 0x0070, /* N-way Test */
53 Rec = 0x0072, /* RX_ER Counter */
54 Cscr = 0x0074, /* CS Configuration */
55 Phy1parm = 0x0078, /* PHY Parameter 1 */
56 Twparm = 0x007C, /* Twister Parameter */
57 Phy2parm = 0x0080, /* PHY Parameter 2 */
58 };
59
60 enum { /* Cr */
61 Bufe = 0x01, /* Rx Buffer Empty */
62 Te = 0x04, /* Transmitter Enable */
63 Re = 0x08, /* Receiver Enable */
64 Rst = 0x10, /* Software Reset */
65 };
66
67 enum { /* Imr/Isr */
68 Rok = 0x0001, /* Receive OK */
69 Rer = 0x0002, /* Receive Error */
70 Tok = 0x0004, /* Transmit OK */
71 Ter = 0x0008, /* Transmit Error */
72 Rxovw = 0x0010, /* Receive Buffer Overflow */
73 PunLc = 0x0020, /* Packet Underrun or Link Change */
74 Fovw = 0x0040, /* Receive FIFO Overflow */
75 Clc = 0x2000, /* Cable Length Change */
76 Timerbit = 0x4000, /* Timer */
77 Serr = 0x8000, /* System Error */
78 };
79
80 enum { /* Tcr */
81 Clrabt = 0x00000001, /* Clear Abort */
82 TxrrSHIFT = 4, /* Transmit Retry Count */
83 TxrrMASK = 0x000000F0,
84 MtxdmaSHIFT = 8, /* Max. DMA Burst Size */
85 MtxdmaMASK = 0x00000700,
86 Mtxdma2048 = 0x00000700,
87 Acrc = 0x00010000, /* Append CRC (not) */
88 LbkSHIFT = 17, /* Loopback Test */
89 LbkMASK = 0x00060000,
90 Rtl8139ArevG = 0x00800000, /* RTL8139A Rev. G ID */
91 IfgSHIFT = 24, /* Interframe Gap */
92 IfgMASK = 0x03000000,
93 HwveridSHIFT = 26, /* Hardware Version ID */
94 HwveridMASK = 0x7C000000,
95 };
96
97 enum { /* Rcr */
98 Aap = 0x00000001, /* Accept All Packets */
99 Apm = 0x00000002, /* Accept Physical Match */
100 Am = 0x00000004, /* Accept Multicast */
101 Ab = 0x00000008, /* Accept Broadcast */
102 Ar = 0x00000010, /* Accept Runt */
103 Aer = 0x00000020, /* Accept Error */
104 Sel9356 = 0x00000040, /* 9356 EEPROM used */
105 Wrap = 0x00000080, /* Rx Buffer Wrap Control */
106 MrxdmaSHIFT = 8, /* Max. DMA Burst Size */
107 MrxdmaMASK = 0x00000700,
108 Mrxdmaunlimited = 0x00000700,
109 RblenSHIFT = 11, /* Receive Buffer Length */
110 RblenMASK = 0x00001800,
111 Rblen8K = 0x00000000, /* 8KB+16 */
112 Rblen16K = 0x00000800, /* 16KB+16 */
113 Rblen32K = 0x00001000, /* 32KB+16 */
114 Rblen64K = 0x00001800, /* 64KB+16 */
115 RxfthSHIFT = 13, /* Receive Buffer Length */
116 RxfthMASK = 0x0000E000,
117 Rxfth256 = 0x00008000,
118 Rxfthnone = 0x0000E000,
119 Rer8 = 0x00010000, /* Accept Error Packets > 8 bytes */
120 MulERINT = 0x00020000, /* Multiple Early Interrupt Select */
121 ErxthSHIFT = 24, /* Early Rx Threshold */
122 ErxthMASK = 0x0F000000,
123 Erxthnone = 0x00000000,
124 };
125
126 enum { /* Received Packet Status */
127 Rcok = 0x0001, /* Receive Completed OK */
128 Fae = 0x0002, /* Frame Alignment Error */
129 Crc = 0x0004, /* CRC Error */
130 Long = 0x0008, /* Long Packet */
131 Runt = 0x0010, /* Runt Packet Received */
132 Ise = 0x0020, /* Invalid Symbol Error */
133 Bar = 0x2000, /* Broadcast Address Received */
134 Pam = 0x4000, /* Physical Address Matched */
135 Mar = 0x8000, /* Multicast Address Received */
136 };
137
138 enum { /* Media Status Register */
139 Rxpf = 0x01, /* Pause Flag */
140 Txpf = 0x02, /* Pause Flag */
141 Linkb = 0x04, /* Inverse of Link Status */
142 Speed10 = 0x08, /* 10Mbps */
143 Auxstatus = 0x10, /* Aux. Power Present Status */
144 Rxfce = 0x40, /* Receive Flow Control Enable */
145 Txfce = 0x80, /* Transmit Flow Control Enable */
146 };
147
148 typedef struct Td Td;
149 struct Td { /* Soft Transmit Descriptor */
150 int tsd;
151 int tsad;
152 uchar* data;
153 Block* bp;
154 };
155
156 enum { /* Tsd0 */
157 SizeSHIFT = 0, /* Descriptor Size */
158 SizeMASK = 0x00001FFF,
159 Own = 0x00002000,
160 Tun = 0x00004000, /* Transmit FIFO Underrun */
161 Tcok = 0x00008000, /* Transmit COmpleted OK */
162 EtxthSHIFT = 16, /* Early Tx Threshold */
163 EtxthMASK = 0x001F0000,
164 NccSHIFT = 24, /* Number of Collisions Count */
165 NccMASK = 0x0F000000,
166 Cdh = 0x10000000, /* CD Heartbeat */
167 Owc = 0x20000000, /* Out of Window Collision */
168 Tabt = 0x40000000, /* Transmit Abort */
169 Crs = 0x80000000, /* Carrier Sense Lost */
170 };
171
172 enum {
173 Rblen = Rblen64K, /* Receive Buffer Length */
174 Ntd = 4, /* Number of Transmit Descriptors */
175 Tdbsz = ROUNDUP(sizeof(Etherpkt), 4),
176 };
177
178 typedef struct Ctlr Ctlr;
179 typedef struct Ctlr {
180 int port;
181 Pcidev* pcidev;
182 Ctlr* next;
183 int active;
184 int id;
185
186 QLock alock; /* attach */
187 Lock ilock; /* init */
188 void* alloc; /* base of per-Ctlr allocated data */
189
190 int pcie; /* flag: pci-express device? */
191
192 uvlong mchash; /* multicast hash */
193
194 int rcr; /* receive configuration register */
195 uchar* rbstart; /* receive buffer */
196 int rblen; /* receive buffer length */
197 int ierrs; /* receive errors */
198
199 Lock tlock; /* transmit */
200 Td td[Ntd];
201 int ntd; /* descriptors active */
202 int tdh; /* host index into td */
203 int tdi; /* interface index into td */
204 int etxth; /* early transmit threshold */
205 int taligned; /* packet required no alignment */
206 int tunaligned; /* packet required alignment */
207
208 int dis; /* disconnect counter */
209 int fcsc; /* false carrier sense counter */
210 int rec; /* RX_ER counter */
211 uint mcast;
212 } Ctlr;
213
214 static Ctlr* ctlrhead;
215 static Ctlr* ctlrtail;
216
217 #define csr8r(c, r) (inb((c)->port+(r)))
218 #define csr16r(c, r) (ins((c)->port+(r)))
219 #define csr32r(c, r) (inl((c)->port+(r)))
220 #define csr8w(c, r, b) (outb((c)->port+(r), (int)(b)))
221 #define csr16w(c, r, w) (outs((c)->port+(r), (ushort)(w)))
222 #define csr32w(c, r, l) (outl((c)->port+(r), (ulong)(l)))
223
224 static void
rtl8139promiscuous(void * arg,int on)225 rtl8139promiscuous(void* arg, int on)
226 {
227 Ether *edev;
228 Ctlr * ctlr;
229
230 edev = arg;
231 ctlr = edev->ctlr;
232 ilock(&ctlr->ilock);
233
234 if(on)
235 ctlr->rcr |= Aap;
236 else
237 ctlr->rcr &= ~Aap;
238 csr32w(ctlr, Rcr, ctlr->rcr);
239 iunlock(&ctlr->ilock);
240 }
241
242 enum {
243 /* everyone else uses 0x04c11db7, but they both produce the same crc */
244 Etherpolybe = 0x04c11db6,
245 Bytemask = (1<<8) - 1,
246 };
247
248 static ulong
ethercrcbe(uchar * addr,long len)249 ethercrcbe(uchar *addr, long len)
250 {
251 int i, j;
252 ulong c, crc, carry;
253
254 crc = ~0UL;
255 for (i = 0; i < len; i++) {
256 c = addr[i];
257 for (j = 0; j < 8; j++) {
258 carry = ((crc & (1UL << 31))? 1: 0) ^ (c & 1);
259 crc <<= 1;
260 c >>= 1;
261 if (carry)
262 crc = (crc ^ Etherpolybe) | carry;
263 }
264 }
265 return crc;
266 }
267
268 static ulong
swabl(ulong l)269 swabl(ulong l)
270 {
271 return l>>24 | (l>>8) & (Bytemask<<8) |
272 (l<<8) & (Bytemask<<16) | l<<24;
273 }
274
275 static void
rtl8139multicast(void * ether,uchar * eaddr,int add)276 rtl8139multicast(void* ether, uchar *eaddr, int add)
277 {
278 Ether *edev;
279 Ctlr *ctlr;
280
281 if (!add)
282 return; /* ok to keep receiving on old mcast addrs */
283
284 edev = ether;
285 ctlr = edev->ctlr;
286 ilock(&ctlr->ilock);
287
288 ctlr->mchash |= 1ULL << (ethercrcbe(eaddr, Eaddrlen) >> 26);
289
290 ctlr->rcr |= Am;
291 csr32w(ctlr, Rcr, ctlr->rcr);
292
293 /* pci-e variants reverse the order of the hash byte registers */
294 if (0 && ctlr->pcie) {
295 csr32w(ctlr, Mar0, swabl(ctlr->mchash>>32));
296 csr32w(ctlr, Mar0+4, swabl(ctlr->mchash));
297 } else {
298 csr32w(ctlr, Mar0, ctlr->mchash);
299 csr32w(ctlr, Mar0+4, ctlr->mchash>>32);
300 }
301
302 iunlock(&ctlr->ilock);
303 }
304
305 static long
rtl8139ifstat(Ether * edev,void * a,long n,ulong offset)306 rtl8139ifstat(Ether* edev, void* a, long n, ulong offset)
307 {
308 int l;
309 char *p;
310 Ctlr *ctlr;
311
312 ctlr = edev->ctlr;
313 p = malloc(READSTR);
314 if(p == nil)
315 error(Enomem);
316 l = snprint(p, READSTR, "rcr %#8.8ux\n", ctlr->rcr);
317 l += snprint(p+l, READSTR-l, "multicast %ud\n", ctlr->mcast);
318 l += snprint(p+l, READSTR-l, "ierrs %d\n", ctlr->ierrs);
319 l += snprint(p+l, READSTR-l, "etxth %d\n", ctlr->etxth);
320 l += snprint(p+l, READSTR-l, "taligned %d\n", ctlr->taligned);
321 l += snprint(p+l, READSTR-l, "tunaligned %d\n", ctlr->tunaligned);
322 ctlr->dis += csr16r(ctlr, Dis);
323 l += snprint(p+l, READSTR-l, "dis %d\n", ctlr->dis);
324 ctlr->fcsc += csr16r(ctlr, Fcsc);
325 l += snprint(p+l, READSTR-l, "fcscnt %d\n", ctlr->fcsc);
326 ctlr->rec += csr16r(ctlr, Rec);
327 l += snprint(p+l, READSTR-l, "rec %d\n", ctlr->rec);
328
329 l += snprint(p+l, READSTR-l, "Tcr %#8.8lux\n", csr32r(ctlr, Tcr));
330 l += snprint(p+l, READSTR-l, "Config0 %#2.2ux\n", csr8r(ctlr, Config0));
331 l += snprint(p+l, READSTR-l, "Config1 %#2.2ux\n", csr8r(ctlr, Config1));
332 l += snprint(p+l, READSTR-l, "Msr %#2.2ux\n", csr8r(ctlr, Msr));
333 l += snprint(p+l, READSTR-l, "Config3 %#2.2ux\n", csr8r(ctlr, Config3));
334 l += snprint(p+l, READSTR-l, "Config4 %#2.2ux\n", csr8r(ctlr, Config4));
335
336 l += snprint(p+l, READSTR-l, "Bmcr %#4.4ux\n", csr16r(ctlr, Bmcr));
337 l += snprint(p+l, READSTR-l, "Bmsr %#4.4ux\n", csr16r(ctlr, Bmsr));
338 l += snprint(p+l, READSTR-l, "Anar %#4.4ux\n", csr16r(ctlr, Anar));
339 l += snprint(p+l, READSTR-l, "Anlpar %#4.4ux\n", csr16r(ctlr, Anlpar));
340 l += snprint(p+l, READSTR-l, "Aner %#4.4ux\n", csr16r(ctlr, Aner));
341 l += snprint(p+l, READSTR-l, "Nwaytr %#4.4ux\n", csr16r(ctlr, Nwaytr));
342 snprint(p+l, READSTR-l, "Cscr %#4.4ux\n", csr16r(ctlr, Cscr));
343 n = readstr(offset, a, n, p);
344 free(p);
345
346 return n;
347 }
348
349 static int
rtl8139reset(Ctlr * ctlr)350 rtl8139reset(Ctlr* ctlr)
351 {
352 int timeo;
353
354 /* stop interrupts */
355 csr16w(ctlr, Imr, 0);
356 csr16w(ctlr, Isr, ~0);
357 csr32w(ctlr, TimerInt, 0);
358
359 /*
360 * Soft reset the controller.
361 */
362 csr8w(ctlr, Cr, Rst);
363 for(timeo = 0; timeo < 1000; timeo++){
364 if(!(csr8r(ctlr, Cr) & Rst))
365 return 0;
366 delay(1);
367 }
368
369 return -1;
370 }
371
372 static void
rtl8139halt(Ctlr * ctlr)373 rtl8139halt(Ctlr* ctlr)
374 {
375 int i;
376
377 csr8w(ctlr, Cr, 0);
378 csr16w(ctlr, Imr, 0);
379 csr16w(ctlr, Isr, ~0);
380 csr32w(ctlr, TimerInt, 0);
381
382 for(i = 0; i < Ntd; i++){
383 if(ctlr->td[i].bp == nil)
384 continue;
385 freeb(ctlr->td[i].bp);
386 ctlr->td[i].bp = nil;
387 }
388 }
389
390 static void
rtl8139shutdown(Ether * edev)391 rtl8139shutdown(Ether *edev)
392 {
393 Ctlr *ctlr;
394
395 ctlr = edev->ctlr;
396 ilock(&ctlr->ilock);
397 rtl8139halt(ctlr);
398 rtl8139reset(ctlr);
399 iunlock(&ctlr->ilock);
400 }
401
402 static void
rtl8139init(Ether * edev)403 rtl8139init(Ether* edev)
404 {
405 int i;
406 ulong r;
407 Ctlr *ctlr;
408 uchar *alloc;
409
410 ctlr = edev->ctlr;
411 ilock(&ctlr->ilock);
412
413 rtl8139halt(ctlr);
414
415 /*
416 * MAC Address.
417 */
418 r = (edev->ea[3]<<24)|(edev->ea[2]<<16)|(edev->ea[1]<<8)|edev->ea[0];
419 csr32w(ctlr, Idr0, r);
420 r = (edev->ea[5]<<8)|edev->ea[4];
421 csr32w(ctlr, Idr0+4, r);
422
423 /*
424 * Receiver
425 */
426 alloc = (uchar*)ROUNDUP((ulong)ctlr->alloc, 32);
427 ctlr->rbstart = alloc;
428 alloc += ctlr->rblen+16;
429 memset(ctlr->rbstart, 0, ctlr->rblen+16);
430 csr32w(ctlr, Rbstart, PCIWADDR(ctlr->rbstart));
431 ctlr->rcr = Rxfth256|Rblen|Mrxdmaunlimited|Ab|Am|Apm;
432
433 /*
434 * Transmitter.
435 */
436 for(i = 0; i < Ntd; i++){
437 ctlr->td[i].tsd = Tsd0+i*4;
438 ctlr->td[i].tsad = Tsad0+i*4;
439 ctlr->td[i].data = alloc;
440 alloc += Tdbsz;
441 ctlr->td[i].bp = nil;
442 }
443 ctlr->ntd = ctlr->tdh = ctlr->tdi = 0;
444 ctlr->etxth = 128/32;
445
446 /*
447 * Enable receiver/transmitter.
448 * Need to enable before writing the Rcr or it won't take.
449 */
450 csr8w(ctlr, Cr, Te|Re);
451 csr32w(ctlr, Tcr, Mtxdma2048);
452 csr32w(ctlr, Rcr, ctlr->rcr);
453 csr32w(ctlr, Mar0, 0);
454 csr32w(ctlr, Mar0+4, 0);
455 ctlr->mchash = 0;
456
457 /*
458 * Interrupts.
459 */
460 csr32w(ctlr, TimerInt, 0);
461 csr16w(ctlr, Imr, Serr|Timerbit|Fovw|PunLc|Rxovw|Ter|Tok|Rer|Rok);
462 csr32w(ctlr, Mpc, 0);
463
464 iunlock(&ctlr->ilock);
465 }
466
467 static void
rtl8139attach(Ether * edev)468 rtl8139attach(Ether* edev)
469 {
470 Ctlr *ctlr;
471
472 if(edev == nil) {
473 print("rtl8139attach: nil edev\n");
474 return;
475 }
476 ctlr = edev->ctlr;
477 if(ctlr == nil) {
478 print("rtl8139attach: nil ctlr for Ether %#p\n", edev);
479 return;
480 }
481 qlock(&ctlr->alock);
482 if(ctlr->alloc == nil){
483 ctlr->rblen = 1<<((Rblen>>RblenSHIFT)+13);
484 ctlr->alloc = malloc(ctlr->rblen+16 + Ntd*Tdbsz + 32);
485 if(ctlr->alloc == nil) {
486 qunlock(&ctlr->alock);
487 error(Enomem);
488 }
489 rtl8139init(edev);
490 }
491 qunlock(&ctlr->alock);
492 }
493
494 static void
rtl8139txstart(Ether * edev)495 rtl8139txstart(Ether* edev)
496 {
497 Td *td;
498 int size;
499 Block *bp;
500 Ctlr *ctlr;
501
502 ctlr = edev->ctlr;
503 while(ctlr->ntd < Ntd){
504 bp = qget(edev->oq);
505 if(bp == nil)
506 break;
507 size = BLEN(bp);
508
509 td = &ctlr->td[ctlr->tdh];
510 if(((int)bp->rp) & 0x03){
511 memmove(td->data, bp->rp, size);
512 freeb(bp);
513 csr32w(ctlr, td->tsad, PCIWADDR(td->data));
514 ctlr->tunaligned++;
515 }
516 else{
517 td->bp = bp;
518 csr32w(ctlr, td->tsad, PCIWADDR(bp->rp));
519 ctlr->taligned++;
520 }
521 csr32w(ctlr, td->tsd, (ctlr->etxth<<EtxthSHIFT)|size);
522
523 ctlr->ntd++;
524 ctlr->tdh = NEXT(ctlr->tdh, Ntd);
525 }
526 }
527
528 static void
rtl8139transmit(Ether * edev)529 rtl8139transmit(Ether* edev)
530 {
531 Ctlr *ctlr;
532
533 ctlr = edev->ctlr;
534 ilock(&ctlr->tlock);
535 rtl8139txstart(edev);
536 iunlock(&ctlr->tlock);
537 }
538
539 static void
rtl8139receive(Ether * edev)540 rtl8139receive(Ether* edev)
541 {
542 Block *bp;
543 Ctlr *ctlr;
544 ushort capr;
545 uchar cr, *p;
546 int l, length, status;
547
548 ctlr = edev->ctlr;
549
550 /*
551 * Capr is where the host is reading from,
552 * Cbr is where the NIC is currently writing.
553 */
554 if(ctlr->rblen == 0)
555 return; /* not attached yet (shouldn't happen) */
556 capr = (csr16r(ctlr, Capr)+16) % ctlr->rblen;
557 while(!(csr8r(ctlr, Cr) & Bufe)){
558 p = ctlr->rbstart+capr;
559
560 /*
561 * Apparently the packet length may be 0xFFF0 if
562 * the NIC is still copying the packet into memory.
563 */
564 length = (*(p+3)<<8)|*(p+2);
565 if(length == 0xFFF0)
566 break;
567 status = (*(p+1)<<8)|*p;
568
569 if(!(status & Rcok)){
570 if(status & (Ise|Fae))
571 edev->frames++;
572 if(status & Crc)
573 edev->crcs++;
574 if(status & (Runt|Long))
575 edev->buffs++;
576
577 /*
578 * Reset the receiver.
579 * Also may have to restore the multicast list
580 * here too if it ever gets used.
581 */
582 cr = csr8r(ctlr, Cr);
583 csr8w(ctlr, Cr, cr & ~Re);
584 csr32w(ctlr, Rbstart, PCIWADDR(ctlr->rbstart));
585 csr8w(ctlr, Cr, cr);
586 csr32w(ctlr, Rcr, ctlr->rcr);
587
588 continue;
589 }
590
591 /*
592 * Receive Completed OK.
593 * Very simplistic; there are ways this could be done
594 * without copying, but the juice probably isn't worth
595 * the squeeze.
596 * The packet length includes a 4 byte CRC on the end.
597 */
598 capr = (capr+4) % ctlr->rblen;
599 p = ctlr->rbstart+capr;
600 capr = (capr+length) % ctlr->rblen;
601 if(status & Mar)
602 ctlr->mcast++;
603
604 if((bp = iallocb(length)) != nil){
605 if(p+length >= ctlr->rbstart+ctlr->rblen){
606 l = ctlr->rbstart+ctlr->rblen - p;
607 memmove(bp->wp, p, l);
608 bp->wp += l;
609 length -= l;
610 p = ctlr->rbstart;
611 }
612 if(length > 0){
613 memmove(bp->wp, p, length);
614 bp->wp += length;
615 }
616 bp->wp -= 4;
617 etheriq(edev, bp, 1);
618 }
619
620 capr = ROUNDUP(capr, 4);
621 csr16w(ctlr, Capr, capr-16);
622 }
623 }
624
625 static void
rtl8139interrupt(Ureg *,void * arg)626 rtl8139interrupt(Ureg*, void* arg)
627 {
628 Td *td;
629 Ctlr *ctlr;
630 Ether *edev;
631 int isr, msr, tsd;
632
633 edev = arg;
634 ctlr = edev->ctlr;
635 if(ctlr == nil) { /* not attached yet? (shouldn't happen) */
636 print("rtl8139interrupt: interrupt for unattached Ether %#p\n",
637 edev);
638 return;
639 }
640
641 while((isr = csr16r(ctlr, Isr)) != 0){
642 csr16w(ctlr, Isr, isr);
643 if(ctlr->alloc == nil) {
644 print("rtl8139interrupt: interrupt for unattached Ctlr "
645 "%#p port %#p\n", ctlr, (void *)ctlr->port);
646 return; /* not attached yet (shouldn't happen) */
647 }
648 if(isr & (Fovw|PunLc|Rxovw|Rer|Rok)){
649 rtl8139receive(edev);
650 if(!(isr & Rok))
651 ctlr->ierrs++;
652 isr &= ~(Fovw|Rxovw|Rer|Rok);
653 }
654
655 if(isr & (Ter|Tok)){
656 ilock(&ctlr->tlock);
657 while(ctlr->ntd){
658 td = &ctlr->td[ctlr->tdi];
659 tsd = csr32r(ctlr, td->tsd);
660 if(!(tsd & (Tabt|Tun|Tcok)))
661 break;
662
663 if(!(tsd & Tcok)){
664 if(tsd & Tun){
665 if(ctlr->etxth < ETHERMAXTU/32)
666 ctlr->etxth++;
667 }
668 edev->oerrs++;
669 }
670
671 if(td->bp != nil){
672 freeb(td->bp);
673 td->bp = nil;
674 }
675
676 ctlr->ntd--;
677 ctlr->tdi = NEXT(ctlr->tdi, Ntd);
678 }
679 rtl8139txstart(edev);
680 iunlock(&ctlr->tlock);
681 isr &= ~(Ter|Tok);
682 }
683
684 if(isr & PunLc){
685 /*
686 * Maybe the link changed - do we care very much?
687 */
688 msr = csr8r(ctlr, Msr);
689 if(!(msr & Linkb)){
690 if(!(msr & Speed10) && edev->mbps != 100){
691 edev->mbps = 100;
692 qsetlimit(edev->oq, 256*1024);
693 }
694 else if((msr & Speed10) && edev->mbps != 10){
695 edev->mbps = 10;
696 qsetlimit(edev->oq, 65*1024);
697 }
698 }
699 isr &= ~(Clc|PunLc);
700 }
701
702 /*
703 * Only Serr|Timerbit should be left by now.
704 * Should anything be done to tidy up? TimerInt isn't
705 * used so that can be cleared. A PCI bus error is indicated
706 * by Serr, that's pretty serious; is there anyhing to do
707 * other than try to reinitialise the chip?
708 */
709 if((isr & (Serr|Timerbit)) != 0){
710 iprint("rtl8139interrupt: imr %#4.4ux isr %#4.4ux\n",
711 csr16r(ctlr, Imr), isr);
712 if(isr & Timerbit)
713 csr32w(ctlr, TimerInt, 0);
714 if(isr & Serr)
715 rtl8139init(edev);
716 }
717 }
718 }
719
720 static Ctlr*
rtl8139match(Ether * edev,int id)721 rtl8139match(Ether* edev, int id)
722 {
723 Pcidev *p;
724 Ctlr *ctlr;
725 int i, port;
726
727 /*
728 * Any adapter matches if no edev->port is supplied,
729 * otherwise the ports must match.
730 */
731 for(ctlr = ctlrhead; ctlr != nil; ctlr = ctlr->next){
732 if(ctlr->active)
733 continue;
734 p = ctlr->pcidev;
735 if(((p->did<<16)|p->vid) != id)
736 continue;
737 port = p->mem[0].bar & ~0x01;
738 if(edev->port != 0 && edev->port != port)
739 continue;
740
741 if(ioalloc(port, p->mem[0].size, 0, "rtl8139") < 0){
742 print("rtl8139: port %#ux in use\n", port);
743 continue;
744 }
745
746 if(pcigetpms(p) > 0){
747 pcisetpms(p, 0);
748
749 for(i = 0; i < 6; i++)
750 pcicfgw32(p, PciBAR0+i*4, p->mem[i].bar);
751 pcicfgw8(p, PciINTL, p->intl);
752 pcicfgw8(p, PciLTR, p->ltr);
753 pcicfgw8(p, PciCLS, p->cls);
754 pcicfgw16(p, PciPCR, p->pcr);
755 }
756
757 ctlr->port = port;
758 if(rtl8139reset(ctlr)) {
759 iofree(port);
760 continue;
761 }
762 pcisetbme(p);
763
764 ctlr->active = 1;
765 return ctlr;
766 }
767 return nil;
768 }
769
770 static struct {
771 char* name;
772 int id;
773 } rtl8139pci[] = {
774 { "rtl8139", (0x8139<<16)|0x10EC, }, /* generic */
775 { "smc1211", (0x1211<<16)|0x1113, }, /* SMC EZ-Card */
776 { "dfe-538tx", (0x1300<<16)|0x1186, }, /* D-Link DFE-538TX */
777 { "dfe-560txd", (0x1340<<16)|0x1186, }, /* D-Link DFE-560TXD */
778 { nil },
779 };
780
781 static int
rtl8139pnp(Ether * edev)782 rtl8139pnp(Ether* edev)
783 {
784 int i, id;
785 Pcidev *p;
786 Ctlr *ctlr;
787 uchar ea[Eaddrlen];
788
789 /*
790 * Make a list of all ethernet controllers
791 * if not already done.
792 */
793 if(ctlrhead == nil){
794 p = nil;
795 while(p = pcimatch(p, 0, 0)){
796 if(p->ccrb != 0x02 || p->ccru != 0)
797 continue;
798 ctlr = malloc(sizeof(Ctlr));
799 if(ctlr == nil)
800 error(Enomem);
801 ctlr->pcidev = p;
802 ctlr->id = (p->did<<16)|p->vid;
803
804 if(ctlrhead != nil)
805 ctlrtail->next = ctlr;
806 else
807 ctlrhead = ctlr;
808 ctlrtail = ctlr;
809 }
810 }
811
812 /*
813 * Is it an RTL8139 under a different name?
814 * Normally a search is made through all the found controllers
815 * for one which matches any of the known vid+did pairs.
816 * If a vid+did pair is specified a search is made for that
817 * specific controller only.
818 */
819 id = 0;
820 for(i = 0; i < edev->nopt; i++){
821 if(cistrncmp(edev->opt[i], "id=", 3) == 0)
822 id = strtol(&edev->opt[i][3], nil, 0);
823 }
824
825 ctlr = nil;
826 if(id != 0)
827 ctlr = rtl8139match(edev, id);
828 else for(i = 0; rtl8139pci[i].name; i++){
829 if((ctlr = rtl8139match(edev, rtl8139pci[i].id)) != nil)
830 break;
831 }
832 if(ctlr == nil)
833 return -1;
834
835 edev->ctlr = ctlr;
836 edev->port = ctlr->port;
837 edev->irq = ctlr->pcidev->intl;
838 edev->tbdf = ctlr->pcidev->tbdf;
839
840 /*
841 * Check if the adapter's station address is to be overridden.
842 * If not, read it from the device and set in edev->ea.
843 */
844 memset(ea, 0, Eaddrlen);
845 if(memcmp(ea, edev->ea, Eaddrlen) == 0){
846 i = csr32r(ctlr, Idr0);
847 edev->ea[0] = i;
848 edev->ea[1] = i>>8;
849 edev->ea[2] = i>>16;
850 edev->ea[3] = i>>24;
851 i = csr32r(ctlr, Idr0+4);
852 edev->ea[4] = i;
853 edev->ea[5] = i>>8;
854 }
855
856 edev->arg = edev;
857 edev->attach = rtl8139attach;
858 edev->transmit = rtl8139transmit;
859 edev->interrupt = rtl8139interrupt;
860 edev->ifstat = rtl8139ifstat;
861
862 edev->promiscuous = rtl8139promiscuous;
863 edev->multicast = rtl8139multicast;
864 edev->shutdown = rtl8139shutdown;
865
866 /*
867 * This should be much more dynamic but will do for now.
868 */
869 if((csr8r(ctlr, Msr) & (Speed10|Linkb)) == 0)
870 edev->mbps = 100;
871
872 return 0;
873 }
874
875 void
ether8139link(void)876 ether8139link(void)
877 {
878 addethercard("rtl8139", rtl8139pnp);
879 }
880