1 typedef struct BIOS32si BIOS32si; 2 typedef struct BIOS32ci BIOS32ci; 3 typedef struct Conf Conf; 4 typedef struct Confmem Confmem; 5 typedef union FPsave FPsave; 6 typedef struct FPssestate FPssestate; 7 typedef struct FPstate FPstate; 8 typedef struct ISAConf ISAConf; 9 typedef struct Label Label; 10 typedef struct Lock Lock; 11 typedef struct MMU MMU; 12 typedef struct Mach Mach; 13 typedef struct Notsave Notsave; 14 typedef struct PCArch PCArch; 15 typedef struct Pcidev Pcidev; 16 typedef struct PCMmap PCMmap; 17 typedef struct PCMslot PCMslot; 18 typedef struct Page Page; 19 typedef struct PMMU PMMU; 20 typedef struct Proc Proc; 21 typedef struct Segdesc Segdesc; 22 typedef struct SFPssestate SFPssestate; 23 typedef vlong Tval; 24 typedef struct Ureg Ureg; 25 typedef struct Vctl Vctl; 26 27 #pragma incomplete BIOS32si 28 #pragma incomplete Pcidev 29 #pragma incomplete Ureg 30 31 #define MAXSYSARG 5 /* for mount(fd, afd, mpt, flag, arg) */ 32 33 #define KMESGSIZE (256*1024) /* lots, for acpi debugging */ 34 #define STAGESIZE 2048 35 36 /* 37 * parameters for sysproc.c 38 */ 39 #define AOUT_MAGIC (I_MAGIC) 40 41 struct Lock 42 { 43 ulong key; 44 ulong sr; 45 ulong pc; 46 Proc *p; 47 Mach *m; 48 ushort isilock; 49 long lockcycles; 50 }; 51 52 struct Label 53 { 54 ulong sp; 55 ulong pc; 56 }; 57 58 59 /* 60 * FPsave.status 61 */ 62 enum 63 { 64 /* this is a state */ 65 FPinit= 0, 66 FPactive= 1, 67 FPinactive= 2, 68 69 /* the following is a bit that can be or'd into the state */ 70 FPillegal= 0x100, 71 }; 72 73 struct FPstate /* x87 fpu state */ 74 { 75 ushort control; 76 ushort r1; 77 ushort status; 78 ushort r2; 79 ushort tag; 80 ushort r3; 81 ulong pc; 82 ushort selector; 83 ushort r4; 84 ulong operand; 85 ushort oselector; 86 ushort r5; 87 uchar regs[80]; /* floating point registers */ 88 }; 89 90 struct FPssestate /* SSE fp state */ 91 { 92 ushort fcw; /* control */ 93 ushort fsw; /* status */ 94 ushort ftw; /* tag */ 95 ushort fop; /* opcode */ 96 ulong fpuip; /* pc */ 97 ushort cs; /* pc segment */ 98 ushort r1; /* reserved */ 99 ulong fpudp; /* data pointer */ 100 ushort ds; /* data pointer segment */ 101 ushort r2; 102 ulong mxcsr; /* MXCSR register state */ 103 ulong mxcsr_mask; /* MXCSR mask register */ 104 uchar xregs[480]; /* extended registers */ 105 }; 106 107 struct SFPssestate /* SSE fp state with alignment slop */ 108 { 109 FPssestate; 110 uchar alignpad[FPalign]; /* slop to allow copying to aligned addr */ 111 ulong magic; /* debugging: check for overrun */ 112 }; 113 114 /* 115 * the FP regs must be stored here, not somewhere pointed to from here. 116 * port code assumes this. 117 */ 118 union FPsave { 119 FPstate; 120 SFPssestate; 121 }; 122 123 struct Confmem 124 { 125 ulong base; 126 ulong npage; 127 ulong kbase; 128 ulong klimit; 129 }; 130 131 struct Conf 132 { 133 ulong nmach; /* processors */ 134 ulong nproc; /* processes */ 135 ulong monitor; /* has monitor? */ 136 Confmem mem[4]; /* physical memory */ 137 ulong npage; /* total physical pages of memory */ 138 ulong upages; /* user page pool */ 139 ulong nimage; /* number of page cache image headers */ 140 ulong nswap; /* number of swap pages */ 141 int nswppo; /* max # of pageouts per segment pass */ 142 ulong base0; /* base of bank 0 */ 143 ulong base1; /* base of bank 1 */ 144 ulong copymode; /* 0 is copy on write, 1 is copy on reference */ 145 ulong ialloc; /* max interrupt time allocation in bytes */ 146 ulong pipeqsize; /* size in bytes of pipe queues */ 147 int nuart; /* number of uart devices */ 148 }; 149 150 /* 151 * MMU stuff in proc 152 */ 153 #define NCOLOR 1 154 struct PMMU 155 { 156 Page* mmupdb; /* page directory base */ 157 Page* mmufree; /* unused page table pages */ 158 Page* mmuused; /* used page table pages */ 159 Page* kmaptable; /* page table used by kmap */ 160 uint lastkmap; /* last entry used by kmap */ 161 int nkmap; /* number of current kmaps */ 162 }; 163 164 /* 165 * things saved in the Proc structure during a notify 166 */ 167 struct Notsave 168 { 169 ulong svflags; 170 ulong svcs; 171 ulong svss; 172 }; 173 174 #include "../port/portdat.h" 175 176 typedef struct { 177 ulong link; /* link (old TSS selector) */ 178 ulong esp0; /* privilege level 0 stack pointer */ 179 ulong ss0; /* privilege level 0 stack selector */ 180 ulong esp1; /* privilege level 1 stack pointer */ 181 ulong ss1; /* privilege level 1 stack selector */ 182 ulong esp2; /* privilege level 2 stack pointer */ 183 ulong ss2; /* privilege level 2 stack selector */ 184 ulong xcr3; /* page directory base register - not used because we don't use trap gates */ 185 ulong eip; /* instruction pointer */ 186 ulong eflags; /* flags register */ 187 ulong eax; /* general registers */ 188 ulong ecx; 189 ulong edx; 190 ulong ebx; 191 ulong esp; 192 ulong ebp; 193 ulong esi; 194 ulong edi; 195 ulong es; /* segment selectors */ 196 ulong cs; 197 ulong ss; 198 ulong ds; 199 ulong fs; 200 ulong gs; 201 ulong ldt; /* selector for task's LDT */ 202 ulong iomap; /* I/O map base address + T-bit */ 203 } Tss; 204 205 struct Segdesc 206 { 207 ulong d0; 208 ulong d1; 209 }; 210 211 struct Mach 212 { 213 int machno; /* physical id of processor (KNOWN TO ASSEMBLY) */ 214 ulong splpc; /* pc of last caller to splhi */ 215 216 ulong* pdb; /* page directory base for this processor (va) */ 217 Tss* tss; /* tss for this processor */ 218 Segdesc *gdt; /* gdt for this processor */ 219 220 Proc* proc; /* current process on this processor */ 221 Proc* externup; /* extern register Proc *up */ 222 223 Page* pdbpool; 224 int pdbcnt; 225 226 ulong ticks; /* of the clock since boot time */ 227 Label sched; /* scheduler wakeup */ 228 Lock alarmlock; /* access to alarm list */ 229 void* alarm; /* alarms bound to this clock */ 230 int inclockintr; 231 232 Proc* readied; /* for runproc */ 233 ulong schedticks; /* next forced context switch */ 234 235 int tlbfault; 236 int tlbpurge; 237 int pfault; 238 int cs; 239 int syscall; 240 int load; 241 int intr; 242 int flushmmu; /* make current proc flush it's mmu state */ 243 int ilockdepth; 244 Perf perf; /* performance counters */ 245 246 ulong spuriousintr; 247 int lastintr; 248 249 int loopconst; 250 251 Lock apictimerlock; 252 int cpumhz; 253 uvlong cyclefreq; /* Frequency of user readable cycle counter */ 254 uvlong cpuhz; 255 int cpuidax; 256 int cpuiddx; 257 char cpuidid[16]; 258 char* cpuidtype; 259 int havetsc; 260 int havepge; 261 uvlong tscticks; 262 int pdballoc; 263 int pdbfree; 264 FPsave *fpsavalign; 265 266 vlong mtrrcap; 267 vlong mtrrdef; 268 vlong mtrrfix[11]; 269 vlong mtrrvar[32]; /* 256 max. */ 270 271 int stack[1]; 272 }; 273 274 /* 275 * KMap the structure doesn't exist, but the functions do. 276 */ 277 typedef struct KMap KMap; 278 #define VA(k) ((void*)(k)) 279 KMap* kmap(Page*); 280 void kunmap(KMap*); 281 282 struct 283 { 284 Lock; 285 int machs; /* bitmap of active CPUs */ 286 int exiting; /* shutdown */ 287 int ispanic; /* shutdown in response to a panic */ 288 int thunderbirdsarego; /* lets the added processors continue to schedinit */ 289 int rebooting; /* just idle cpus > 0 */ 290 }active; 291 292 /* 293 * routines for things outside the PC model, like power management 294 */ 295 struct PCArch 296 { 297 char* id; 298 int (*ident)(void); /* this should be in the model */ 299 void (*reset)(void); /* this should be in the model */ 300 int (*serialpower)(int); /* 1 == on, 0 == off */ 301 int (*modempower)(int); /* 1 == on, 0 == off */ 302 303 void (*intrinit)(void); 304 int (*intrenable)(Vctl*); 305 int (*intrvecno)(int); 306 int (*intrdisable)(int); 307 void (*introff)(void); 308 void (*intron)(void); 309 310 void (*clockenable)(void); 311 uvlong (*fastclock)(uvlong*); 312 void (*timerset)(uvlong); 313 314 void (*resetothers)(void); /* put other cpus into reset */ 315 }; 316 317 /* cpuid instruction result register bits */ 318 enum { 319 /* dx */ 320 Fpuonchip = 1<<0, 321 Vmex = 1<<1, /* virtual-mode extensions */ 322 Pse = 1<<3, /* page size extensions */ 323 Tsc = 1<<4, /* time-stamp counter */ 324 Cpumsr = 1<<5, /* model-specific registers, rdmsr/wrmsr */ 325 Pae = 1<<6, /* physical-addr extensions */ 326 Mce = 1<<7, /* machine-check exception */ 327 Cmpxchg8b = 1<<8, 328 Cpuapic = 1<<9, 329 Mtrr = 1<<12, /* memory-type range regs. */ 330 Pge = 1<<13, /* page global extension */ 331 Pse2 = 1<<17, /* more page size extensions */ 332 Clflush = 1<<19, 333 Mmx = 1<<23, 334 Fxsr = 1<<24, /* have SSE FXSAVE/FXRSTOR */ 335 Sse = 1<<25, /* thus sfence instr. */ 336 Sse2 = 1<<26, /* thus mfence & lfence instr.s */ 337 }; 338 339 /* 340 * a parsed plan9.ini line 341 */ 342 #define NISAOPT 8 343 344 struct ISAConf { 345 char *type; 346 ulong port; 347 int irq; 348 ulong dma; 349 ulong mem; 350 ulong size; 351 ulong freq; 352 353 int nopt; 354 char *opt[NISAOPT]; 355 }; 356 357 extern PCArch *arch; /* PC architecture */ 358 359 /* 360 * Each processor sees its own Mach structure at address MACHADDR. 361 * However, the Mach structures must also be available via the per-processor 362 * MMU information array machp, mainly for disambiguation and access to 363 * the clock which is only maintained by the bootstrap processor (0). 364 */ 365 Mach* machp[MAXMACH]; 366 367 #define MACHP(n) (machp[n]) 368 369 extern Mach *m; 370 #define up (((Mach*)MACHADDR)->externup) 371 372 /* 373 * hardware info about a device 374 */ 375 typedef struct { 376 ulong port; 377 int size; 378 } Devport; 379 380 struct DevConf 381 { 382 ulong intnum; /* interrupt number */ 383 char *type; /* card type, malloced */ 384 int nports; /* Number of ports */ 385 Devport *ports; /* The ports themselves */ 386 }; 387 388 typedef struct BIOS32ci { /* BIOS32 Calling Interface */ 389 u32int eax; 390 u32int ebx; 391 u32int ecx; 392 u32int edx; 393 u32int esi; 394 u32int edi; 395 } BIOS32ci; 396