1beagleboard rev c3: 2cortex-a8 cpu: arm v7-a arch. rev 3, 500MHz, dual-issue 3OMAP3530-GP rev 2, CPU-OPP2 L3-165MHz 4OMAP3 Beagle board + LPDDR/NAND 5DRAM: 256 MB 6NAND: 256 MiB 7Board revision C 8Serial #784200230000000004013f790401d018 9 10igepv2 board: 11cortex-a8 cpu: arm v7-a arch. rev 3, 720MHz, dual-issue 12OMAP3530-GP ES3.1, CPU-OPP2 L3-165MHz 13IGEP v2.x rev. B + LPDDR/ONENAND 14DRAM: 512 MB 15Muxed OneNAND(DDP) 512MB 1.8V 16-bit (0x58) 16OneNAND version = 0x0031 17Chip support all block unlock 18Chip has 2 plane 19Scanning device for bad blocks 20Bad eraseblock 3134 at 0x187c0000 21Bad eraseblock 3135 at 0x187e0000 22OneNAND: 512 MB 23 24omap3530 SoC 25CORE_CLK runs at 26MHz 26see spruf98d from ti.com (/public/doc/ti/omap35x.ref.spruf98d.pdf) 27 28separate i & d tlbs, each 32 entries 29 can invalidate i, d or both tlbs by { all, mva, or asid match } 30 31i & d L1 caches, 16K each, 4 ways, 64 sets, 64-byte lines 32 i is VIPT, d is PIPT 33 no `test and clean D & U all' operations 34 no prefetching, no cache maintenance 35 can invalidate i, d or both cache but not D & U all 36 can invalidate entire i-cache only 37 can clean or invalidate by set and way data/unified cache 38unified L2 PIPT cache, 256K, 8 ways, 512 sets, 64-byte lines 39no hardware cache coherence 40 41l3 interconnect firewalls are all off at boot time, except for a bit of 42 secure ram 43sram at 0x40200000 size 1MB 44l4 interconnect firewalls seem to be sane at boot time 45 46___ 47The state of the Beagleboard/IGEPv2 (TI OMAP35 SoC, Cortex-A8) port. 48 49Plan 9 runs on the IGEPv2 and Gumstix Overo boards. 50 51On the Beagleboard, Plan 9 is not yet usable but it gets as far as 52trying to access the USB ethernet (since the Beagleboard has no 53built-in ethernet and must use USB ethernet). 54 55IGEP & Gumstix Ethernet 56 57The smsc9221 ethernet consumes a lot of system time. The design 58decision to use fifos rather than buffer rings and to not incorporate 59dma into the ethernet controller is probably responsible. With only a 60single core, running the 9221 consumes a lot of the available CPU 61time. It's probably worth trying to use the system dma controller again. 62 63USB 64 65The ohci and ehci controllers are seen, but no devices yet. 66 67There are four USB errata that need to be looked into for the igepv2 68(silicon 3.1) at least. From the omap3530 errata (rev e): 69 70- 3.1.1.130 only one usb dma channel (rx or tx) can be active 71 at one time: use interrupt mode instead 72- 3.1.1.144 otg soft reset doesn't work right 73- 3.1.1.183 ohci and ehci controllers cannot work concurrently 74- §3.1.3 usb limitations: all ports must be configured to identical speeds 75 (high vs full/low) 76 77Flash 78 79access to nand flash would be handy for nvram and paqfs file systems. 80 81In the flash, x-loader occupies up to 0x20000, then u-boot from 820x80000 to 0x1e0000, and there's a linux kernel after that (if you 83care). The beagle's flash chip is a micron pop 2Gb nand 84mt29f2g16abdhc-et (physical marking jw256), and the igep's is a 85samsung onenand. 86 87VFPv3 Floating Point 88 89The Cortex-A8 has VFPv3 floating point, which uses different opcodes 90than 5c/5l currently generate. New 5c or 5l is in the works. 91 92Video 93 94The display subsystem for omap3 (dss) is divided into 3 parts, called lcd, 95video and dsi (ignoring the various accelerators). The system only 96supports the lcd via dvi interface so far because it's the only one we 97have been able to test. 1280x1024x16 is the default resolution, this 98might be changed. Writing to /dev/dssctl (e.g., echo 1024x768x16 99>/dev/dssctl) changes the resolution. Currently the system does not 100use the rfbi since it seems like an unnecessary optimisation at this 101point. Per Odlund wrote the first draft of the video driver for a 102Google Summer of Code project. 103 104Stray Interrupts 105 106IRQs 56 and 57 are I2C. 83, 86 and 94 are MMC. 107 108___ 109 110The code is fairly heavy-handed with the use of barrier instructions 111(BARRIERS in assembler, coherence in C), partly in reaction to bad 112experience doing Power PC ports, but also just as precautions against 113modern processors, which may feel free to execute instructions out of 114order or some time later, store to memory out of order or some time 115later, otherwise break the model of traditional sequential processors, 116or any combination of the above. 117___ 118 119There are a few rough edges: 120 121- the clock.c scheduling rate (HZ) is quite approximate. The OMAP 122timers are complex, but one could eventually do better (or just let 123timesync compensate). 124 125- User processes are limited to 512MB virtual (mainly by the IGEPv2 Ethernet 126being at 0x2c000000), which isn't a problem since Beagleboards only 127have 256MB of dram and IGEPv2s have 512MB, and we don't want to swap. 128 129- might use ucalloc.c to allocate uncached scratch space for generated code 130in coproc.c. 131 132- the C implementation of cache primitives failed with mmu off; still true? 133 134- unlock, setup: protect module register target APE (PM_RT) per spruf98c §1.6.7 135 136- setup mpp (multi-purpose pins)? 137 138___ 139 memory map (mostly from omap35x ref) 140hex addr size what 141---- 1420 16MB physical address of flash registers, buffers 14320000000 16MB virtual address of flash registers, buffers 1442c000000 ? smc 9221 ethernet 14538000000 16MB 256MB (beagle) or 512MB (igep) nand flash mapped here 146 14740000000 112K boot rom, top of user space 14840200000 64K sram 149 15048000000 16MB L4 core 15148002000 8K system control (scm) 15248004000 16K clock manager 15348040000 8K L4-core config 15448050000 4K graphics 15548062000 4K usb tll 15648064000 1K usb uhh_config 15748064400 1K ohci 15848064800 1K ehci 1594806a000 8K 8250 uart0 1604806c000 8K 8250 uart1 16148086000 4K gptimer10 16248088000 4K gptimer11 1634809c000 8K mmc/sd goo 164480ab000 8K hs usb otg 165480ad000 8K mmc/sd goo 166480b4000 8K mmc/sd goo 167480c7000 device intr controller 16848200000 2K intr ctlr (intc) 169 17048300000 256K L4-wakeup 17148304000 4K gptimer12 17248318000 8K gptimer1 173 17449000000 1MB L4 peripherals 17549020000 8K 8250 uart2 (with exposed connector for console) 17649032000 4K gptimer2 17749034000 4K gptimer3 178⋯ 17949040000 4K gptimer9 18049050000 8K gpio2 181⋯ 18249058000 8K gpio6 183 18450000000 64K graphics accelerator 185 18668000000 1K L3 config (rt) 18768004000 1K L3 hs usb host 18868004400 1K L3 hs usb otg 18968005400 1K L3 graphics 19068006800 1K L4-core config 19168010000 L3 protection mechanism 192 1936e000000 ? gpmc 194 19580000000 256MB dram on beagle 196 512MB dram on igep 197 198c0000000 1GB kernel virtual space, mapped to 80000000 199 200apparently the vector address (0 or 0xffff0000) is virtual, 201so we're expected to map it to ram. 202