1 /* 2 * Memory and machine-specific definitions. Used in C and assembler. 3 */ 4 #define KiB 1024u /* Kibi 0x0000000000000400 */ 5 #define MiB 1048576u /* Mebi 0x0000000000100000 */ 6 #define GiB 1073741824u /* Gibi 000000000040000000 */ 7 8 /* 9 * Not sure where these macros should go. 10 * This probably isn't right but will do for now. 11 * The macro names are problematic too. 12 */ 13 /* 14 * In BITN(o), 'o' is the bit offset in the register. 15 * For multi-bit fields use F(v, o, w) where 'v' is the value 16 * of the bit-field of width 'w' with LSb at bit offset 'o'. 17 */ 18 #define BITN(o) (1<<(o)) 19 #define F(v, o, w) (((v) & ((1<<(w))-1))<<(o)) 20 21 /* 22 * Sizes 23 */ 24 #define BY2PG (4*KiB) /* bytes per page */ 25 #define PGSHIFT 12 /* log(BY2PG) */ 26 27 #define MAXMACH 1 /* max # cpus system can run */ 28 #define MACHSIZE BY2PG 29 30 #define KSTKSIZE (16*KiB) /* was 8K */ 31 #define STACKALIGN(sp) ((sp) & ~3) /* bug: assure with alloc */ 32 33 /* 34 * Address spaces. 35 * KTZERO is used by kprof and dumpstack (if any). 36 * 37 * KZERO (0xc0000000) is mapped to physical 0x80000000 (start of dram). 38 * u-boot claims to occupy the first 3 MB of dram, but we're willing to 39 * step on it once we're loaded. Expect plan9.ini in the first 64K past 3MB. 40 * 41 * L2 PTEs are stored in 1K before Mach (11K to 12K above KZERO). 42 * cpu0's Mach struct is at L1 - MACHSIZE(4K) to L1 (12K to 16K above KZERO). 43 * L1 PTEs are stored from L1 to L1+32K (16K to 48K above KZERO). 44 * KTZERO may be anywhere after that (but probably shouldn't collide with 45 * u-boot). 46 * This should leave over 8K from KZERO to L2 PTEs. 47 */ 48 #define KSEG0 0xC0000000 /* kernel segment */ 49 /* mask to check segment; good for 512MB dram */ 50 #define KSEGM 0xE0000000 51 #define KZERO KSEG0 /* kernel address space */ 52 #define L1 (KZERO+16*KiB) /* tt ptes: 16KiB aligned */ 53 #define CONFADDR (KZERO+0x300000) /* unparsed plan9.ini */ 54 /* KTZERO must match loadaddr in mkfile */ 55 #define KTZERO (KZERO+0x310000) /* kernel text start */ 56 57 #define UZERO 0 /* user segment */ 58 #define UTZERO (UZERO+BY2PG) /* user text start */ 59 #define UTROUND(t) ROUNDUP((t), BY2PG) 60 /* moved USTKTOP down to 512MB to keep MMIO space out of user space. */ 61 #define USTKTOP 0x20000000 /* user segment end +1 */ 62 #define USTKSIZE (8*1024*1024) /* user stack size */ 63 #define TSTKTOP (USTKTOP-USTKSIZE) /* sysexec temporary stack */ 64 #define TSTKSIZ 256 65 66 /* address at which to copy and execute rebootcode */ 67 #define REBOOTADDR KADDR(0x100) 68 69 /* 70 * Legacy... 71 */ 72 #define BLOCKALIGN 32 /* only used in allocb.c */ 73 #define KSTACK KSTKSIZE 74 75 /* 76 * Sizes 77 */ 78 #define BI2BY 8 /* bits per byte */ 79 #define BY2SE 4 80 #define BY2WD 4 81 #define BY2V 8 /* only used in xalloc.c */ 82 83 #define CACHELINESZ 64 /* bytes per cache line */ 84 #define PTEMAPMEM (1024*1024) 85 #define PTEPERTAB (PTEMAPMEM/BY2PG) 86 #define SEGMAPSIZE 1984 /* magic 16*124 */ 87 #define SSEGMAPSIZE 16 /* magic */ 88 #define PPN(x) ((x)&~(BY2PG-1)) /* pure page number? */ 89 90 /* 91 * With a little work these move to port. 92 */ 93 #define PTEVALID (1<<0) 94 #define PTERONLY 0 95 #define PTEWRITE (1<<1) 96 #define PTEUNCACHED (1<<2) 97 #define PTEKERNEL (1<<3) 98 99 /* 100 * Physical machine information from here on. 101 */ 102 103 /* gpmc-controlled address space 0—1G */ 104 #define PHYSNAND 1 /* cs0 is onenand flash */ 105 #define PHYSETHER 0x2c000000 106 107 #define PHYSIO 0x48000000 /* L4 ctl */ 108 109 #define PHYSSCM 0x48002000 /* system control module */ 110 111 /* core control pad cfg 0x48002030—0x480021e4, */ 112 /* core control d2d pad cfg 0x480021e4—0x48002264 */ 113 #define PHYSSCMPCONF 0x48002270 /* general device config */ 114 #define PHYSOMAPSTS 0x4800244c /* standalone short: has l2 size */ 115 /* core control pad cfg (2) 0x480025d8—0x480025fc */ 116 #define PHYSSWBOOTCFG 0x48002910 /* sw booting config */ 117 /* wakeup control pad cfg 0x48002a00—0x48002a54 */ 118 119 #define PHYSSCMMPU 0x48004900 /* actually CPU */ 120 #define PHYSSCMCORE 0x48004a00 121 #define PHYSSCMWKUP 0x48004c00 122 #define PHYSSCMPLL 0x48004d00 /* clock ctl for dpll[3-5] */ 123 #define PHYSSCMDSS 0x48004e00 124 #define PHYSSCMPER 0x48005000 125 #define PHYSSCMUSB 0x48005400 126 127 #define PHYSL4CORE 0x48040100 /* l4 ap */ 128 #define PHYSDSS 0x48050000 /* start of dss registers */ 129 #define PHYSDISPC 0x48050400 130 #define PHYSGFX 0x48050480 /* part of dispc */ 131 132 #define PHYSSDMA 0x48056000 /* system dma */ 133 #define PHYSDMA 0x48060000 134 135 #define PHYSUSBTLL 0x48062000 /* usb: transceiver-less link */ 136 #define PHYSUHH 0x48064000 /* usb: `high-speed usb host' ctlr or subsys */ 137 #define PHYSOHCI 0x48064400 /* usb 1.0: slow */ 138 #define PHYSEHCI 0x48064800 /* usb 2.0: medium */ 139 #define PHYSUART0 0x4806a000 140 #define PHYSUART1 0x4806c000 141 #define PHYSMMCHS1 0x4809c000 /* mmc/sdio */ 142 #define PHYSUSBOTG 0x480ab000 /* on-the-go usb */ 143 #define PHYSMMCHS3 0x480ad000 144 #define PHYSMMCHS2 0x480b4000 145 146 #define PHYSINTC 0x48200000 /* interrupt controller */ 147 148 #define PHYSPRMIVA2 0x48206000 /* prm iva2 regs */ 149 /* 48306d40 sys_clkin_sel */ 150 #define PHYSPRMGLBL 0x48307200 /* prm global regs */ 151 #define PHYSPRMWKUSB 0x48307400 152 153 #define PHYSCNTRL 0x4830a200 /* SoC id, etc. */ 154 #define PHYSWDT1 0x4830c000 /* wdt1, not on GP omaps */ 155 156 #define PHYSGPIO1 0x48310000 /* contains dss gpio */ 157 158 #define PHYSWDOG 0x48314000 /* watchdog timer, wdt2 */ 159 #define PHYSWDT2 0x48314000 /* watchdog timer, wdt2 */ 160 #define PHYSTIMER1 0x48318000 161 162 #define PHYSL4WKUP 0x48328100 /* l4 wkup */ 163 #define PHYSL4PER 0x49000100 /* l4 per */ 164 165 #define PHYSCONS 0x49020000 /* uart console (third one) */ 166 167 #define PHYSWDT3 0x49030000 /* wdt3 */ 168 #define PHYSTIMER2 0x49032000 169 #define PHYSTIMER3 0x49034000 170 #define PHYSGPIO5 0x49056000 171 #define PHYSGPIO6 0x49058000 /* contains igep ether gpio */ 172 173 #define PHYSIOEND 0x49100000 /* end of PHYSIO identity map */ 174 175 #define PHYSL4EMU 0x54006100 /* l4 emu */ 176 #define PHYSL4PROT 0x54728000 /* l4 protection regs */ 177 178 #define PHYSL3 0x68000000 /* l3 interconnect control */ 179 #define PHYSL3GPMCCFG 0x68002000 /* l3 gpmc target port agent cfg */ 180 #define PHYSL3USB 0x68004000 /* l3 regs for usb */ 181 #define PHYSL3USBOTG 0x68004400 /* l3 regs for usb otg */ 182 /* (target port) protection registers */ 183 #define PHYSL3PMRT 0x68010000 /* l3 PM register target prot. */ 184 #define PHYSL3GPMCPM 0x68012400 /* l3 gpmc target port protection */ 185 #define PHYSL3OCTRAM 0x68012800 /* l3 ocm ram */ 186 #define PHYSL3OCTROM 0x68012c00 /* l3 ocm rom */ 187 #define PHYSL3MAD2D 0x68013000 /* l3 die-to-die */ 188 #define PHYSL3IVA 0x68014000 /* l3 die-to-die */ 189 190 #define PHYSSMS 0x6c000000 /* cfg regs: sms addr space 2 */ 191 #define PHYSDRC 0x6d000000 /* sdram ctlr, addr space 3 */ 192 #define PHYSGPMC 0x6e000000 /* flash, non-dram memory ctlr */ 193 194 #define PHYSDRAM 0x80000000 195 196 #define VIRTNAND 0x20000000 /* fixed by u-boot */ 197 #define VIRTIO PHYSIO 198