1 /* 2 * arm-specific definitions for cortex-a8 3 * these are used in C and assembler 4 * 5 * `cortex' refers specifically to the cortex-a8. 6 */ 7 8 /* 9 * Program Status Registers 10 */ 11 #define PsrMusr 0x00000010 /* mode */ 12 #define PsrMfiq 0x00000011 13 #define PsrMirq 0x00000012 14 #define PsrMsvc 0x00000013 /* `protected mode for OS' */ 15 #define PsrMmon 0x00000016 /* `secure monitor' (trustzone hyper) */ 16 #define PsrMabt 0x00000017 17 #define PsrMund 0x0000001B 18 #define PsrMsys 0x0000001F /* `privileged user mode for OS' (trustzone) */ 19 #define PsrMask 0x0000001F 20 21 #define PsrDfiq 0x00000040 /* disable FIQ interrupts */ 22 #define PsrDirq 0x00000080 /* disable IRQ interrupts */ 23 24 #define PsrV 0x10000000 /* overflow */ 25 #define PsrC 0x20000000 /* carry/borrow/extend */ 26 #define PsrZ 0x40000000 /* zero */ 27 #define PsrN 0x80000000 /* negative/less than */ 28 29 /* 30 * Coprocessors 31 */ 32 #define CpFP 10 /* float FP, VFP cfg. */ 33 #define CpDFP 11 /* double FP */ 34 #define CpSC 15 /* System Control */ 35 36 /* 37 * Primary (CRn) CpSC registers. 38 */ 39 #define CpID 0 /* ID and cache type */ 40 #define CpCONTROL 1 /* miscellaneous control */ 41 #define CpTTB 2 /* Translation Table Base(s) */ 42 #define CpDAC 3 /* Domain Access Control */ 43 #define CpFSR 5 /* Fault Status */ 44 #define CpFAR 6 /* Fault Address */ 45 #define CpCACHE 7 /* cache/write buffer control */ 46 #define CpTLB 8 /* TLB control */ 47 #define CpCLD 9 /* L2 Cache Lockdown, op1==1 */ 48 #define CpTLD 10 /* TLB Lockdown, with op2 */ 49 #define CpVECS 12 /* vector bases, op1==0, Crm==0, op2s (cortex) */ 50 #define CpPID 13 /* Process ID */ 51 #define CpDTLB 15 /* TLB, L1 cache stuff (cortex) */ 52 53 /* 54 * CpTTB op1==0, Crm==0 opcode2 values. 55 */ 56 #define CpTTB0 0 57 #define CpTTB1 1 /* cortex */ 58 #define CpTTBctl 2 /* cortex */ 59 60 /* 61 * CpFSR op1==0, Crm==0 opcode 2 values. 62 */ 63 #define CpDFSR 0 /* data fault status */ 64 #define CpIFSR 1 /* instruction fault status */ 65 66 /* 67 * CpID Secondary (CRm) registers. 68 */ 69 #define CpIDidct 0 70 71 /* 72 * CpID op1==0 opcode2 fields. 73 * the cortex has more op1 codes for cache size, etc. 74 */ 75 #define CpIDid 0 /* main ID */ 76 #define CpIDct 1 /* cache type */ 77 #define CpIDtlb 3 /* tlb type (cortex) */ 78 #define CpIDmpid 5 /* multiprocessor id (cortex) */ 79 80 /* CpIDid op1 values */ 81 #define CpIDcsize 1 /* cache size (cortex) */ 82 #define CpIDcssel 2 /* cache size select (cortex) */ 83 84 /* 85 * CpCONTROL op2 codes, op1==0, Crm==0. 86 */ 87 #define CpMainctl 0 88 #define CpAuxctl 1 89 #define CpCPaccess 2 90 91 /* 92 * CpCONTROL: op1==0, CRm==0, op2==CpMainctl. 93 * main control register. 94 * cortex/armv7 has more ops and CRm values. 95 */ 96 #define CpCmmu 0x00000001 /* M: MMU enable */ 97 #define CpCalign 0x00000002 /* A: alignment fault enable */ 98 #define CpCdcache 0x00000004 /* C: data cache on */ 99 #define CpCsbo (3<<22|1<<18|1<<16|017<<3) /* must be 1 (armv7) */ 100 #define CpCsbz (CpCtre|1<<26|CpCve|1<<15|7<<7) /* must be 0 (armv7) */ 101 #define CpCsw (1<<10) /* SW: SWP(B) enable (deprecated in v7) */ 102 #define CpCpredict 0x00000800 /* Z: branch prediction (armv7) */ 103 #define CpCicache 0x00001000 /* I: instruction cache on */ 104 #define CpChv 0x00002000 /* V: high vectors */ 105 #define CpCrr (1<<14) /* RR: round robin vs random cache replacement */ 106 #define CpCha (1<<17) /* HA: hw access flag enable */ 107 #define CpCdz (1<<19) /* DZ: divide by zero fault enable */ 108 #define CpCfi (1<<21) /* FI: fast intrs */ 109 #define CpCve (1<<24) /* VE: intr vectors enable */ 110 #define CpCee (1<<25) /* EE: exception endianness */ 111 #define CpCnmfi (1<<27) /* NMFI: non-maskable fast intrs. */ 112 #define CpCtre (1<<28) /* TRE: TEX remap enable */ 113 #define CpCafe (1<<29) /* AFE: access flag (ttb) enable */ 114 115 /* 116 * CpCONTROL: op1==0, CRm==0, op2==CpAuxctl. 117 * Auxiliary control register on cortex at least. 118 */ 119 #define CpACcachenopipe (1<<20) /* don't pipeline cache maint. */ 120 #define CpACcp15serial (1<<18) /* serialise CP1[45] ops. */ 121 #define CpACcp15waitidle (1<<17) /* CP1[45] wait-on-idle */ 122 #define CpACcp15pipeflush (1<<16) /* CP1[45] flush pipeline */ 123 #define CpACneonissue1 (1<<12) /* neon single issue */ 124 #define CpACldstissue1 (1<<11) /* force single issue ld, st */ 125 #define CpACissue1 (1<<10) /* force single issue */ 126 #define CpACnobsm (1<<7) /* no branch size mispredicts */ 127 #define CpACibe (1<<6) /* cp15 invalidate & btb enable */ 128 #define CpACl1neon (1<<5) /* cache neon (FP) data in L1 cache */ 129 #define CpACasa (1<<4) /* enable speculative accesses */ 130 #define CpACl1pe (1<<3) /* l1 cache parity enable */ 131 #define CpACl2en (1<<1) /* l2 cache enable; default 1 */ 132 /* 133 * CpCONTROL Secondary (CRm) registers and opcode2 fields. 134 */ 135 #define CpCONTROLscr 1 136 137 #define CpSCRscr 0 138 139 /* 140 * CpCACHE Secondary (CRm) registers and opcode2 fields. op1==0. 141 * In ARM-speak, 'flush' means invalidate and 'clean' means writeback. 142 */ 143 #define CpCACHEintr 0 /* interrupt (op2==4) */ 144 #define CpCACHEisi 1 /* inner-sharable I cache (v7) */ 145 #define CpCACHEpaddr 4 /* 0: phys. addr (cortex) */ 146 #define CpCACHEinvi 5 /* instruction, branch table */ 147 #define CpCACHEinvd 6 /* data or unified */ 148 // #define CpCACHEinvu 7 /* unified (not on cortex) */ 149 #define CpCACHEva2pa 8 /* va -> pa translation (cortex) */ 150 #define CpCACHEwb 10 /* writeback */ 151 #define CpCACHEinvdse 11 /* data or unified by mva */ 152 #define CpCACHEwbi 14 /* writeback+invalidate */ 153 154 #define CpCACHEall 0 /* entire (not for invd nor wb(i) on cortex) */ 155 #define CpCACHEse 1 /* single entry */ 156 #define CpCACHEsi 2 /* set/index (set/way) */ 157 #define CpCACHEtest 3 /* test loop */ 158 #define CpCACHEwait 4 /* wait (prefetch flush on cortex) */ 159 #define CpCACHEdmbarr 5 /* wb only (cortex) */ 160 #define CpCACHEflushbtc 6 /* flush branch-target cache (cortex) */ 161 #define CpCACHEflushbtse 7 /* ⋯ or just one entry in it (cortex) */ 162 163 /* 164 * CpTLB Secondary (CRm) registers and opcode2 fields. 165 */ 166 #define CpTLBinvi 5 /* instruction */ 167 #define CpTLBinvd 6 /* data */ 168 #define CpTLBinvu 7 /* unified */ 169 170 #define CpTLBinv 0 /* invalidate all */ 171 #define CpTLBinvse 1 /* invalidate single entry */ 172 #define CpTBLasid 2 /* by ASID (cortex) */ 173 174 /* 175 * CpCLD Secondary (CRm) registers and opcode2 fields for op1==0. (cortex) 176 */ 177 #define CpCLDena 12 /* enables */ 178 #define CpCLDcyc 13 /* cycle counter */ 179 #define CpCLDuser 14 /* user enable */ 180 181 #define CpCLDenapmnc 0 182 #define CpCLDenacyc 1 183 184 /* 185 * CpCLD Secondary (CRm) registers and opcode2 fields for op1==1. 186 */ 187 #define CpCLDl2 0 /* l2 cache */ 188 189 #define CpCLDl2aux 2 /* auxiliary control */ 190 191 /* 192 * l2 cache aux. control 193 */ 194 #define CpCl2ecc (1<<28) /* use ecc, not parity */ 195 #define CpCl2noldforw (1<<27) /* no ld forwarding */ 196 #define CpCl2nowrcomb (1<<25) /* no write combining */ 197 #define CpCl2nowralldel (1<<24) /* no write allocate delay */ 198 #define CpCl2nowrallcomb (1<<23) /* no write allocate combine */ 199 #define CpCl2nowralloc (1<<22) /* no write allocate */ 200 #define CpCl2eccparity (1<<21) /* enable ecc or parity */ 201 #define CpCl2inner (1<<16) /* inner cacheability */ 202 /* other bits are tag ram & data ram latencies */ 203 204 /* 205 * CpTLD Secondary (CRm) registers and opcode2 fields. 206 */ 207 #define CpTLDlock 0 /* TLB lockdown registers */ 208 #define CpTLDpreload 1 /* TLB preload */ 209 210 #define CpTLDi 0 /* TLB instr. lockdown reg. */ 211 #define CpTLDd 1 /* " data " " */ 212 213 /* 214 * CpVECS Secondary (CRm) registers and opcode2 fields. 215 */ 216 #define CpVECSbase 0 217 218 #define CpVECSnorm 0 /* (non-)secure base addr */ 219 #define CpVECSmon 1 /* secure monitor base addr */ 220 221 /* 222 * MMU page table entries. 223 * Mbz (0x10) bit is implementation-defined and must be 0 on the cortex. 224 */ 225 #define Mbz (0<<4) 226 #define Fault 0x00000000 /* L[12] pte: unmapped */ 227 228 #define Coarse (Mbz|1) /* L1 */ 229 #define Section (Mbz|2) /* L1 1MB */ 230 #define Fine (Mbz|3) /* L1 */ 231 232 #define Large 0x00000001 /* L2 64KB */ 233 #define Small 0x00000002 /* L2 4KB */ 234 #define Tiny 0x00000003 /* L2 1KB: not in v7 */ 235 #define Buffered 0x00000004 /* L[12]: write-back not -thru */ 236 #define Cached 0x00000008 /* L[12] */ 237 #define Dom0 0 238 239 #define Noaccess 0 /* AP, DAC */ 240 #define Krw 1 /* AP */ 241 /* armv7 deprecates AP[2] == 1 & AP[1:0] == 2 (Uro), prefers 3 (new in v7) */ 242 #define Uro 2 /* AP */ 243 #define Urw 3 /* AP */ 244 #define Client 1 /* DAC */ 245 #define Manager 3 /* DAC */ 246 247 #define AP(n, v) F((v), ((n)*2)+4, 2) 248 #define L1AP(ap) (AP(3, (ap))) 249 #define L2AP(ap) (AP(0, (ap))) /* armv7 */ 250 #define DAC(n, v) F((v), (n)*2, 2) 251 252 #define HVECTORS 0xffff0000 253