1global scale sheevaplug & guruplug 2 3marvell 88f6281 (feroceon kirkwood) SoC 4arm926ej-s rev 1 [56251311] (armv5tejl) 1.2GHz cpu 5 6l1 I & D VIVT caches 16K each: 4-way, 128 sets, 32-byte lines 7 l1 D is write-through, l1 I is write-back 8unified l2 PIPT cache 256K: 4-way, 2048 sets, 32-byte lines 9 potentially 512K: 8-way 10 11apparently the mmu walks the page tables in dram and won't look in the 12l2 cache. there is no hardware cache coherence, thus the l1 caches 13need to be flushed or invalidated when mmu mappings change, but l2 14only needs to be flushed or invalidated around dma operations and page 15table changes, and only the affected dma buffers and descriptors or 16page table entries need to be flushed or invalidated in l2. 17 18we arrange that device registers are uncached. 19 20be aware that cache operations act on cache lines (of CACHELINESZ 21bytes) as atomic units, so if you invalidate one word of a cache line, 22you invalidate the entire cache line, whether it's been written back 23(is clean) or not (is dirty). mixed data structures with parts 24maintained by hardware and other parts by software are especially 25tricky. we try to pad the initial hardware parts so that the software 26parts start in a new cache line. 27 28there are no video controllers so far, so this port is a cpu 29kernel only. 30 31512MB of dram at physical address 0 32512MB of nand flash 3316550 uart for console 34see http://www.marvell.com/files/products/embedded_processors/kirkwood/\ 35 FS_88F6180_9x_6281_OpenSource.pdf, stored locally as 36 /public/doc/marvell/88f61xx.kirkwood.pdf 37 38If you plan to use flash, it would be wise to avoid touching the first 39megabyte, which contains u-boot, right up to 0x100000. There's a 40linux kernel from there to 0x400000, if you care. You'll also likely 41want to use paqfs rather than fossil or kfs for file systems in flash 42since there is no wear-levelling. 43 44The code is fairly heavy-handed with the use of barrier instructions 45(BARRIERS in assembler, coherence in C), partly in reaction to bad 46experience doing Power PC ports, but also just as precautions against 47modern processors, which may feel free to execute instructions out of 48order or some time later, store to memory out of order or some time 49later, otherwise break the model of traditional sequential processors, 50or any combination of the above. 51 52this plan 9 port is based on the port of native inferno to the 53sheevaplug by Salva Peiró (saoret.one@gmail.com) and Mechiel Lukkien 54(mechiel@ueber.net). 55 56___ 57 58# type this once at u-boot, replacing 00504301c49e with your plug's 59# mac address; thereafter the plug will pxe boot: 60setenv bootdelay 2 61setenv bootcmd 'bootp; bootp; tftp 0x1000 /cfg/pxe/00504301c49e; bootp; tftp 0x800000; go 0x800000' 62saveenv 63 64# see /cfg/pxe/example-kw 65 66 67 physical mem map 68 69hex addr size what 70---- 710 512MB sdram 72c8010000 2K cesa sram 73 74 virtual mem map (from cpu address map & mmu mappings) 75 76hex addr size what 77---- 780 512MB user process address space 7960000000 512MB kzero, mapped to 0 8090000000 256MB pcie mem # identity mapped by u-boot 81d0000000 1MB internal regs default address at reset 82d8000000 128MB nand flash # 512MB addressed through this (guru) 83f0000000 16MB pcie i/o # mapped to 0xc0000000 by u-boot 84f1000000 1MB internal regs (on-chip devices) as mapped by u-boot 85f1000000 64K dram regs 86f1010000 64K uart, flashes, rtc, gpio, etc. 87f1030000 64K crypto accelerator (cesa) 88f1040000 64K pcie regs 89f1050000 64K usb otg regs (ehci-like) 90f1070000 64K gbe regs 91f1080000 64K non-ahci sata regs 92f1090000 64K sdio regs 93f8000000 16MB spi flash # mapped to 0 by u-boot 94f9000000 8MB nand flash # identity mapped by u-boot (sheeva/openrd) 95fb000000 64KB crypto engine # identity mapped by u-boot 96ff000000 16MB boot rom # identity mapped by u-boot 97... as per physical map 98