1/* 2 * sheevaplug machine assist, definitions 3 * arm926ej-s processor at 1.2GHz 4 * 5 * loader uses R11 as scratch. 6 */ 7#include "mem.h" 8#include "arm.h" 9 10#undef B /* B is for 'botch' */ 11 12#define PADDR(a) ((a) & ~KZERO) 13#define KADDR(a) (KZERO|(a)) 14 15#define L1X(va) (((((va))>>20) & 0x0fff)<<2) 16 17#define MACHADDR (L1-MACHSIZE) 18 19#define PTEDRAM (Dom0|L1AP(Krw)|Section|Cached|Buffered) 20#define PTEIO (Dom0|L1AP(Krw)|Section) 21 22/* wave at the user; clobbers R1 & R7; needs R12 (SB) set */ 23#define PUTC(c) \ 24 ISB; \ 25 MOVW $PHYSCONS, R7; \ 26 MOVW $(c), R1; \ 27 MOVW R1, (R7); \ 28 ISB 29 30/* new instructions */ 31#define CLZ(s, d) WORD $(0xe16f0f10 | (d) << 12 | (s)) /* count leading 0s */ 32 33#define DMB \ 34 MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEwb), CpCACHEdmbarr 35/* 36 * data synchronisation barrier (formerly drain write buffer). 37 * waits for cache flushes, eviction buffer drain, tlb flushes, 38 * branch-prediction flushes, writes to memory; the lot. 39 * on sheeva, also flushes L2 eviction buffer. 40 * zeroes R0. 41 */ 42#define DSB \ 43 MOVW $0, R0; \ 44 MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEwb), CpCACHEwait 45/* 46 * prefetch flush; zeroes R0. 47 * arm926ej-s manual says we need to sync with l2 cache in isb, 48 * and uncached load is the easiest way. doesn't seem to matter. 49 */ 50#define ISB \ 51 MOVW $0, R0; \ 52 MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEwait 53// MOVW (R0), R0; MOVW $0, R0 54 55/* zeroes R0 */ 56#define BARRIERS ISB; DSB 57 58/* 59 * invoked with PTE bits in R2, pa in R3, PTE pointed to by R4. 60 * fill PTE pointed to by R4 and increment R4 past it. 61 * increment R3 by a MB. clobbers R1. 62 */ 63#define FILLPTE() \ 64 ORR R3, R2, R1; /* pte bits in R2, pa in R3 */ \ 65 MOVW R1, (R4); \ 66 ADD $4, R4; /* bump PTE address */ \ 67 ADD $MiB, R3; /* bump pa */ \ 68 69/* zero PTE pointed to by R4 and increment R4 past it. assumes R0 is 0. */ 70#define ZEROPTE() \ 71 MOVW R0, (R4); \ 72 ADD $4, R4; /* bump PTE address */ 73