xref: /plan9-contrib/sys/src/nboot/bitsy/uart.c (revision 529c1f209803c78c4f2cda11b13818a57f01c872)
1*529c1f20SDavid du Colombier #include	"u.h"
2*529c1f20SDavid du Colombier #include	"lib.h"
3*529c1f20SDavid du Colombier #include	"mem.h"
4*529c1f20SDavid du Colombier #include	"dat.h"
5*529c1f20SDavid du Colombier #include	"fns.h"
6*529c1f20SDavid du Colombier #include	"io.h"
7*529c1f20SDavid du Colombier 
8*529c1f20SDavid du Colombier enum
9*529c1f20SDavid du Colombier {
10*529c1f20SDavid du Colombier 	/* ctl[0] bits */
11*529c1f20SDavid du Colombier 	Parity=		1<<0,
12*529c1f20SDavid du Colombier 	Even=		1<<1,
13*529c1f20SDavid du Colombier 	Stop2=		1<<2,
14*529c1f20SDavid du Colombier 	Bits8=		1<<3,
15*529c1f20SDavid du Colombier 	SCE=		1<<4,	/* synchronous clock enable */
16*529c1f20SDavid du Colombier 	RCE=		1<<5,	/* rx on falling edge of clock */
17*529c1f20SDavid du Colombier 	TCE=		1<<6,	/* tx on falling edge of clock */
18*529c1f20SDavid du Colombier 
19*529c1f20SDavid du Colombier 	/* ctl[3] bits */
20*529c1f20SDavid du Colombier 	Rena=		1<<0,	/* receiver enable */
21*529c1f20SDavid du Colombier 	Tena=		1<<1,	/* transmitter enable */
22*529c1f20SDavid du Colombier 	Break=		1<<2,	/* force TXD3 low */
23*529c1f20SDavid du Colombier 	Rintena=	1<<3,	/* enable receive interrupt */
24*529c1f20SDavid du Colombier 	Tintena=	1<<4,	/* enable transmitter interrupt */
25*529c1f20SDavid du Colombier 	Loopback=	1<<5,	/* loop back data */
26*529c1f20SDavid du Colombier 
27*529c1f20SDavid du Colombier 	/* data bits */
28*529c1f20SDavid du Colombier 	DEparity=	1<<8,	/* parity error */
29*529c1f20SDavid du Colombier 	DEframe=	1<<9,	/* framing error */
30*529c1f20SDavid du Colombier 	DEoverrun=	1<<10,	/* overrun error */
31*529c1f20SDavid du Colombier 
32*529c1f20SDavid du Colombier 	/* status[0] bits */
33*529c1f20SDavid du Colombier 	Tint=		1<<0,	/* transmit fifo half full interrupt */
34*529c1f20SDavid du Colombier 	Rint0=		1<<1,	/* receiver fifo 1/3-2/3 full */
35*529c1f20SDavid du Colombier 	Rint1=		1<<2,	/* receiver fifo not empty and receiver idle */
36*529c1f20SDavid du Colombier 	Breakstart=	1<<3,
37*529c1f20SDavid du Colombier 	Breakend=	1<<4,
38*529c1f20SDavid du Colombier 	Fifoerror=	1<<5,	/* fifo error */
39*529c1f20SDavid du Colombier 
40*529c1f20SDavid du Colombier 	/* status[1] bits */
41*529c1f20SDavid du Colombier 	Tbusy=		1<<0,	/* transmitting */
42*529c1f20SDavid du Colombier 	Rnotempty=	1<<1,	/* receive fifo not empty */
43*529c1f20SDavid du Colombier 	Tnotfull=	1<<2,	/* transmit fifo not full */
44*529c1f20SDavid du Colombier 	ParityError=	1<<3,
45*529c1f20SDavid du Colombier 	FrameError=	1<<4,
46*529c1f20SDavid du Colombier 	Overrun=	1<<5,
47*529c1f20SDavid du Colombier };
48*529c1f20SDavid du Colombier 
49*529c1f20SDavid du Colombier Uartregs *uart3regs = (Uartregs*)UART3REGS;
50*529c1f20SDavid du Colombier 
51*529c1f20SDavid du Colombier 
52*529c1f20SDavid du Colombier /*
53*529c1f20SDavid du Colombier  *  for iprint, just write it
54*529c1f20SDavid du Colombier  */
55*529c1f20SDavid du Colombier void
serialputs(char * str,int n)56*529c1f20SDavid du Colombier serialputs(char *str, int n)
57*529c1f20SDavid du Colombier {
58*529c1f20SDavid du Colombier 	Uartregs *ur;
59*529c1f20SDavid du Colombier 
60*529c1f20SDavid du Colombier 	ur = uart3regs;
61*529c1f20SDavid du Colombier 	while(n-- > 0){
62*529c1f20SDavid du Colombier 		/* wait for output ready */
63*529c1f20SDavid du Colombier 		while((ur->status[1] & Tnotfull) == 0)
64*529c1f20SDavid du Colombier 			;
65*529c1f20SDavid du Colombier 		ur->data = *str++;
66*529c1f20SDavid du Colombier 	}
67*529c1f20SDavid du Colombier 	while((ur->status[1] & Tbusy))
68*529c1f20SDavid du Colombier 		;
69*529c1f20SDavid du Colombier }
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